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White Rabbit core collection
Commit 9dfd9435 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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added GSI'S Scalable Control Unit demo design (initial commit)

parent 5d852cc7
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syn/gsi_scu/wr_core_demo/Manifest.py 0 → 100644
View file @ 9dfd9435
target = "altera"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "ep2agx125ef"
syn_grade = "c5"
syn_package = "29"
syn_top = "exploder_ng"
syn_project = "exploder_ng"
modules = {"local" : [ "../../../", "../../../top/gsi_scu/wr_core_demo"]}
\ No newline at end of file
syn/gsi_scu/wr_core_demo/exploder_ng.qsf 0 → 100644
View file @ 9dfd9435
set_global_assignment -name FAMILY "Arria II GX"
set_global_assignment -name DEVICE EP2AGX125EF29C5
set_global_assignment -name TOP_LEVEL_ENTITY exploder_ng
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:49:21 FEBRUARY 02, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
set_global_assignment -name SEARCH_PATH ./
set_global_assignment -name SEARCH_PATH "pci_express_compiler-library/"
set_global_assignment -name SEARCH_PATH "pci_megacore-library/"
set_global_assignment -name SEARCH_PATH "ddr2_sdram_controller-library/"
set_global_assignment -name SEARCH_PATH .
set_global_assignment -name SEARCH_PATH "ip_compiler_for_pci_express-library"
set_global_assignment -name SEARCH_PATH "../wr-cores/ip_cores/general-cores/modules/common/"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT ANY
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR scu_pcie_ddr3 -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT BSDL -section_id eda_board_design_boundary_scan
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_Y10 -to nres
set_global_assignment -name SMART_RECOMPILE ON
set_location_assignment PIN_N3 -to clk_20m_vcxo_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_20m_vcxo_i
set_location_assignment PIN_M1 -to clk_125m_pllref_p
set_instance_assignment -name IO_STANDARD LVDS -to clk_125m_pllref_p
set_location_assignment PIN_N1 -to "clk_125m_pllref_p(n)"
set_location_assignment PIN_AE15 -to L_CLKp
set_instance_assignment -name IO_STANDARD LVDS -to L_CLKp
set_location_assignment PIN_AF15 -to "L_CLKp(n)"
set_location_assignment PIN_AE6 -to uart_rxd_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nres
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_rxd_i
set_location_assignment PIN_AF6 -to uart_txd_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd_o
set_location_assignment PIN_AF2 -to serial_to_cb_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to serial_to_cb_o
set_location_assignment PIN_U27 -to sfp_rxp_i
set_location_assignment PIN_AH17 -to sfp_tx_disable_o
set_location_assignment PIN_T25 -to sfp_txp_o
set_global_assignment -name VHDL_FILE ../../../modules/fabric/wr_fabric_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/pow_reset.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/fabric/xwb_fabric_source.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_tbi_phy/dec_8b10b.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_tbi_phy/enc_8b10b.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_tbi_phy/disparity_gen_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/timing/dmtd_phase_meas.vhd
set_global_assignment -name VHDL_FILE ../../../modules/timing/dmtd_with_deglitcher.vhd
set_global_assignment -name VHDL_FILE ../../../modules/timing/multi_dmtd_with_deglitcher.vhd
set_global_assignment -name VHDL_FILE ../../../modules/timing/hpll_period_detect.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_mini_nic/minic_packet_buffer.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wrc_syscon_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_mini_nic/xwr_mini_nic.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll/softpll_wb.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll/wr_softpll.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll/xwr_softpll.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_registers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/endpoint_private_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_autonegotiation.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_1000basex_pcs.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_crc_size_check.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_bypass_queue.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_path.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_wb_master.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_oob_insert.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_early_address_match.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_tx_framer.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_packet_filter.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_vlan_unit.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_ts_counter.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_timestamping_unit.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_leds_controller.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rtu_header_extract.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_buffer.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_sync_detect.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_sync_detect_16bit.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_wishbone_controller.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/endpoint_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/wr_endpoint.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/xwr_endpoint.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_pps_gen/pps_gen_wb.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_pps_gen/wr_pps_gen.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_pps_gen/xwr_pps_gen.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wrcore_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wr_core.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wrc_dpram.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/exploder_ng.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wrc_periph.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wb_reset.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wbp_mux.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wrc_syscon_wb.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/xwr_core.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/xwr_syscon_wb.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/wr_gxb_phy_arria2/altgx_reconf.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/wr_gxb_phy_arria2/arria_phy.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/wr_gxb_phy_arria2/wr_gxb_phy_arriaii.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_tbi_phy/wr_tbi_phy.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
set_global_assignment -name VHDL_FILE ../../../modules/fabric/xwb_fabric_sink.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_mini_nic/wr_mini_nic.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_mini_nic/minic_wb_slave.vhd
set_global_assignment -name VHDL_FILE ../../../modules/mini_bone/mini_bone.vhd
set_global_assignment -name VHDL_FILE ../../../modules/mini_bone/xmini_bone.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_location_assignment PIN_H4 -to leds_o[0]
set_location_assignment PIN_J5 -to leds_o[1]
set_location_assignment PIN_H3 -to leds_o[2]
set_location_assignment PIN_J4 -to leds_o[3]
\ No newline at end of file
top/gsi_scu/wr_core_demo/Manifest.py 0 → 100644
View file @ 9dfd9435
modules = {"local" : "../../../modules/mini_bone"}
files = ["exploder_ng.vhd", "pow_reset.vhd"]
\ No newline at end of file
top/gsi_scu/wr_core_demo/exploder_ng.vhd 0 → 100644
View file @ 9dfd9435
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
library work;
use work.wishbone_pkg.all;
entity EXPLODER_ng is
port
(
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p : in std_logic; -- 125 MHz PLL reference
L_CLKp : in std_logic; -- local clk from 125Mhz oszillator
nres : in std_logic; -- powerup reset
-----------------------------------------
--UART
-----------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
serial_to_cb_o : out std_logic;
sfp_tx_disable_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_rxp_i : in std_logic;
leds_o : out std_logic_vector(3 downto 0)
);
end EXPLODER_ng;
architecture rtl of EXPLODER_ng is
component pow_reset is
port (
clk : in std_logic; -- 125Mhz
nreset : buffer std_logic
);
end component;
component wr_gxb_phy_arriaii
generic (
g_simulation : integer;
g_force_disparity : integer);
port (
clk_reconf_i : in std_logic;
clk_ref_i : in std_logic;
tx_clk_o : out std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic;
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
component xwr_core is
generic(
g_simulation : integer := 0;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_ep_rxbuf_size : integer := 12;
g_dpram_initf : string := "";
g_dpram_size : integer := 16384; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic;
rst_n_i : in std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
led_red_o : out std_logic;
led_green_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
btn1_i : in std_logic;
btn2_i : in std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
owr_en_o : out std_logic;
owr_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic := '0';
tm_clk_aux_locked_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic
);
end component;
component xmini_bone
generic (
g_class_mask : std_logic_vector(7 downto 0);
g_our_ethertype : std_logic_vector(15 downto 0));
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- Reset
signal rst_a : std_logic;
signal rst : std_logic;
-- SPI
signal spi_slave_select : std_logic_vector(7 downto 0);
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_fb_dmtd : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal dac_rst_n : std_logic;
signal led_divider : unsigned(23 downto 0);
signal wrc_scl_o : std_logic;
signal wrc_scl_i : std_logic;
signal wrc_sda_o : std_logic;
signal wrc_sda_i : std_logic;
signal dio : std_logic_vector(3 downto 0);
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic;
signal phy_tx_clk : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic;
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_clk : std_logic;
signal local_reset_n : std_logic;
signal button1_synced : std_logic_vector(2 downto 0);
signal wrc_slave_in : t_wishbone_slave_in;
signal wrc_slave_out : t_wishbone_slave_out;
signal nreset : std_logic := '0';
signal clk_reconf : std_logic;
signal divctr : unsigned(3 downto 0);
signal mb_src_out : t_wrf_source_out;
signal mb_src_in : t_wrf_source_in;
signal mb_snk_out : t_wrf_sink_out;
signal mb_snk_in : t_wrf_sink_in;
signal mb_master_out : t_wishbone_master_out;
signal mb_master_in : t_wishbone_master_in;
signal dummy_gpio, gpio_out : std_logic_vector(31 downto 0);
begin
process(l_clkp)
begin
if rising_edge(L_CLKp) then
divctr <= divctr + 1;
end if;
end process;
-- this is ugly, use PLL instead, I'm too lazy.
clk_reconf <= std_logic(divctr(3));
serial_to_cb_o <= '0';
wrc_slave_in.cyc <= '0';
sfp_tx_disable_o <= '0';
reset : pow_reset
port map (
clk => l_cLKp,
nreset => nreset
);
U_WR_CORE : xwr_core
generic map (
g_simulation => 0,
g_phys_uart => true,
g_virtual_uart => false,
g_ep_rxbuf_size => 4096,
g_dpram_initf => "",
g_dpram_size => 16384,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => l_cLKp,
clk_dmtd_i => l_cLKp,
clk_ref_i => l_cLKp,
clk_aux_i => '0',
rst_n_i => nreset,
phy_ref_clk_i => phy_tx_clk,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
scl_i => '0',
sda_i => '0',
btn1_i => '0',
btn2_i => '0',
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
owr_i => '0',
slave_i => wrc_slave_in,
slave_o => wrc_slave_out,
wrf_src_i => mb_snk_out,
wrf_src_o => mb_snk_in,
wrf_snk_i => mb_src_out,
wrf_snk_o => mb_src_in
);
U_Altera_PHY : wr_gxb_phy_arriaii
generic map (
g_simulation => 0,
g_force_disparity => 1)
port map (
clk_reconf_i => clk_reconf,
clk_ref_i => l_cLKp,
tx_clk_o => phy_tx_clk,
tx_data_i => phy_tx_data,
tx_k_i => phy_tx_k,
tx_disparity_o => phy_tx_disparity,
tx_enc_err_o => phy_tx_enc_err,
rx_rbclk_o => phy_rx_rbclk,
rx_data_o => phy_rx_data,
rx_k_o => phy_rx_k,
rx_enc_err_o => phy_rx_enc_err,
rx_bitslide_o => phy_rx_bitslide,
rst_i => phy_rst,
loopen_i => '0',
pad_txp_o => sfp_txp_o,
pad_rxp_i => sfp_rxp_i);
U_mbone : xmini_bone
generic map (
g_class_mask => x"f0",
g_our_ethertype => x"a0a0")
port map (
clk_sys_i => l_cLKp,
rst_n_i => nreset,
src_o => mb_src_out,
src_i => mb_src_in,
snk_o => mb_snk_out,
snk_i => mb_snk_in,
master_o => mb_master_out,
master_i => mb_master_in);
U_GPIO : xwb_gpio_port
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_pins => 32,
g_with_builtin_tristates => false)
port map (
clk_sys_i => l_cLKp,
rst_n_i => nreset,
slave_i => mb_master_out,
slave_o => mb_master_in,
gpio_b => dummy_gpio,
gpio_out_o => gpio_out,
gpio_in_i => x"00000000");
leds_o <= gpio_out(3 downto 0);
end rtl;
top/gsi_scu/wr_core_demo/pow_reset.vhd 0 → 100644
View file @ 9dfd9435
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pow_reset is
port (
clk : in std_logic; -- 125Mhz
nreset : buffer std_logic
);
end entity;
architecture pow_reset_arch of pow_reset is
signal powerOn : unsigned(6 downto 0) := "0000000"; -- 7Bit for 1ms nrst
begin
nres : process(Clk)
begin
if Clk'event and Clk = '1' then
if nreset = '0' then
powerOn <= powerOn + 1;
end if;
nReset <= std_logic(powerOn(powerON'high));
end if;
end process;
end architecture;
top/readme_platforms.txt 0 → 100644
View file @ 9dfd9435
Available device plaftorms (so far):
------------------------------------
gsi_scu - GSI's Scalable Control Unit (SCU), based on Altera ArriaII-GX (EP2AGX125)
spec_1_1 - CERN's Simple PCI-Express Carrier (SPEC), based on Xilinx Spartan-6 (XC6SLX45). Version 1.1 or newer (pin-compatible)
\ No newline at end of file
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