Commit 9dfd9435 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

added GSI'S Scalable Control Unit demo design (initial commit)

parent 5d852cc7
target = "altera"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "ep2agx125ef"
syn_grade = "c5"
syn_package = "29"
syn_top = "exploder_ng"
syn_project = "exploder_ng"
modules = {"local" : [ "../../../", "../../../top/gsi_scu/wr_core_demo"]}
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modules = {"local" : "../../../modules/mini_bone"}
files = ["exploder_ng.vhd", "pow_reset.vhd"]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pow_reset is
port (
clk : in std_logic; -- 125Mhz
nreset : buffer std_logic
end entity;
architecture pow_reset_arch of pow_reset is
signal powerOn : unsigned(6 downto 0) := "0000000"; -- 7Bit for 1ms nrst
nres : process(Clk)
if Clk'event and Clk = '1' then
if nreset = '0' then
powerOn <= powerOn + 1;
end if;
nReset <= std_logic(powerOn(powerON'high));
end if;
end process;
end architecture;
Available device plaftorms (so far):
gsi_scu - GSI's Scalable Control Unit (SCU), based on Altera ArriaII-GX (EP2AGX125)
spec_1_1 - CERN's Simple PCI-Express Carrier (SPEC), based on Xilinx Spartan-6 (XC6SLX45). Version 1.1 or newer (pin-compatible)
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