Skip to content

W
White Rabbit core collection
Commit 9aa94408 authored by Guido Visser's avatar Guido Visser Committed by Peter Jansweijer
Browse files
Options

test crap

parent 241ee64f
Pipeline #338 failed with stages
      in 2 minutes
      Hide whitespace changes
      Inline Side-by-side
      Showing with 29 additions and 11 deletions
      top/spec7_write_design/spec7_write_top.vhd
      View file @ 9aa94408
      ......@@ -91,9 +91,9 @@ entity spec7_write_top is
      -- SPI interface to DACs
      ---------------------------------------------------------------------------
      --dac_refclk_cs_n_o : out std_logic;
      --dac_refclk_sclk_o : out std_logic;
      --dac_refclk_din_o : out std_logic;
      dac_refclk_cs_n_o : out std_logic;
      dac_refclk_sclk_o : out std_logic;
      dac_refclk_din_o : out std_logic;
      dac_refclk_sclk_p_o : out std_logic;
      dac_refclk_sclk_n_o : out std_logic;
      ......@@ -272,8 +272,8 @@ architecture top of spec7_write_top is
      signal dac_refclk_sclk : std_logic;
      signal dac_refclk_din : std_logic;
      signal dac_refclk_cs_n : std_logic;
      signal dac_refclk_cs_n : std_logic;
      -- clock and reset
      -- signal clk_125m_pllref : std_logic;
      signal clk_sys_62m5 : std_logic;
      ......@@ -559,6 +559,24 @@ AXI2WB : xwb_axi4lite_bridge
      O => dac_refclk_cs_n_p_o,
      OB => dac_refclk_cs_n_n_o);
      -- test crap should be turn off when using the hpspec it was just voor testing tbat the FMC io was working
      -- Now it wil tune the on board vcxo when running in slave.
      dac_refclk_sclk_single : OBUF
      port map (
      I => dac_refclk_sclk,
      O => dac_refclk_sclk_o);
      dac_refclk_din_single : OBUF
      port map (
      I => dac_refclk_din,
      O => dac_refclk_din_o);
      dac_refclk_cs_single : OBUF
      port map (
      I => dac_refclk_cs_n,
      O => dac_refclk_cs_n_o);
      -- end test crap
      -- Type of PPS_IN input:
      -- Differential LVDS
      -- Or
      ......
      top/spec7_write_design/spec7_write_top.xdc
      View file @ 9aa94408
      ......@@ -70,12 +70,12 @@ set_property IOSTANDARD LVCMOS18 [get_ports dac_dmtd_sclk_o]
      set_property PACKAGE_PIN F12 [get_ports dac_dmtd_cs_n_o]
      set_property IOSTANDARD LVCMOS18 [get_ports dac_dmtd_cs_n_o]
      #set_property PACKAGE_PIN D11 [get_ports dac_refclk_din_o]
      #set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_din_o]
      #set_property PACKAGE_PIN F10 [get_ports dac_refclk_sclk_o]
      #set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_sclk_o]
      #set_property PACKAGE_PIN D10 [get_ports dac_refclk_cs_n_o]
      #set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_cs_n_o]
      set_property PACKAGE_PIN D11 [get_ports dac_refclk_din_o]
      set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_din_o]
      set_property PACKAGE_PIN F10 [get_ports dac_refclk_sclk_o]
      set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_sclk_o]
      set_property PACKAGE_PIN D10 [get_ports dac_refclk_cs_n_o]
      set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_cs_n_o]
      # To control the DAC on the HPSEC the dac signals are routed via the FMC connector.
      # See below for the pins definitions.
      ......
      Markdown is supported
      0% or
      You are about to add 0 people to the discussion. Proceed with caution.
      Finish editing this message first!
      Please register or to comment