Skip to content

W
White Rabbit core collection
Commit 98ffca2b authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag Committed by Grzegorz Daniluk
Browse files
Options

Work in progress. Rx tb will soon be deleted. Tx tb will be main one. Tx… 

Work in progress. Rx tb will soon be deleted. Tx tb will be main one. Tx features testing working. Rx features must be fixed and also features relating to link quality (delay, drop frames, etx)
parent ad07295d
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 3486 additions and 59 deletions
testbench/wr_streamers/rx-streamer-tb/include/if_wb_link.svh 0 → 100644
View file @ 98ffca2b
interface IWishboneLink;
parameter g_data_width = 32;
parameter g_addr_width = 32;
wire [g_addr_width - 1 : 0] adr;
wire [g_data_width - 1 : 0] dat_o;
wire [g_data_width - 1 : 0] dat_i;
wire [(g_data_width/8)-1 : 0] sel;
wire ack;
wire stall;
wire err;
wire rty;
wire cyc;
wire stb;
wire we;
modport slave
(
output adr,
output dat_o,
input dat_i,
output sel,
output cyc,
output stb,
output we,
input ack,
input stall,
input err,
input rty
);
modport master
(
input adr,
input dat_o,
output dat_i,
input sel,
input cyc,
input stb,
input we,
output ack,
output stall,
output err,
output rty
);
endinterface // IWishboneLink
testbench/wr_streamers/rx-streamer-tb/include/mainold-2.sv 0 → 100644
View file @ 98ffca2b
This diff is collapsed.
testbench/wr_streamers/rx-streamer-tb/include/mainold.sv 0 → 100644
View file @ 98ffca2b
This diff is collapsed.
testbench/wr_streamers/rx-streamer-tb/include/tb_data_gen_send.sv 0 → 100644
View file @ 98ffca2b
class CGENERATE_AND_SEND
// Generate a block of data words of random size, containing subsequent
// numbers
/////////////////////////////////////////////////////////////////////////////
task automatic generate_block(ref block_t blk);
int size = $dist_uniform(seed, g_block_size_min, g_block_size_max);
int i;
for(i = 0; i<size; i++)
begin
if (i == 0)
blk.first_wrd = tx_counter_val; // Copy first word
if (i == size-1)
blk.last_wrd = tx_counter_val; // Copy last word
blk.words.push_back(tx_counter_val++); //
if (i == 0 || i==size-1)
blk.wrd_cnt.push_back(i+1);// first or last words
else
blk.wrd_cnt.push_back(0); // All other words
end //for loop
endtask // generate_block
////////////////////////////////////////////////////////
task automatic generate_frame(ref streamer_frame_t frm);
int size = $dist_uniform(seed, g_frame_size_min, g_frame_size_max);
int i;
block_t blk;
for(i = 0; i<size; i++)
begin
blk.words = {};
blk.wrd_cnt = {};
generate_block(blk);
frm.blocks.push_back(blk);
end
endtask
// Sends out a data block (blk) by driving TX_(DVALID, DATA, LAST) lines
// of the TX streamer
/////////////////////////////////////////////////////////////////////////////
task automatic send_block(ref block_t blk);
int i = 0;
////$display("Sending block of %d words...", blk.words.data.size());
while(i < blk.words.size())
begin
if(tx_streamer_dreq) begin
// assert the TX_LAST line on the last word in the current block
tx_streamer_last <= (i == (blk.words.size() - 1)) ? 1 : 0;
tx_streamer_data <= blk.words[i];
//$display("Data to be sent is %d*****\n", tx_streamer_data);
tx_streamer_dvalid <= 1;
i++;
end else
tx_streamer_dvalid <= 0;
@(posedge clk);
end // while (i < blk.words.data.size())
tx_streamer_dvalid <= 0;
tx_streamer_last <= 0;
@(posedge clk);
endtask // send_block
///////////////////////////////////////////////////////////////////
task automatic send_frame(ref streamer_frame_t frm);
int i = 0;
while (i < frm.blocks.size()) begin
send_block(frm.blocks[i]);
i++;
end
endtask
endclass
\ No newline at end of file
testbench/wr_streamers/rx-streamer-tb/include/tb_wr_fabric_link_control.sv 0 → 100644
View file @ 98ffca2b
//-----------------------------------------------------------------------------
// Title : Definitions for WR streamers testbench
// Project : White Rabbit Cores
// URL : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
//-----------------------------------------------------------------------------
// File : wr-streamers-tb-class.sv
// Author(s) : Denia Bouhired <denia.bouhired@cern.ch>
// Company : CERN (BE-CO-HT)
// Created : 2017-04-28
//-----------------------------------------------------------------------------
// Description:
//
// SystemVerilog package with all definitions, interfaces, etc. necessary
// for the wr streamers testbench.
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2017 CERN
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.gnu.org/licenses/lgpl-2.1.html
//
//-----------------------------------------------------------------------------
//`include "../../../sim/if_wb_link.svh"
class CWRFABRIC_LINK_CTRL;
int data_width, addr_width;
IWishboneLink in;
IWishboneLink out;
//Class constructor
function new ();
// this.out() = this.in();
// this.in.g_data_width = data_width;
// this.in.g_addr_width = addr_width;
// this.out.g_data_width = data_width;
// this.out.g_addr_width = addr_width;
endfunction //new
//
function corrupt_data ();
in();
out();
endfunction
function drop_frames ();
in();
out();
endfunction //drop_frames
function break_link ();
in();
out();
endfunction //break_link
endclass;
// Transmitter class
// class CWRSTREAMERS_TX extends CWRSTREAMERS;
// function
// endclass;
// Receiver class
// class CWRSTREAMERS_RX extends CWRSTREAMERS;
// endclass;
testbench/wr_streamers/rx-streamer-tb/main.sv
View file @ 98ffca2b
......@@ -189,7 +189,6 @@ module main;
tx_streamer
#(
.g_data_width (g_word_width),
.g_tx_buffer_size(2*g_tx_thr),
.g_tx_threshold (g_tx_thr),
.g_tx_timeout (g_tx_tm_out),
......@@ -422,7 +421,7 @@ task automatic drop_frame ();
drop_frm = 0;
endtask //drop_frame
// end
task automatic delay_frame ();
......
testbench/wr_streamers/rx-streamer-tb/tcl_stacktrace.txt
View file @ 98ffca2b
......@@ -23,3 +23,28 @@ Trace back: invalid command name ""
("after" script)
<2: ::tkerror {invalid command name ""}
<1: ::bgerror {invalid command name ""}
Wed May 24 15:41:46 W. Europe Daylight Time 2017
Trace back: invalid command name ""
while executing
"$tree expandeditems -worm"
(procedure "_resetTree" line 6)
invoked from within
"_resetTree $w"
(procedure "QObjects::sort" line 4)
invoked from within
"QObjects::sort .main_pane.objects 0 ascending"
("eval" body line 1)
invoked from within
"eval $itk_option(-sortcommand) $column $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::sort" body line 26)
invoked from within
"sort $sortIdx $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::_initializeSortColumn" body line 10)
invoked from within
"::.main_pane.objects.interior.cs.body.tree _initializeSortColumn"
(in namespace inscope "::vsimwidgets::Hierarchy" script line 1)
invoked from within
"namespace inscope ::vsimwidgets::Hierarchy {::.main_pane.objects.interior.cs.body.tree _initializeSortColumn}"
("after" script)
<2: ::tkerror {invalid command name ""}
<1: ::bgerror {invalid command name ""}
testbench/wr_streamers/tx-streamer-tb/include/if_wb_link.svh 0 → 100644
View file @ 98ffca2b
interface IWishboneLink;
parameter g_data_width = 32;
parameter g_addr_width = 32;
wire [g_addr_width - 1 : 0] adr;
wire [g_data_width - 1 : 0] dat_o;
wire [g_data_width - 1 : 0] dat_i;
wire [(g_data_width/8)-1 : 0] sel;
wire ack;
wire stall;
wire err;
wire rty;
wire cyc;
wire stb;
wire we;
modport slave
(
output adr,
output dat_o,
input dat_i,
output sel,
output cyc,
output stb,
output we,
input ack,
input stall,
input err,
input rty
);
modport master
(
input adr,
input dat_o,
output dat_i,
input sel,
input cyc,
input stb,
input we,
output ack,
output stall,
output err,
output rty
);
endinterface // IWishboneLink
testbench/wr_streamers/tx-streamer-tb/include/mainold-2.sv 0 → 100644
View file @ 98ffca2b
This diff is collapsed.
testbench/wr_streamers/tx-streamer-tb/include/mainold.sv 0 → 100644
View file @ 98ffca2b
This diff is collapsed.
testbench/wr_streamers/tx-streamer-tb/include/tb_data_gen_send.sv 0 → 100644
View file @ 98ffca2b
class CGENERATE_AND_SEND
// Generate a block of data words of random size, containing subsequent
// numbers
/////////////////////////////////////////////////////////////////////////////
task automatic generate_block(ref block_t blk);
int size = $dist_uniform(seed, g_block_size_min, g_block_size_max);
int i;
for(i = 0; i<size; i++)
begin
if (i == 0)
blk.first_wrd = tx_counter_val; // Copy first word
if (i == size-1)
blk.last_wrd = tx_counter_val; // Copy last word
blk.words.push_back(tx_counter_val++); //
if (i == 0 || i==size-1)
blk.wrd_cnt.push_back(i+1);// first or last words
else
blk.wrd_cnt.push_back(0); // All other words
end //for loop
endtask // generate_block
////////////////////////////////////////////////////////
task automatic generate_frame(ref streamer_frame_t frm);
int size = $dist_uniform(seed, g_frame_size_min, g_frame_size_max);
int i;
block_t blk;
for(i = 0; i<size; i++)
begin
blk.words = {};
blk.wrd_cnt = {};
generate_block(blk);
frm.blocks.push_back(blk);
end
endtask
// Sends out a data block (blk) by driving TX_(DVALID, DATA, LAST) lines
// of the TX streamer
/////////////////////////////////////////////////////////////////////////////
task automatic send_block(ref block_t blk);
int i = 0;
////$display("Sending block of %d words...", blk.words.data.size());
while(i < blk.words.size())
begin
if(tx_streamer_dreq) begin
// assert the TX_LAST line on the last word in the current block
tx_streamer_last <= (i == (blk.words.size() - 1)) ? 1 : 0;
tx_streamer_data <= blk.words[i];
//$display("Data to be sent is %d*****\n", tx_streamer_data);
tx_streamer_dvalid <= 1;
i++;
end else
tx_streamer_dvalid <= 0;
@(posedge clk);
end // while (i < blk.words.data.size())
tx_streamer_dvalid <= 0;
tx_streamer_last <= 0;
@(posedge clk);
endtask // send_block
///////////////////////////////////////////////////////////////////
task automatic send_frame(ref streamer_frame_t frm);
int i = 0;
while (i < frm.blocks.size()) begin
send_block(frm.blocks[i]);
i++;
end
endtask
endclass
\ No newline at end of file
testbench/wr_streamers/tx-streamer-tb/include/tb_wr_fabric_link_control.sv 0 → 100644
View file @ 98ffca2b
//-----------------------------------------------------------------------------
// Title : Definitions for WR streamers testbench
// Project : White Rabbit Cores
// URL : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
//-----------------------------------------------------------------------------
// File : wr-streamers-tb-class.sv
// Author(s) : Denia Bouhired <denia.bouhired@cern.ch>
// Company : CERN (BE-CO-HT)
// Created : 2017-04-28
//-----------------------------------------------------------------------------
// Description:
//
// SystemVerilog package with all definitions, interfaces, etc. necessary
// for the wr streamers testbench.
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2017 CERN
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.gnu.org/licenses/lgpl-2.1.html
//
//-----------------------------------------------------------------------------
//`include "../../../sim/if_wb_link.svh"
class CWRFABRIC_LINK_CTRL;
int data_width, addr_width;
IWishboneLink in;
IWishboneLink out;
//Class constructor
function new ();
// this.out() = this.in();
// this.in.g_data_width = data_width;
// this.in.g_addr_width = addr_width;
// this.out.g_data_width = data_width;
// this.out.g_addr_width = addr_width;
endfunction //new
//
function corrupt_data ();
in();
out();
endfunction
function drop_frames ();
in();
out();
endfunction //drop_frames
function break_link ();
in();
out();
endfunction //break_link
endclass;
// Transmitter class
// class CWRSTREAMERS_TX extends CWRSTREAMERS;
// function
// endclass;
// Receiver class
// class CWRSTREAMERS_RX extends CWRSTREAMERS;
// endclass;
testbench/wr_streamers/tx-streamer-tb/run.do
View file @ 98ffca2b
......@@ -5,7 +5,7 @@ set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do wave.do
run 500us
run 100us
wave zoomfull
radix -hex
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment