Commit 984a86f5 authored by Peter Jansweijer's avatar Peter Jansweijer

add dbg_o port

parent 18699344
Pipeline #358 failed with stages
in 2 minutes
......@@ -218,6 +218,9 @@ package wr_board_pkg is
pps_valid_o : out std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
link_ok_o : out std_logic);
end component xwrc_board_common;
......
......@@ -263,6 +263,9 @@ entity xwrc_board_common is
pps_valid_o : out std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
-- Link ok indication
link_ok_o : out std_logic
);
......@@ -483,6 +486,7 @@ begin -- architecture struct
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
rst_aux_n_o => aux_rst_n,
dbg_o => dbg_o,
aux_diag_i => aux_diag_in,
aux_diag_o => aux_diag_out,
link_ok_o => link_ok);
......
......@@ -149,6 +149,7 @@ package wr_spec7_pkg is
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
link_ok_o : out std_logic);
end component xwrc_board_spec7;
......
......@@ -255,6 +255,9 @@ entity xwrc_board_spec7 is
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
-- Link ok indication
link_ok_o : out std_logic
);
......@@ -756,6 +759,9 @@ begin -- architecture struct
btn2_i => btn2_i,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
dbg_o => dbg_o,
link_ok_o => link_ok_o);
cmp_wb_spec7_con : xwb_crossbar
......
......@@ -89,6 +89,8 @@ entity wr_pps_gen is
pps_valid_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic
......@@ -252,7 +254,6 @@ begin -- behavioral
ppsg_cntr_utclo <= std_logic_vector(cntr_utc(31 downto 0));
ppsg_cntr_utchi <= std_logic_vector(cntr_utc(39 downto 32));
-- loads adjustment values into internal regsiters
p_wishbone_loads : process(clk_sys_i, rst_n_i)
begin
......@@ -450,6 +451,31 @@ begin -- behavioral
end process;
dbg_o(0) <= ppsg_adj_utchi_wr;
dbg_o(1) <= ppsg_adj_utclo_wr;
dbg_o(2) <= ppsg_adj_nsec_wr;
dbg_o(3) <= ext_sync_p;
dbg_o(4) <= sync_in_progress;
dbg_o(5) <= ppsg_escr_sync_in;
dbg_o(6) <= ppsg_escr_sync_out;
dbg_o(7) <= adjust_in_progress_nsec;
dbg_o(8) <= adjust_in_progress_utc;
dbg_o(9) <= ns_overflow;
dbg_o(10) <= ns_overflow_adv;
dbg_o(11) <= ns_overflow_2nd;
dbg_o(12) <= pps_valid_int;
dbg_o(13) <= ppsg_cr_cnt_rst;
dbg_o(14) <= ppsg_cr_cnt_en;
dbg_o(15) <= ppsg_cr_cnt_set_p;
dbg_o(16) <= ppsg_escr_sec_set;
dbg_o(17) <= cntr_adjust_p;
dbg_o(18) <= pps_out_int;
dbg_o(19) <= ppsg_escr_pps_valid;
dbg_o(20) <= ppsg_escr_sync_load;
dbg_o(21) <= pps_in_refclk;
dbg_o(22) <= pps_in_i;
dbg_o(31 downto 23) <= (others => '0');
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
......
......@@ -75,6 +75,7 @@ entity xwr_pps_gen is
pps_led_o : out std_logic;
pps_valid_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
......@@ -114,6 +115,7 @@ architecture behavioral of xwr_pps_gen is
pps_out_o : out std_logic;
pps_led_o : out std_logic;
pps_valid_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic
......@@ -152,6 +154,7 @@ begin -- behavioral
pps_out_o => pps_out_o,
pps_led_o => pps_led_o,
pps_valid_o => pps_valid_o,
dbg_o => dbg_o,
tm_utc_o => tm_utc_o,
tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o
......
......@@ -306,7 +306,8 @@ entity wr_core is
rst_aux_n_o : out std_logic;
link_ok_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
-------------------------------------
-- DIAG to/from external modules
-------------------------------------
......@@ -641,6 +642,7 @@ begin
pps_out_o => pps_p_o,
pps_led_o => pps_led_o,
pps_valid_o => pps_valid,
dbg_o => dbg_o,
tm_utc_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
......
......@@ -89,6 +89,7 @@ package wrcore_pkg is
pps_out_o : out std_logic;
pps_led_o : out std_logic;
pps_valid_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic
......@@ -501,7 +502,9 @@ package wrcore_pkg is
rst_aux_n_o : out std_logic;
link_ok_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
);
......@@ -743,6 +746,8 @@ package wrcore_pkg is
pps_p_o : out std_logic;
pps_led_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
rst_aux_n_o : out std_logic;
link_ok_o : out std_logic;
......
......@@ -267,6 +267,8 @@ entity xwr_core is
pps_p_o : out std_logic;
pps_led_o : out std_logic;
dbg_o : out std_logic_vector(31 downto 0);
rst_aux_n_o : out std_logic;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
......@@ -449,6 +451,8 @@ begin
link_ok_o => link_ok_o,
dbg_o => dbg_o,
aux_diag_i => aux_diag_i,
aux_diag_o => aux_diag_o
);
......
......@@ -174,6 +174,8 @@ entity spec7_write_top is
-- B11 Single ended PPS_IN (Bank 13 AE23)
pps_i : in std_logic;
dbg_o : out std_logic_vector(22 downto 0);
-- blink 1-PPS.
led_pps_o : out std_logic;
......@@ -301,6 +303,7 @@ architecture top of spec7_write_top is
--PCIe
signal pci_clk : std_logic;
signal dbg : std_logic_vector(31 downto 0);
component pll_62m5_500m is
......@@ -488,8 +491,11 @@ AXI2WB : xwb_axi4lite_bridge
pps_p_o => wrc_pps_out,
pps_led_o => wrc_pps_led,
led_link_o => led_link_o,
dbg_o => dbg,
led_act_o => led_act_o);
dbg_o <= dbg(22 downto 0);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
......
......@@ -355,75 +355,144 @@ set_property IOSTANDARD LVCMOS25 [get_ports pps_i]
#set_property PACKAGE_PIN AC12 [get_ports fmc_la00_cc_p]
#set_property IOSTANDARD LVDS_25 [get_ports fmc_la00_cc_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la00_cc_p]
set_property PACKAGE_PIN AC12 [get_ports {dbg_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[0]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 3
#set_property PACKAGE_PIN AD11 [get_ports fmc_la00_cc_n]
#set_property IOSTANDARD LVDS_25 [get_ports fmc_la00_cc_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la00_cc_n]
set_property PACKAGE_PIN AD11 [get_ports {dbg_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[1]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 5
#set_property PACKAGE_PIN AB15 [get_ports fmc_la01_cc_p]
#set_property IOSTANDARD LVDS_25 [get_ports fmc_la01_cc_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la01_cc_p]
set_property PACKAGE_PIN AB15 [get_ports {dbg_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[2]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 7
#set_property PACKAGE_PIN AB14 [get_ports fmc_la01_cc_n]
#set_property IOSTANDARD LVDS_25 [get_ports fmc_la01_cc_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la01_cc_n]
set_property PACKAGE_PIN AB14 [get_ports {dbg_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[3]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 9
#set_property PACKAGE_PIN AE17 [get_ports fmc_la02_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la02_p]
set_property PACKAGE_PIN AE17 [get_ports {dbg_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[4]}]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 11
#set_property PACKAGE_PIN AF17 [get_ports fmc_la02_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la02_n]
set_property PACKAGE_PIN AF17 [get_ports {dbg_o[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[5]}]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 13
#set_property PACKAGE_PIN AA24 [get_ports fmc_la03_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la03_p]
set_property PACKAGE_PIN AA24 [get_ports {dbg_o[6]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[6]}]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 15
#set_property PACKAGE_PIN AB24 [get_ports fmc_la03_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la03_n]
set_property PACKAGE_PIN AB24 [get_ports {dbg_o[7]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[7]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 17
#set_property PACKAGE_PIN AE16 [get_ports fmc_la04_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la04_p]
set_property PACKAGE_PIN AE16 [get_ports {dbg_o[8]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[8]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 19
#set_property PACKAGE_PIN AE15 [get_ports fmc_la04_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la04_n]
set_property PACKAGE_PIN AE15 [get_ports {dbg_o[9]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[9]}]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 21
#set_property PACKAGE_PIN W20 [get_ports fmc_la05_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la05_p]
set_property PACKAGE_PIN W20 [get_ports {dbg_o[10]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[10]}]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 23
#set_property PACKAGE_PIN Y20 [get_ports fmc_la05_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la05_n]
set_property PACKAGE_PIN Y20 [get_ports {dbg_o[11]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[11]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 25
#set_property PACKAGE_PIN W18 [get_ports fmc_la06_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la06_p]
set_property PACKAGE_PIN W18 [get_ports {dbg_o[12]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[12]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 27
#set_property PACKAGE_PIN W19 [get_ports fmc_la06_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la06_n]
set_property PACKAGE_PIN W19 [get_ports {dbg_o[13]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[13]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 29
#set_property PACKAGE_PIN AB17 [get_ports fmc_la07_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la07_p]
set_property PACKAGE_PIN AB17 [get_ports {dbg_o[14]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[14]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 31
#set_property PACKAGE_PIN AB16 [get_ports fmc_la07_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la07_n]
set_property PACKAGE_PIN AB16 [get_ports {dbg_o[15]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[15]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 33
#set_property PACKAGE_PIN Y17 [get_ports fmc_la08_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la08_p]
set_property PACKAGE_PIN Y17 [get_ports {dbg_o[16]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[16]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 35
#set_property PACKAGE_PIN AA17 [get_ports fmc_la08_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la08_n]
set_property PACKAGE_PIN AA17 [get_ports {dbg_o[17]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[17]}]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
#set_property PACKAGE_PIN AA19 [get_ports fmc_la09_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la09_p]
set_property PACKAGE_PIN AA19 [get_ports {dbg_o[18]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[18]}]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
#set_property PACKAGE_PIN AB19 [get_ports fmc_la09_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la09_n]
set_property PACKAGE_PIN AB19 [get_ports {dbg_o[19]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[19]}]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 2
#set_property PACKAGE_PIN Y18 [get_ports fmc_la10_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la10_p]
set_property PACKAGE_PIN Y18 [get_ports {dbg_o[20]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[20]}]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 4
#set_property PACKAGE_PIN AA18 [get_ports fmc_la10_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la10_n]
set_property PACKAGE_PIN AA18 [get_ports {dbg_o[21]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[21]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 6
#set_property PACKAGE_PIN AF15 [get_ports fmc_la11_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la11_p]
set_property PACKAGE_PIN AF15 [get_ports {dbg_o[22]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dbg_o[22]}]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 8
#set_property PACKAGE_PIN AF14 [get_ports fmc_la11_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la11_n]
......
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