sim: updated register layouts

modified: endpoint_regs.v modified: minic_regs.vh

sim: updated register layouts
modified: endpoint_regs.v modified: minic_regs.vh
9828ec32 · Tomasz Wlostowski · 594f497e · 9828ec32 · 9828ec32 · 9828ec32
Commit 9828ec32 authored Jan 17, 2012 by Tomasz Wlostowski
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endpoint_regs.v sim/endpoint_regs.v +10 -0

minic_regs.vh sim/minic_regs.vh +5 -0

pps_gen_regs.v sim/pps_gen_regs.v +24 -0

softpll_regs.v sim/softpll_regs.v +41 -0

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--- a/sim/endpoint_regs.v
+++ b/sim/endpoint_regs.v
@@ -97,5 +97,15 @@
 `define EP_DSR_LSTATUS 32'h00000001
 `define EP_DSR_LACT_OFFSET 1
 `define EP_DSR_LACT 32'h00000002
+`define ADDR_EP_DMCR                   8'h3c
+`define EP_DMCR_EN_OFFSET 0
+`define EP_DMCR_EN 32'h00000001
+`define EP_DMCR_N_AVG_OFFSET 16
+`define EP_DMCR_N_AVG 32'h0fff0000
+`define ADDR_EP_DMSR                   8'h40
+`define EP_DMSR_PS_VAL_OFFSET 0
+`define EP_DMSR_PS_VAL 32'h00ffffff
+`define EP_DMSR_PS_RDY_OFFSET 24
+`define EP_DMSR_PS_RDY 32'h01000000
 `define BASE_EP_RMON_RAM               8'h80
 `define SIZE_EP_RMON_RAM               32'h20
--- a/sim/minic_regs.vh
+++ b/sim/minic_regs.vh
@@ -31,6 +31,11 @@
 `define MINIC_DBGR_IRQ_CNT 32'h00ffffff
 `define MINIC_DBGR_WB_IRQ_VAL_OFFSET 24
 `define MINIC_DBGR_WB_IRQ_VAL 32'h01000000
+`define ADDR_MINIC_MPROT               6'h1c
+`define MINIC_MPROT_LO_OFFSET 0
+`define MINIC_MPROT_LO 32'h0000ffff
+`define MINIC_MPROT_HI_OFFSET 16
+`define MINIC_MPROT_HI 32'hffff0000
 `define ADDR_MINIC_EIC_IDR             6'h20
 `define MINIC_EIC_IDR_TX_OFFSET 0
 `define MINIC_EIC_IDR_TX 32'h00000001

--- a/sim/pps_gen_regs.v
+++ b/sim/pps_gen_regs.v
+`define ADDR_PPSG_CR                   5'h0
+`define PPSG_CR_CNT_RST_OFFSET 0
+`define PPSG_CR_CNT_RST 32'h00000001
+`define PPSG_CR_CNT_EN_OFFSET 1
+`define PPSG_CR_CNT_EN 32'h00000002
+`define PPSG_CR_CNT_ADJ_OFFSET 2
+`define PPSG_CR_CNT_ADJ 32'h00000004
+`define PPSG_CR_CNT_SET_OFFSET 3
+`define PPSG_CR_CNT_SET 32'h00000008
+`define PPSG_CR_PWIDTH_OFFSET 4
+`define PPSG_CR_PWIDTH 32'hfffffff0
+`define ADDR_PPSG_CNTR_NSEC            5'h4
+`define ADDR_PPSG_CNTR_UTCLO           5'h8
+`define ADDR_PPSG_CNTR_UTCHI           5'hc
+`define ADDR_PPSG_ADJ_NSEC             5'h10
+`define ADDR_PPSG_ADJ_UTCLO            5'h14
+`define ADDR_PPSG_ADJ_UTCHI            5'h18
+`define ADDR_PPSG_ESCR                 5'h1c
+`define PPSG_ESCR_SYNC_OFFSET 0
+`define PPSG_ESCR_SYNC 32'h00000001
+`define PPSG_ESCR_PPS_VALID_OFFSET 1
+`define PPSG_ESCR_PPS_VALID 32'h00000002
+`define PPSG_ESCR_TM_VALID_OFFSET 2
+`define PPSG_ESCR_TM_VALID 32'h00000004
--- a/sim/softpll_regs.v
+++ b/sim/softpll_regs.v
+`define ADDR_SPLL_CSR                  6'h0
+`define SPLL_CSR_N_REF_OFFSET 0
+`define SPLL_CSR_N_REF 32'h0000003f
+`define SPLL_CSR_N_OUT_OFFSET 8
+`define SPLL_CSR_N_OUT 32'h00000700
+`define ADDR_SPLL_OCCR                 6'h4
+`define SPLL_OCCR_OUT_EN_OFFSET 0
+`define SPLL_OCCR_OUT_EN 32'h000000ff
+`define SPLL_OCCR_AUX_LOCK_OFFSET 8
+`define SPLL_OCCR_AUX_LOCK 32'h0000ff00
+`define ADDR_SPLL_RCER                 6'h8
+`define ADDR_SPLL_PER_HPLL             6'hc
+`define ADDR_SPLL_DAC_HPLL             6'h10
+`define ADDR_SPLL_DAC_MAIN             6'h14
+`define SPLL_DAC_MAIN_VALUE_OFFSET 0
+`define SPLL_DAC_MAIN_VALUE 32'h0000ffff
+`define SPLL_DAC_MAIN_DAC_SEL_OFFSET 16
+`define SPLL_DAC_MAIN_DAC_SEL 32'h000f0000
+`define ADDR_SPLL_DEGLITCH_THR         6'h18
+`define ADDR_SPLL_EIC_IDR              6'h20
+`define SPLL_EIC_IDR_TAG_OFFSET 0
+`define SPLL_EIC_IDR_TAG 32'h00000001
+`define ADDR_SPLL_EIC_IER              6'h24
+`define SPLL_EIC_IER_TAG_OFFSET 0
+`define SPLL_EIC_IER_TAG 32'h00000001
+`define ADDR_SPLL_EIC_IMR              6'h28
+`define SPLL_EIC_IMR_TAG_OFFSET 0
+`define SPLL_EIC_IMR_TAG 32'h00000001
+`define ADDR_SPLL_EIC_ISR              6'h2c
+`define SPLL_EIC_ISR_TAG_OFFSET 0
+`define SPLL_EIC_ISR_TAG 32'h00000001
+`define ADDR_SPLL_TRR_R0               6'h30
+`define SPLL_TRR_R0_VALUE_OFFSET 0
+`define SPLL_TRR_R0_VALUE 32'h00ffffff
+`define SPLL_TRR_R0_CHAN_ID_OFFSET 24
+`define SPLL_TRR_R0_CHAN_ID 32'h7f000000
+`define SPLL_TRR_R0_DISC_OFFSET 31
+`define SPLL_TRR_R0_DISC 32'h80000000
+`define ADDR_SPLL_TRR_CSR              6'h34
+`define SPLL_TRR_CSR_EMPTY_OFFSET 17
+`define SPLL_TRR_CSR_EMPTY 32'h00020000