use optimized DPRAM for faster initialization during WRPC synthesis

912b3cad · Grzegorz Daniluk · 28fd3d67 · 0973db51 · 912b3cad · 28fd3d67
Commit 912b3cad authored Feb 14, 2017 by Grzegorz Daniluk
4 changed files
--- a/general-cores @ 0973db51
+++ b/general-cores @ 0973db51
-Subproject commit 0d75c0fdc0059b9ce3a8adb76a4ff14b5b795d6c
+Subproject commit 0973db51ec0e21f2ef961c1b6843c6672eee7f23
--- a/syn/spec_1_1/wr_core_demo/wrc.bram
+++ b/syn/spec_1_1/wr_core_demo/wrc.bram
--- a/syn/spec_1_1/wr_core_demo/wrc.ram
+++ b/syn/spec_1_1/wr_core_demo/wrc.ram
--- a/top/spec_1_1/wr_core_demo/spec_top.vhd
+++ b/top/spec_1_1/wr_core_demo/spec_top.vhd
@@ -468,7 +468,7 @@ begin
      g_tx_runt_padding           => true,
      g_pcs_16bit                 => false,
      g_records_for_phy           => true,
-      g_dpram_initf               => "wrc.ram",
+      g_dpram_initf               => "wrc.bram",
      g_aux_sdb                   => c_etherbone_sdb,
      g_dpram_size                => 131072/4,
      g_interface_mode            => PIPELINED,