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White Rabbit core collection
Commit 8fb70ab3 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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TRU: adding features and I/F necessary for TRU unit. I/F for packet filter, flow… 

TRU: adding features and I/F necessary for TRU unit. I/F for packet filter, flow ctr and adding functionality for killing link
parent 681dfd62
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Showing with 137 additions and 14 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 8fb70ab3
......@@ -120,6 +120,12 @@ package endpoint_pkg is
rtu_rq_has_prio_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
pfilter_pclass_o : out std_logic_vector(7 downto 0);
pfilter_drop_o : out std_logic;
pfilter_done_o : out std_logic;
fc_pause_req_i : in std_logic := '0';
fc_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_pause_ready_o : out std_logic;
inject_req_i : in std_logic := '0';
inject_ready_o : out std_logic;
inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
......@@ -219,6 +225,12 @@ package endpoint_pkg is
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
pfilter_pclass_o : out std_logic_vector(7 downto 0);
pfilter_drop_o : out std_logic;
pfilter_done_o : out std_logic;
fc_pause_req_i : in std_logic := '0';
fc_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_pause_ready_o : out std_logic;
inject_req_i : in std_logic := '0';
inject_ready_o : out std_logic;
inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 8fb70ab3
......@@ -203,6 +203,7 @@ package endpoint_private_pkg is
txtsu_ack_i : in std_logic;
txts_timestamp_i : in std_logic_vector(31 downto 0);
txts_timestamp_valid_i : in std_logic;
ep_ctrl_i : in std_logic;
regs_i : in t_ep_out_registers);
end component;
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ 8fb70ab3
......@@ -112,7 +112,7 @@ entity ep_1000basex_pcs is
txpcs_timestamp_trigger_p_a_o : out std_logic;
link_ok_o : out std_logic;
link_ctr_i : in std_logic;
-----------------------------------------------------------------------------
-- GTP/GTX/TBI Serdes interface
---------------------------------------------------------------------------
......@@ -354,6 +354,7 @@ architecture rtl of ep_1000basex_pcs is
signal mdio_mcr_uni_en : std_logic;
signal mdio_mcr_anrestart : std_logic;
signal mdio_mcr_pdown : std_logic;
signal mdio_mcr_pdown_cpu : std_logic;
signal mdio_mcr_anenable : std_logic;
signal mdio_mcr_loopback : std_logic;
signal mdio_mcr_reset : std_logic;
......@@ -537,6 +538,9 @@ begin -- rtl
txpcs_busy_o <= txpcs_busy_int;
-- to enable killing of link (by ML)
mdio_mcr_pdown <= mdio_mcr_pdown_cpu or (not link_ctr_i);
serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown;
mdio_wr_spec_bslide <= serdes_rx_bitslide_i(4 downto 0);
......@@ -561,7 +565,7 @@ begin -- rtl
mdio_mcr_uni_en_o => mdio_mcr_uni_en,
mdio_mcr_anrestart_o => mdio_mcr_anrestart,
mdio_mcr_pdown_o => mdio_mcr_pdown,
mdio_mcr_pdown_o => mdio_mcr_pdown_cpu,
mdio_mcr_anenable_o => mdio_mcr_anenable,
mdio_mcr_loopback_o => mdio_mcr_loopback,
mdio_mcr_reset_o => mdio_mcr_reset,
......
modules/wr_endpoint/ep_rx_path.vhd
View file @ 8fb70ab3
......@@ -89,6 +89,11 @@ entity ep_rx_path is
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers;
-- info for TRU module
pfilter_pclass_o : out std_logic_vector(7 downto 0);
pfilter_drop_o : out std_logic;
pfilter_done_o : out std_logic;
-------------------------------------------------------------------------------
-- RTU interface
-------------------------------------------------------------------------------
......@@ -491,5 +496,10 @@ begin -- behavioral
src_wb_o => src_wb_o
);
-- direct output of packet filter data (for TRU)
pfilter_pclass_o <= pfilter_pclass;
pfilter_drop_o <= pfilter_drop;
pfilter_done_o <= pfilter_done;
end behavioral;
modules/wr_endpoint/ep_tx_framer.vhd
View file @ 8fb70ab3
......@@ -113,6 +113,7 @@ entity ep_tx_framer is
-- Control registers
-------------------------------------------------------------------------------
ep_ctrl_i : in std_logic;
regs_i : in t_ep_out_registers
);
......@@ -171,8 +172,8 @@ architecture behavioral of ep_tx_framer is
signal stall_int : std_logic;
signal stall_int_d0 : std_logic;
signal untagging : std_logic;
signal got_error : std_logic;
signal got_error : std_logic;
signal tx_en : std_logic;
function b2s (x : boolean)
return std_logic is
......@@ -282,8 +283,7 @@ begin -- behavioral
error_p1 <= snk_valid and b2s(snk_i.adr = c_WRF_STATUS) and decoded_status.error;
abort_now <= '1' when (state /= TXF_IDLE and state /= TXF_GAP) and (regs_i.ecr_tx_en_o = '0' or error_p1 = '1') else '0';
abort_now <= '1' when (state /= TXF_IDLE and state /= TXF_GAP) and (tx_en = '0' or error_p1 = '1') else '0';
p_store_status : process(clk_sys_i)
begin
......@@ -402,7 +402,7 @@ begin -- behavioral
-- Check start-of-frame and send-pause signals and eventually
-- commence frame transmission
if(pcs_dreq_i = '1' and (sof_p1 = '1' or fc_pause_p_i = '1') and regs_i.ecr_tx_en_o = '1') then
if(pcs_dreq_i = '1' and (sof_p1 = '1' or fc_pause_p_i = '1') and tx_en = '1') then
-- enable writing to PCS FIFO
q_sof <= '1';
write_mask <= '1';
......@@ -724,8 +724,9 @@ begin -- behavioral
end if;
end process;
stall_int <= (not (pcs_dreq_i and tx_ready) and regs_i.ecr_tx_en_o) or (snk_i.cyc xor snk_cyc_d0); -- /dev/null if disabled
tx_en <= regs_i.ecr_tx_en_o and ep_ctrl_i;
stall_int <= (not (pcs_dreq_i and tx_ready) and tx_en) or (snk_i.cyc xor snk_cyc_d0); -- /dev/null if disabled
snk_out.stall <= stall_int;
......
modules/wr_endpoint/ep_tx_header_processor.vhd
View file @ 8fb70ab3
......@@ -123,7 +123,7 @@ entity ep_tx_header_processor is
-------------------------------------------------------------------------------
-- Control registers
-------------------------------------------------------------------------------
ep_ctrl_i : in std_logic;
regs_i : in t_ep_out_registers
);
......@@ -162,7 +162,7 @@ architecture behavioral of ep_tx_header_processor is
signal abort_now : std_logic;
signal stall_int : std_logic;
signal tx_en : std_logic;
function b2s (x : boolean)
return std_logic is
......@@ -236,6 +236,7 @@ begin -- behavioral
error_p1 <= snk_valid and b2s(wb_snk_i.adr = c_WRF_STATUS) and decoded_status.error;
abort_now <= '1' when (state /= TXF_IDLE and state /= TXF_GAP) and (regs_i.ecr_tx_en_o = '0' or error_p1 = '1') else '0';
-- abort_now <= '1' when (state /= TXF_IDLE and state /= TXF_GAP) and (tx_en = '0' or error_p1 = '1') else '0'; -- ML
p_store_status : process(clk_sys_i)
begin
......@@ -351,6 +352,7 @@ begin -- behavioral
-- commence frame transmission
if(src_dreq_i = '1' and (sof_p1 = '1' or fc_pause_req_i = '1') and regs_i.ecr_tx_en_o = '1') then
-- if(src_dreq_i = '1' and (sof_p1 = '1' or fc_pause_p_i = '1') and tx_en = '1') then --ML
fc_pause_ready_o <= '0';
tx_pause_mode <= fc_pause_req_i;
......@@ -505,6 +507,7 @@ begin -- behavioral
end if;
end process;
tx_en <= regs_i.ecr_tx_en_o and ep_ctrl_i;
p_gen_stall : process(src_dreq_i, state, regs_i, wb_snk_i, snk_cyc_d0)
begin
......
modules/wr_endpoint/ep_tx_path.vhd
View file @ 8fb70ab3
......@@ -130,7 +130,7 @@ entity ep_tx_path is
-------------------------------------------------------------------------------
-- Control registers
-------------------------------------------------------------------------------
ep_ctrl_i : in std_logic :='1';
regs_i : in t_ep_out_registers
);
......@@ -175,6 +175,7 @@ begin -- rtl
txtsu_ack_i => txtsu_ack_i,
txts_timestamp_i => txts_timestamp_i,
txts_timestamp_valid_i => txts_timestamp_valid_i,
ep_ctrl_i => ep_ctrl_i,
regs_i => regs_i);
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 8fb70ab3
......@@ -223,6 +223,22 @@ entity wr_endpoint is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-------------------------------------------------------------------------------
-- direct output of packet filter (for TRU/HW-RSTP)
-------------------------------------------------------------------------------
pfilter_pclass_o : out std_logic_vector(7 downto 0);
pfilter_drop_o : out std_logic;
pfilter_done_o : out std_logic;
-------------------------------------------------------------------------------
-- control of PAUSE sending (for TRU/HW-RSTP)
-------------------------------------------------------------------------------
fc_pause_req_i : in std_logic := '0';
fc_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_pause_ready_o : out std_logic;
-------------------------------------------------------------------------------
-- Packet Injection Interface (for TRU/HW-RSTP)
-------------------------------------------------------------------------------
......@@ -249,7 +265,11 @@ entity wr_endpoint is
led_link_o : out std_logic;
led_act_o : out std_logic;
-- HI physically kills the link (turn of laser)
link_kill_i : in std_logic := '0';
-- HI indicates that link is up (so cable connected), LOW indicates that link is faulty
-- (e.g.: cable disconnected)
link_up_o : out std_logic
);
......@@ -321,6 +341,7 @@ architecture syn of wr_endpoint is
inject_ready_o : out std_logic;
inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
ep_ctrl_i : in std_logic :='1';
regs_i : in t_ep_out_registers);
end component;
......@@ -347,6 +368,9 @@ architecture syn of wr_endpoint is
rmon_o : inout t_rmon_triggers;
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers;
pfilter_pclass_o : out std_logic_vector(7 downto 0);
pfilter_drop_o : out std_logic;
pfilter_done_o : out std_logic;
rtu_rq_o : out t_ep_internal_rtu_request;
rtu_full_i : in std_logic;
rtu_rq_valid_o : out std_logic);
......@@ -372,6 +396,7 @@ architecture syn of wr_endpoint is
txpcs_dreq_o : out std_logic;
txpcs_timestamp_trigger_p_a_o : out std_logic;
link_ok_o : out std_logic;
link_ctr_i : in std_logic := '1';
serdes_rst_o : out std_logic;
serdes_syncen_o : out std_logic;
serdes_loopen_o : out std_logic;
......@@ -546,6 +571,17 @@ architecture syn of wr_endpoint is
signal rtu_rq : t_ep_internal_rtu_request;
signal dvalid_tx, dvalid_rx : std_logic;
-------------------------------------------------------------------------------
-- TRU stuff
-------------------------------------------------------------------------------
signal ep_ctrl : std_logic;
signal pfilter_pclass : std_logic_vector(7 downto 0);
signal pfilter_drop : std_logic;
signal pfilter_done : std_logic;
signal tx_pclass : std_logic_vector(7 downto 0);
begin
-----------------------------------------------------------------------------
......@@ -599,7 +635,8 @@ begin
txpcs_timestamp_trigger_p_a_o => txpcs_timestamp_trigger_p_a,
link_ok_o => link_ok,
link_ok_o => link_ok,
link_ctr_i => ep_ctrl,
serdes_rst_o => phy_rst_o,
serdes_loopen_o => phy_loopen_o,
......@@ -633,7 +670,7 @@ begin
-- txfra_enable <= link_ok and regs_fromwb.ecr_tx_en_o;
txfra_pause_req <= '0';
-- txfra_pause_req <= '0';
U_Tx_Path : ep_tx_path
generic map (
......@@ -654,6 +691,7 @@ begin
fc_pause_ready_o => txfra_pause_ready,
fc_pause_delay_i => txfra_pause_delay,
fc_flow_enable_i => txfra_flow_enable,
ep_ctrl_i => ep_ctrl,
regs_i => regs_fromwb,
txts_timestamp_i => txts_timestamp_value,
......@@ -717,6 +755,10 @@ begin
regs_i => regs_fromwb,
regs_o => regs_towb_rpath,
pfilter_pclass_o => pfilter_pclass,
pfilter_drop_o => pfilter_drop,
pfilter_done_o => pfilter_done,
rtu_full_i => rtu_full_i,
rtu_rq_o => rtu_rq,
rtu_rq_valid_o => rtu_rq_strobe_p1_o,
......@@ -988,6 +1030,29 @@ begin
led_act_o => led_act_o);
end generate gen_leds;
-------------------------- TRU stuff -----------------------------------
link_up_o <= link_ok; -- indicates that link is IP
pfilter_pclass_o <= pfilter_pclass;
pfilter_done_o <= pfilter_done;
pfilter_drop_o <= pfilter_drop;
txfra_pause_req <= fc_pause_req_i;
fc_pause_ready_o <= txfra_pause_ready;
txfra_pause_delay <= fc_pause_delay_i;
-- TRU needs to be able to share the control of ouput path, i.e. turn off the laser
p_ep_ctrl: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
ep_ctrl <= '1';
else
ep_ctrl <= not link_kill_i ;
end if;
end if;
end process;
end syn;
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 8fb70ab3
......@@ -191,6 +191,26 @@ entity xwr_endpoint is
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-------------------------------------------------------------------------------
-- direct output of packet filter (for TRU/HW-RSTP)
-------------------------------------------------------------------------------
pfilter_pclass_o : out std_logic_vector(7 downto 0);
pfilter_drop_o : out std_logic;
pfilter_done_o : out std_logic;
-------------------------------------------------------------------------------
-- control of PAUSE sending (for TRU/HW-RSTP)
-------------------------------------------------------------------------------
fc_pause_req_i : in std_logic := '0';
fc_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_pause_ready_o : out std_logic;
-------------------------------------------------------------------------------
-- Packet Injection Interface (for TRU/HW-RSTP)
-------------------------------------------------------------------------------
-- injection request: triggers transmission of the packet to be injected,
-- allowed when inject_ready = 1
inject_req_i : in std_logic := '0';
......@@ -317,6 +337,12 @@ begin
led_act_o => led_act_o,
link_up_o => link_up_o,
link_kill_i => link_kill_i,
pfilter_pclass_o => pfilter_pclass_o,
pfilter_drop_o => pfilter_drop_o,
pfilter_done_o => pfilter_done_o,
fc_pause_req_i => fc_pause_req_i,
fc_pause_delay_i => fc_pause_delay_i,
fc_pause_ready_o => fc_pause_ready_o,
inject_req_i => inject_req_i,
inject_user_value_i => inject_user_value_i,
inject_packet_sel_i => inject_packet_sel_i,
......
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