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White Rabbit core collection
Commit 8fa73b6e authored by Maciej Lipinski's avatar Maciej Lipinski
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[PHY/Virtex5] synchronize resets with rx_clk

parent be42d527
Pipeline #690 failed with stages
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      platform/xilinx/wr_gtp_phy/virtex5/wr_gtp_phy_virtex5.vhd
      View file @ 8fa73b6e
      ......@@ -372,6 +372,9 @@ architecture rtl of wr_gtp_phy_virtex5 is
      signal ch0_rdy, ch1_rdy : std_logic;
      signal ch0_rx_clk_rst: std_logic;
      signal ch1_rx_clk_rst: std_logic;
      begin -- rtl
      -------------------------------------------------------------------------------
      -- Channel 0 logic
      ......@@ -407,7 +410,7 @@ begin -- rtl
      begin
      if rising_edge(ch01_ref_clk_i) then
      ch0_rst_d0 <= ch0_rst_i;
      ch0_rst_d0 <= ch0_rst_i; -- pass from sys_clk to ref_clk
      ch0_rst_synced <= ch0_rst_d0;
      if(ch0_rst_synced = '1') then
      ......@@ -431,7 +434,7 @@ begin -- rtl
      U_Align_Detect_CH0: v5_gtp_align_detect
      port map (
      clk_rx_i => ch0_rx_rec_clk,
      rst_i => ch01_gtp_reset,
      rst_i => ch0_rx_clk_rst,
      data_i => ch0_rx_data_int,
      k_i => ch0_rx_k_int,
      aligned_o => ch0_rx_byte_is_aligned);
      ......@@ -441,7 +444,7 @@ begin -- rtl
      generic map (
      g_simulation => g_simulation)
      port map (
      gtp_rst_i => ch01_gtp_reset,
      gtp_rst_i => ch0_rx_clk_rst,
      gtp_rx_clk_i => ch0_rx_rec_clk,
      gtp_rx_comma_det_i => ch0_rx_comma_det,
      gtp_rx_byte_is_aligned_i => ch0_rx_byte_is_aligned,
      ......@@ -487,9 +490,9 @@ begin -- rtl
      end if;
      end process;
      p_gen_output_ch0 : process(ch0_rx_rec_clk, ch01_gtp_reset)
      p_gen_output_ch0 : process(ch0_rx_rec_clk, ch0_rx_clk_rst)
      begin
      if(ch01_gtp_reset = '1') then
      if(ch0_rx_clk_rst = '1') then
      ch0_rx_data_o <= (others => '0');
      ch0_rx_k_o <= '0';
      ch0_rx_enc_err_o <= '0';
      ......@@ -513,6 +516,15 @@ begin -- rtl
      -- drive the recovered clock output
      ch0_rx_rbclk_o <= ch0_rx_rec_clk;
      U_sync_rx_clk_rst_ch0 : gc_sync_ffs
      generic map (
      g_sync_edge => "positive")
      port map (
      clk_i => ch0_rx_rec_clk,
      rst_n_i => '1',
      data_i => ch0_gtp_reset,
      synced_o => ch0_rx_clk_rst);
      end generate gen_with_channel0;
      ch0_gtp_loopback <= "000";
      ......@@ -572,7 +584,7 @@ begin -- rtl
      U_Align_Detect_CH1: v5_gtp_align_detect
      port map (
      clk_rx_i => ch1_rx_rec_clk,
      rst_i => ch01_gtp_reset,
      rst_i => ch1_rx_clk_rst,
      data_i => ch1_rx_data_int,
      k_i => ch1_rx_k_int,
      aligned_o => ch1_rx_byte_is_aligned);
      ......@@ -584,7 +596,7 @@ begin -- rtl
      generic map (
      g_simulation => g_simulation)
      port map (
      gtp_rst_i => ch01_gtp_reset,
      gtp_rst_i => ch1_rx_clk_rst,
      gtp_rx_clk_i => ch1_rx_rec_clk,
      gtp_rx_comma_det_i => ch1_rx_comma_det,
      gtp_rx_byte_is_aligned_i => ch1_rx_byte_is_aligned,
      ......@@ -631,9 +643,9 @@ begin -- rtl
      end if;
      end process;
      p_gen_output_ch1 : process(ch1_rx_rec_clk, ch1_rst_i)
      p_gen_output_ch1 : process(ch1_rx_rec_clk, ch1_rx_clk_rst)
      begin
      if(ch1_rst_i = '1') then
      if(ch1_rx_clk_rst = '1') then
      ch1_rx_data_o <= (others => '0');
      ch1_rx_k_o <= '0';
      ch1_rx_enc_err_o <= '0';
      ......@@ -654,6 +666,16 @@ begin -- rtl
      end process;
      ch1_rx_rbclk_o <= ch1_rx_rec_clk;
      U_sync_rx_clk_rst_ch1 : gc_sync_ffs
      generic map (
      g_sync_edge => "positive")
      port map (
      clk_i => ch1_rx_rec_clk,
      rst_n_i => '1',
      data_i => ch1_gtp_reset,
      synced_o => ch1_rx_clk_rst);
      end generate gen_with_channel1;
      ch1_gtp_loopback <= "000";
      ......@@ -664,7 +686,7 @@ begin -- rtl
      gen_with_common : if(g_enable_ch0 /= 0) or (g_enable_ch1 /= 0) generate
      ch01_gtp_reset <= ch0_gtp_reset; -- or ch1_gtp_reset;
      ch01_gtp_reset <= ch0_gtp_reset or ch1_gtp_reset;
      ch01_ref_clk_in <= gtp_clk_i;
      ......@@ -767,6 +789,9 @@ begin -- rtl
      -- ML:
      ch0_rdy_o <= '1'; -- todo
      ch1_rdy_o <= '1'; -- todo
      -- ch0_rdy <= ch0_rx_enable_output_synced when (g_enable_ch0 = 1) else '0';
      -- ch1_rdy <= ch1_rx_enable_output_synced when (g_enable_ch1 = 1) else '0';
      -- ch0_rdy <= ch01_gtp_locked and ch01_align_done when (g_enable_ch0 = 1) else '0';
      -- ch1_rdy <= ch01_gtp_locked and ch01_align_done when (g_enable_ch1 = 1) else '0';
      --
      ......
      platform/xilinx/xwrc_platform_xilinx.vhd
      View file @ 8fa73b6e
      ......@@ -876,7 +876,7 @@ begin -- architecture rtl
      ch0_rx_k_o => ch0_phy8_out.rx_k(0),
      ch0_rx_enc_err_o => ch0_phy8_out.rx_enc_err,
      ch0_rx_bitslide_o => ch0_phy8_out.rx_bitslide,
      ch0_rst_i => phy8_i.rst,
      ch0_rst_i => phy8_i.rst, -- sys_clk domain
      ch0_loopen_i => phy8_i.loopen,
      ch0_loopen_vec_i => phy8_i.loopen_vec,
      ch0_tx_prbs_sel_i => phy8_i.tx_prbs_sel,
      ......@@ -893,7 +893,7 @@ begin -- architecture rtl
      ch1_rx_k_o => ch1_phy8_out.rx_k(0),
      ch1_rx_enc_err_o => ch1_phy8_out.rx_enc_err,
      ch1_rx_bitslide_o => ch1_phy8_out.rx_bitslide,
      ch1_rst_i => phy8_i.rst,
      ch1_rst_i => phy8_i.rst,-- sys_clk domain
      ch1_loopen_i => phy8_i.loopen,
      ch1_loopen_vec_i => phy8_i.loopen_vec,
      ch1_tx_prbs_sel_i => phy8_i.tx_prbs_sel,
      ......@@ -994,7 +994,7 @@ begin -- architecture rtl
      ch0_rx_k_o => ch0_phy8_out.rx_k(0),
      ch0_rx_enc_err_o => ch0_phy8_out.rx_enc_err,
      ch0_rx_bitslide_o => ch0_phy8_out.rx_bitslide,
      ch0_rst_i => phy8_i.rst,
      ch0_rst_i => phy8_i.rst, -- sys_clk domain
      ch0_loopen_i => phy8_i.loopen,
      ch0_rdy_o => ch0_phy8_out.rdy,
      ch1_tx_data_i => phy8_i.tx_data,
      ......@@ -1006,7 +1006,7 @@ begin -- architecture rtl
      ch1_rx_k_o => ch1_phy8_out.rx_k(0),
      ch1_rx_enc_err_o => ch1_phy8_out.rx_enc_err,
      ch1_rx_bitslide_o => ch1_phy8_out.rx_bitslide,
      ch1_rst_i => phy8_i.rst,
      ch1_rst_i => phy8_i.rst, -- sys_clk domain
      ch1_loopen_i => phy8_i.loopen,
      ch1_rdy_o => ch1_phy8_out.rdy,
      pad_txn0_o => ch0_sfp_txn,
      ......@@ -1146,7 +1146,7 @@ begin -- architecture rtl
      rx_k_o => phy16_o.rx_k,
      rx_enc_err_o => phy16_o.rx_enc_err,
      rx_bitslide_o => phy16_o.rx_bitslide,
      rst_i => phy16_i.rst,
      rst_i => phy16_i.rst, -- sys_clk domain
      loopen_i => phy16_i.loopen_vec,
      tx_prbs_sel_i => phy16_i.tx_prbs_sel,
      rdy_o => phy16_o.rdy,
      ......@@ -1222,7 +1222,7 @@ begin -- architecture rtl
      rx_k_o => phy16_o.rx_k,
      rx_enc_err_o => phy16_o.rx_enc_err,
      rx_bitslide_o => phy16_o.rx_bitslide,
      rst_i => phy16_i.rst,
      rst_i => phy16_i.rst, -- sys_clk domain
      loopen_i => phy16_i.loopen_vec,
      tx_prbs_sel_i => phy16_i.tx_prbs_sel,
      rdy_o => phy16_o.rdy,
      ......
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