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White Rabbit core collection
Commit 8e07dc58 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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board: rename clk_ext_i port so that it is consistent across all boards

parent 9b8256e1
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Showing with 37 additions and 37 deletions
board/common/wr_board_pkg.vhd
View file @ 8e07dc58
......@@ -87,7 +87,7 @@ package wr_board_pkg is
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
......
board/common/xwrc_board_common.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-22
-- Last update: 2017-03-08
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Wrapper for WR PTP core with common features shared between
......@@ -90,7 +90,7 @@ entity xwrc_board_common is
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
......@@ -332,7 +332,7 @@ begin -- architecture struct
clk_dmtd_i => clk_dmtd_i,
clk_ref_i => clk_ref_i,
clk_aux_i => clk_aux_i,
clk_ext_i => clk_ext_i,
clk_ext_i => clk_10m_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_stopped_i => clk_ext_stopped_i,
......
board/spec/wr_spec_pkg.vhd
View file @ 8e07dc58
......@@ -31,7 +31,7 @@ package wr_spec_pkg is
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
......@@ -129,7 +129,7 @@ package wr_spec_pkg is
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
......
board/spec/wrc_board_spec.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-03-08
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -90,7 +90,7 @@ entity wrc_board_spec is
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
......@@ -393,7 +393,7 @@ begin -- architecture struct
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_ref_i => clk_10m_ext_ref_i,
clk_10m_ext_i => clk_10m_ext_i,
pps_ext_i => pps_ext_i,
clk_sys_62m5_o => clk_sys_62m5_o,
clk_ref_125m_o => clk_ref_125m_o,
......
board/spec/xwrc_board_spec.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-03-08
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -93,7 +93,7 @@ entity xwrc_board_spec is
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
......@@ -309,7 +309,7 @@ begin -- architecture struct
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_10m_ext_ref_i,
clk_10m_ext_i => clk_10m_ext_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_i => clk_125m_pllref_buf,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
......@@ -418,7 +418,7 @@ begin -- architecture struct
clk_dmtd_i => clk_pll_dmtd,
clk_ref_i => clk_pll_125m,
clk_aux_i => clk_aux_i,
clk_ext_i => clk_10m_ext,
clk_10m_ext_i => clk_10m_ext,
clk_ext_mul_i => ext_ref_mul,
clk_ext_mul_locked_i => ext_ref_mul_locked,
clk_ext_stopped_i => ext_ref_mul_stopped,
......
board/svec/wr_svec_pkg.vhd
View file @ 8e07dc58
......@@ -31,7 +31,7 @@ package wr_svec_pkg is
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
......@@ -130,7 +130,7 @@ package wr_svec_pkg is
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
......
board/svec/wrc_board_svec.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-03-08
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -90,7 +90,7 @@ entity wrc_board_svec is
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
......@@ -395,7 +395,7 @@ begin -- architecture struct
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_ref_i => clk_10m_ext_ref_i,
clk_10m_ext_i => clk_10m_ext_i,
pps_ext_i => pps_ext_i,
clk_sys_62m5_o => clk_sys_62m5_o,
clk_ref_125m_o => clk_ref_125m_o,
......
board/svec/xwrc_board_svec.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-03-08
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -93,7 +93,7 @@ entity xwrc_board_svec is
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
......@@ -315,7 +315,7 @@ begin -- architecture struct
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_10m_ext_ref_i,
clk_10m_ext_i => clk_10m_ext_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_i => clk_125m_pllref_buf,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
......@@ -430,7 +430,7 @@ begin -- architecture struct
clk_dmtd_i => clk_pll_dmtd,
clk_ref_i => clk_pll_125m,
clk_aux_i => clk_aux_i,
clk_ext_i => clk_10m_ext,
clk_10m_ext_i => clk_10m_ext,
clk_ext_mul_i => ext_ref_mul,
clk_ext_mul_locked_i => ext_ref_mul_locked,
clk_ext_stopped_i => ext_ref_mul_stopped,
......
board/vfchd/wr_vfchd_pkg.vhd
View file @ 8e07dc58
......@@ -28,7 +28,7 @@ package wr_vfchd_pkg is
clk_board_125m_i : in std_logic;
clk_board_20m_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_10m_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
areset_n_i : in std_logic;
clk_sys_62m5_o : out std_logic;
......@@ -112,7 +112,7 @@ package wr_vfchd_pkg is
clk_board_125m_i : in std_logic;
clk_board_20m_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_10m_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
areset_n_i : in std_logic;
clk_sys_62m5_o : out std_logic;
......
board/vfchd/wrc_board_vfchd.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-03-08
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -89,7 +89,7 @@ entity wrc_board_vfchd is
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_ext_10m_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- Reset input (active low, can be async)
......@@ -377,7 +377,7 @@ begin -- architecture struct
clk_board_125m_i => clk_board_125m_i,
clk_board_20m_i => clk_board_20m_i,
clk_aux_i => clk_aux_i,
clk_ext_10m_i => clk_ext_10m_i,
clk_10m_ext_i => clk_10m_ext_i,
areset_n_i => areset_n_i,
clk_sys_62m5_o => clk_sys_62m5_o,
clk_ref_125m_o => clk_ref_125m_o,
......
board/vfchd/xwrc_board_vfchd.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-03-08
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -87,7 +87,7 @@ entity xwrc_board_vfchd is
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_ext_10m_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- Reset input (active low, can be async)
......@@ -285,7 +285,7 @@ begin -- architecture struct
g_pcs_16bit => g_pcs_16bit)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_ext_10m_i,
clk_10m_ext_i => clk_10m_ext_i,
clk_20m_vcxo_i => clk_board_20m_i,
clk_125m_pllref_i => clk_board_125m_i,
sfp_tx_o => sfp_tx_o,
......@@ -416,7 +416,7 @@ begin -- architecture struct
clk_dmtd_i => clk_pll_dmtd,
clk_ref_i => clk_pll_125m,
clk_aux_i => clk_aux_i,
clk_ext_i => clk_10m_ext,
clk_10m_ext_i => clk_10m_ext,
clk_ext_mul_i => ext_ref_mul,
clk_ext_mul_locked_i => ext_ref_mul_locked,
clk_ext_stopped_i => '0',
......
top/spec_ref_design/spec_wr_ref_top.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-20
-- Last update: 2017-03-08
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SPEC.
......@@ -425,7 +425,7 @@ begin -- architecture top
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_ref_i => clk_ext_10m,
clk_10m_ext_i => clk_ext_10m,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
......
top/svec_ref_design/svec_wr_ref_top.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-02-22
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SVEC.
......@@ -356,7 +356,7 @@ begin -- architecture top
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_ref_i => clk_ext_ref,
clk_10m_ext_i => clk_ext_ref,
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
......
top/vfchd_ref_design/vfchd_wr_ref_top.vhd
View file @ 8e07dc58
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-01-24
-- Last update: 2017-02-24
-- Last update: 2017-03-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the VFC-HD.
......@@ -404,7 +404,7 @@ begin -- architecture top
port map (
clk_board_125m_i => clk_board_125m_i,
clk_board_20m_i => clk_board_20m_i,
clk_ext_10m_i => clk_ext_ref,
clk_10m_ext_i => clk_ext_ref,
areset_n_i => areset_n_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
......
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