Commit 83501b68 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'peter_clbv2_3_4_ref_design_191119' into proposed_master

parents faf5e9a3 2b4daa08
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try:
if board in ["spec", "svec", "vfchd", "common"]:
if board in ["spec", "svec", "vfchd", "clbv2", "clbv3", "clbv4", "common"]:
modules = {"local" : [ board ] }
except NameError:
pass
......@@ -282,6 +282,8 @@ package wr_clbv2_pkg is
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
......
......@@ -287,6 +287,8 @@ package wr_clbv3_pkg is
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
......
files = [
"wr_clbv4_pkg.vhd",
"xwrc_board_clbv4.vhd",
"wrc_board_clbv4.vhd",
]
modules = {
"local" : [
"../common",
]
}
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for CLBv4
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_clbv4_pkg.vhd
-- Author(s) : Pascal Bos
-- Company : Nikhef
-- Created : 2019-06-18
-- Last update: 2019-06-18
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.streamers_pkg.all;
package wr_CLBv4_pkg is
component xwrc_board_clbv4 is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_125m_dmtd_n_i : in std_logic;
clk_125m_dmtd_p_i : in std_logic;
clk_125m_gtx_n_i : in std_logic;
clk_125m_gtx_p_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_62m5_o : out std_logic;
clk_dmtd_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_clbv4;
component wrc_board_clbv4 is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "PLAINFBRC";
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_125m_dmtd_n_i : in std_logic;
clk_125m_dmtd_p_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
wrf_src_adr_o : out std_logic_vector(1 downto 0);
wrf_src_dat_o : out std_logic_vector(15 downto 0);
wrf_src_cyc_o : out std_logic;
wrf_src_stb_o : out std_logic;
wrf_src_we_o : out std_logic;
wrf_src_sel_o : out std_logic_vector(1 downto 0);
wrf_src_ack_i : in std_logic;
wrf_src_stall_i : in std_logic;
wrf_src_err_i : in std_logic;
wrf_src_rty_i : in std_logic;
wrf_snk_adr_i : in std_logic_vector(1 downto 0);
wrf_snk_dat_i : in std_logic_vector(15 downto 0);
wrf_snk_cyc_i : in std_logic;
wrf_snk_stb_i : in std_logic;
wrf_snk_we_i : in std_logic;
wrf_snk_sel_i : in std_logic_vector(1 downto 0);
wrf_snk_ack_o : out std_logic;
wrf_snk_stall_o : out std_logic;
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_tx_cfg_mac_t_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
wrs_tx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_cfg_acc_b_i : in std_logic := '1';
wrs_rx_cfg_flt_r_i : in std_logic := '0';
wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0) := x"0000000";
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
wb_eth_we_o : out std_logic;
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tstamps_stb_o : out std_logic;
tstamps_tsval_o : out std_logic_vector(31 downto 0);
tstamps_port_id_o : out std_logic_vector(5 downto 0);
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component wrc_board_clbv4;
end wr_clbv4_pkg;
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for clbv4
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wrc_board_clbv4.vhd
-- Author(s) : Pascal Bos <bosp@nikhef.nl>
-- Company : Nikhef
-- Created : 2019-05-22
-- Last update: 2019-05-22
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the clbv4 board.
-- Version with no VHDL records on the top-level (mainly for Verilog
-- instantiation).
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
use work.etherbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv4_pkg.all;
entity wrc_board_clbv4 is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : integer := 1;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- "plainfbrc" = expose WRC fabric interface
-- "streamers" = attach WRC streamers to fabric interface
-- "etherbone" = attach Etherbone slave to fabric interface
g_fabric_iface : string := "plainfbrc";
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_125m_dmtd_p_i : in std_logic;
clk_125m_dmtd_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_62m5_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
---------------------------------------------------------------------------
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
wrf_src_adr_o : out std_logic_vector(1 downto 0);
wrf_src_dat_o : out std_logic_vector(15 downto 0);
wrf_src_cyc_o : out std_logic;
wrf_src_stb_o : out std_logic;
wrf_src_we_o : out std_logic;
wrf_src_sel_o : out std_logic_vector(1 downto 0);
wrf_src_ack_i : in std_logic;
wrf_src_stall_i : in std_logic;
wrf_src_err_i : in std_logic;
wrf_src_rty_i : in std_logic;
wrf_snk_adr_i : in std_logic_vector(1 downto 0);
wrf_snk_dat_i : in std_logic_vector(15 downto 0);
wrf_snk_cyc_i : in std_logic;
wrf_snk_stb_i : in std_logic;
wrf_snk_we_i : in std_logic;
wrf_snk_sel_i : in std_logic_vector(1 downto 0);
wrf_snk_ack_o : out std_logic;
wrf_snk_stall_o : out std_logic;
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_tx_cfg_mac_t_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
wrs_tx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_cfg_acc_b_i : in std_logic := '1';
wrs_rx_cfg_flt_r_i : in std_logic := '0';
wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0) := x"0000000";
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
wb_eth_we_o : out std_logic;
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
tstamps_stb_o : out std_logic;
tstamps_tsval_o : out std_logic_vector(31 downto 0);
tstamps_port_id_o : out std_logic_vector(5 downto 0);
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
);
end entity wrc_board_clbv4;
architecture std_wrapper of wrc_board_clbv4 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- WR fabric interface
signal wrf_src_out : t_wrf_source_out;
signal wrf_src_in : t_wrf_source_in;
signal wrf_snk_out : t_wrf_sink_out;
signal wrf_snk_in : t_wrf_sink_in;
-- External WB interface
-- Etherbone interface
-- Aux diagnostics
constant c_diag_ro_size : integer := g_diag_ro_vector_width/32;
constant c_diag_rw_size : integer := g_diag_rw_vector_width/32;
signal aux_diag_in : t_generic_word_array(c_diag_ro_size-1 downto 0);
signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
-- External Tx Timestamping I/F
signal timestamps_out : t_txtsu_timestamp;
-- streamers config
signal wrs_tx_cfg_in : t_tx_streamer_cfg;
signal wrs_rx_cfg_in : t_rx_streamer_cfg;
begin -- architecture struct
wrf_src_adr_o <= wrf_src_out.adr;
wrf_src_dat_o <= wrf_src_out.dat;
wrf_src_cyc_o <= wrf_src_out.cyc;
wrf_src_stb_o <= wrf_src_out.stb;
wrf_src_we_o <= wrf_src_out.we;
wrf_src_sel_o <= wrf_src_out.sel;
wrf_src_in.ack <= wrf_src_ack_i;
wrf_src_in.stall <= wrf_src_stall_i;
wrf_src_in.err <= wrf_src_err_i;
wrf_src_in.rty <= wrf_src_rty_i;
wrf_snk_in.adr <= wrf_snk_adr_i;
wrf_snk_in.dat <= wrf_snk_dat_i;
wrf_snk_in.cyc <= wrf_snk_cyc_i;
wrf_snk_in.stb <= wrf_snk_stb_i;
wrf_snk_in.we <= wrf_snk_we_i;
wrf_snk_in.sel <= wrf_snk_sel_i;
wrf_snk_ack_o <= wrf_snk_out.ack;
wrf_snk_stall_o <= wrf_snk_out.stall;
wrf_snk_err_o <= wrf_snk_out.err;
wrf_snk_rty_o <= wrf_snk_out.rty;
aux_diag_in <= f_de_vectorize_diag(aux_diag_i, g_diag_ro_vector_width);
aux_diag_o <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width);
tstamps_stb_o <= timestamps_out.stb;
tstamps_tsval_o <= timestamps_out.tsval;
tstamps_port_id_o <= timestamps_out.port_id;
tstamps_frame_id_o <= timestamps_out.frame_id;
wrs_tx_cfg_in.mac_local <= wrs_tx_cfg_mac_l_i;
wrs_tx_cfg_in.mac_target <= wrs_tx_cfg_mac_t_i;
wrs_tx_cfg_in.ethertype <= wrs_tx_cfg_etype_i;
wrs_rx_cfg_in.mac_local <= wrs_rx_cfg_mac_l_i;
wrs_rx_cfg_in.mac_remote <= wrs_rx_cfg_mac_r_i;
wrs_rx_cfg_in.ethertype <= wrs_rx_cfg_etype_i;
wrs_rx_cfg_in.accept_broadcasts <= wrs_rx_cfg_acc_b_i;
wrs_rx_cfg_in.filter_remote <= wrs_rx_cfg_flt_r_i;
wrs_rx_cfg_in.fixed_latency <= wrs_rx_cfg_fix_l_i;
-- Instantiate the records-based module
cmp_xwrc_board_clbv4 : xwrc_board_clbv4
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_aux_clks => g_aux_clks,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_dpram_initf => g_dpram_initf,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => c_diag_ro_size,
g_diag_rw_size => c_diag_rw_size)
port map (
areset_n_i => areset_n_i,
areset_edge_n_i => areset_edge_n_i,
clk_125m_dmtd_p_i => clk_125m_dmtd_p_i,
clk_125m_dmtd_n_i => clk_125m_dmtd_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_10m_ext_i,
pps_ext_i => pps_ext_i,
clk_sys_62m5_o => clk_sys_62m5_o,
clk_ref_62m5_o => clk_ref_62m5_o,
rst_sys_62m5_n_o => rst_sys_62m5_n_o,
rst_ref_62m5_n_o => rst_ref_62m5_n_o,
dac_refclk_cs_n_o => dac_refclk_cs_n_o,
dac_refclk_sclk_o => dac_refclk_sclk_o,
dac_refclk_din_o => dac_refclk_din_o,
dac_dmtd_cs_n_o => dac_dmtd_cs_n_o,
dac_dmtd_sclk_o => dac_dmtd_sclk_o,
dac_dmtd_din_o => dac_dmtd_din_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_det_i,
sfp_sda_i => sfp_sda_i,
sfp_sda_o => sfp_sda_o,
sfp_scl_i => sfp_scl_i,
sfp_scl_o => sfp_scl_o,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_i,
eeprom_sda_o => eeprom_sda_o,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
onewire_i => onewire_i,
onewire_oen_o => onewire_oen_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
wrf_src_o => wrf_src_out,
wrf_src_i => wrf_src_in,
wrf_snk_o => wrf_snk_out,
wrf_snk_i => wrf_snk_in,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_in,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_in,
aux_diag_i => aux_diag_in,
aux_diag_o => aux_diag_out,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
timestamps_o => timestamps_out,
timestamps_ack_i => tstamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
led_act_o => led_act_o,
led_link_o => led_link_o,
btn1_i => btn1_i,
btn2_i => btn2_i,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o);
end architecture std_wrapper;
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for clbv4
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_board_clbv4.vhd
-- Author(s) : Pascal Bos <bosp@nikhef.nl>
-- Company : Nikhef
-- Created : 2019-05-06
-- Last update: 2019-05-06
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the clbv3 board.
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
--use work.etherbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv4_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity xwrc_board_clbv4 is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := TRUE;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 1;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset input (active low, can be async)
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_125m_dmtd_n_i : in std_logic; -- 124.992 MHz
clk_125m_dmtd_p_i : in std_logic;
clk_125m_gtx_n_i : in std_logic;
clk_125m_gtx_p_i : in std_logic;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 62.5MHz ref clock output
clk_ref_62m5_o : out std_logic;
-- 124.992 / 2 = 62.496 MHz dmtd clock output
clk_dmtd_62m5_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
---------------------------------------------------------------------------
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- No External WB interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
---------------------------------------------------------------------------
-- No Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
);
end entity xwrc_board_clbv4;
architecture struct of xwrc_board_clbv4 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- IBUFDS
signal clk_125m_dmtd_buf : std_logic;
signal clk_dmtd : std_logic;
-- PLLs, clocks
signal clk_pll_62m5 : std_logic;
signal clk_ref_62m5 : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
-- Reset logic
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DACs
signal dac_dmtd_load : std_logic;
signal dac_dmtd_data : std_logic_vector(15 downto 0);
signal dac_refclk_load : std_logic;
signal dac_refclk_data : std_logic_vector(15 downto 0);
-- OneWire
signal onewire_in : std_logic_vector(1 downto 0);
signal onewire_en : std_logic_vector(1 downto 0);
-- PHY
signal phy16_to_wrc : t_phy_16bits_to_wrc;
signal phy16_from_wrc : t_phy_16bits_from_wrc;
-- External reference
signal ext_ref_mul : std_logic;
signal ext_ref_mul_locked : std_logic;
signal ext_ref_mul_stopped : std_logic;
signal ext_ref_rst : std_logic;
begin -- architecture struct
-----------------------------------------------------------------------------
-- Platform-dependent part (PHY, PLLs, buffers, etc)
-----------------------------------------------------------------------------
cmp_ibufgds_dmtd : IBUFGDS
generic map (
DIFF_TERM => TRUE)
port map (
O => clk_125m_dmtd_buf,
I => clk_125m_dmtd_p_i,
IB => clk_125m_dmtd_n_i);
clk_dmtd_62m5_o <= clk_dmtd;
cmp_xwrc_platform : xwrc_platform_xilinx
generic map (
g_fpga_family => "kintex7",
g_direct_dmtd => TRUE,
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_10m_ext_i,
clk_125m_dmtd_i => clk_125m_dmtd_buf,
clk_125m_gtp_p_i => clk_125m_gtx_p_i, --Note clbv4 used GTX instead of GTPs
clk_125m_gtp_n_i => clk_125m_gtx_n_i,
sfp_txn_o => sfp_txn_o,
sfp_txp_o => sfp_txp_o,
sfp_rxn_i => sfp_rxn_i,
sfp_rxp_i => sfp_rxp_i,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_los_i => sfp_los_i,
sfp_tx_disable_o => sfp_tx_disable_o,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_ref_62m5, -- Note: This is a 62m5 Clock for 16 bit PHYs!
clk_62m5_dmtd_o => clk_dmtd,
pll_locked_o => pll_locked,
clk_10m_ext_o => clk_10m_ext,
phy16_o => phy16_to_wrc,
phy16_i => phy16_from_wrc,
ext_ref_mul_o => ext_ref_mul,
ext_ref_mul_locked_o => ext_ref_mul_locked,
ext_ref_mul_stopped_o => ext_ref_mul_stopped,
ext_ref_rst_i => ext_ref_rst);
clk_sys_62m5_o <= clk_pll_62m5;
clk_ref_62m5_o <= clk_ref_62m5;
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_pll_62m5,
rst_n_i => '1',
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_ref_62m5;
cmp_rstlogic_reset : gc_reset
generic map (
g_clocks => 2, -- 62.5MHz, 125MHz
g_logdelay => 4, -- 16 clock cycles
g_syncdepth => 3) -- length of sync chains
port map (
free_clk_i => clk_125m_dmtd_buf,
locked_i => rstlogic_arst_n,
clks_i => rstlogic_clk_in,
rstn_o => rstlogic_rst_out);
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0);
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_62m5_n_o <= rstlogic_rst_out(1);
-----------------------------------------------------------------------------
-- 2x SPI DAC
-----------------------------------------------------------------------------
cmp_dmtd_dac : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_pll_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_dmtd_data,
cs_sel_i => "1",
load_i => dac_dmtd_load,
sclk_divsel_i => "001",
dac_cs_n_o(0) => dac_dmtd_cs_n_o,
dac_sclk_o => dac_dmtd_sclk_o,
dac_sdata_o => dac_dmtd_din_o);
cmp_refclk_dac : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_pll_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_refclk_data,
cs_sel_i => "1",
load_i => dac_refclk_load,
sclk_divsel_i => "001",
dac_cs_n_o(0) => dac_refclk_cs_n_o,
dac_sclk_o => dac_refclk_sclk_o,
dac_sdata_o => dac_refclk_din_o);
-----------------------------------------------------------------------------
-- The WR PTP core with optional fabric interface attached
-----------------------------------------------------------------------------
cmp_board_common : xwrc_board_common
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "CLB4",
g_phys_uart => TRUE,
g_virtual_uart => TRUE,
g_aux_clks => g_aux_clks,
g_ep_rxbuf_size => 1024,
g_tx_runt_padding => TRUE,
g_dpram_initf => g_dpram_initf,
g_dpram_size => 131072/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_aux_sdb => c_wrc_periph3_sdb,
g_softpll_enable_debugger => FALSE,
g_vuart_fifo_size => 1024,
g_pcs_16bit => TRUE,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_fabric_iface => g_fabric_iface
)
port map (
clk_sys_i => clk_pll_62m5,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_ref_62m5,
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext,
clk_ext_mul_i => ext_ref_mul,
clk_ext_mul_locked_i => ext_ref_mul_locked,
clk_ext_stopped_i => ext_ref_mul_stopped,
clk_ext_rst_o => ext_ref_rst,
pps_ext_i => pps_ext_i,
rst_n_i => rst_62m5_n,
dac_hpll_load_p1_o => dac_dmtd_load,
dac_hpll_data_o => dac_dmtd_data,
dac_dpll_load_p1_o => dac_refclk_load,
dac_dpll_data_o => dac_refclk_data,
phy16_o => phy16_from_wrc,
phy16_i => phy16_to_wrc,
scl_o => eeprom_scl_o,
scl_i => eeprom_scl_i,
sda_o => eeprom_sda_o,
sda_i => eeprom_sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_det_i,
spi_sclk_o => open,
spi_ncs_o => open,
spi_mosi_o => open,
spi_miso_i => '0',
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
owr_pwren_o => open,
owr_en_o => onewire_en,
owr_i => onewire_in,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_i,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_i,
aux_diag_i => aux_diag_i,
aux_diag_o => aux_diag_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
timestamps_o => timestamps_o,
timestamps_ack_i => timestamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
led_act_o => led_act_o,
led_link_o => led_link_o,
btn1_i => btn1_i,
btn2_i => btn2_i,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o);
sfp_rate_select_o <= '1';
onewire_oen_o <= onewire_en(0);
onewire_in(0) <= onewire_i;
onewire_in(1) <= '1';
end architecture struct;
board = "clbv2"
target = "xilinx"
action = "synthesis"
......@@ -6,8 +7,8 @@ syn_grade = "-2"
syn_package = "fbg676"
syn_top = "clbv2_wr_ref_top"
syn_project = "clbv2_wr_ref.xise"
syn_project = "clbv2_wr_ref.xpr"
syn_tool = "ise"
syn_tool = "vivado"
modules = { "local" : "../../top/clbv2_ref_design/"}
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../board/clbv2/xwrc_board_clbv2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_aligner.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xtx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/streamers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../board/common/xwrc_board_common.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../top/clbv2_ref_design/clbv2_wr_ref_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_diags_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/wr_streamers_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../board/common/wr_board_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../board/clbv2/wr_clbv2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/escape_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../modules/wrc_core/xwrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/escape_inserter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/streamers_priv_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_packet_injection.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="127"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="129"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="130"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="131"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="133"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../platform/xilinx/xwrc_platform_xilinx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../top/clbv2_ref_design/clbv2_wr_ref_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="138"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="139"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="140"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="151"/>
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="153"/>
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="155"/>
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="158"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="159"/>
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/dropping_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="160"/>
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="161"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="162"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="163"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="165"/>
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="166"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k160t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|clbv2_wr_ref_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clbv2_wr_ref_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="clbv2_wr_ref_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fbg676" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="clbv2_wr_ref_top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="clbv2_wr_ref_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="clbv2_wr_ref_top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="clbv2_wr_ref_top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="clbv2_wr_ref.xise" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-11-30T12:58:29" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9A7162D46C074C4395ECD9E6FDD4DA79" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
board = "clbv3"
target = "xilinx"
action = "synthesis"
......@@ -6,8 +7,8 @@ syn_grade = "-2"
syn_package = "fbg484"
syn_top = "clbv3_wr_ref_top"
syn_project = "clbv3_wr_ref.xise"
syn_project = "clbv3_wr_ref.xpr"
syn_tool = "ise"
syn_tool = "vivado"
modules = { "local" : "../../top/clbv3_ref_design/"}
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/streamers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../platform/xilinx/xwrc_platform_xilinx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/escape_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xtx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../board/common/xwrc_board_common.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_diags_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/wr_streamers_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../top/clbv3_ref_design/clbv3_wr_ref_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../board/common/wr_board_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../board/clbv3/xwrc_board_clbv3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../modules/wrc_core/xwrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/escape_inserter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_aligner.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/streamers_priv_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_packet_injection.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="127"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="129"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="130"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../board/clbv3/wr_clbv3_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="131"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="133"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="138"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="139"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="140"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../top/clbv3_ref_design/clbv3_wr_ref_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="151"/>
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="153"/>
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="155"/>
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="158"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="159"/>
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/dropping_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="160"/>
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="161"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="162"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="163"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="165"/>
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="166"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="167"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc7a200t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Artix7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|clbv3_wr_ref_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clbv3_wr_ref_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="clbv3_wr_ref_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fbg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="clbv3_wr_ref_top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="clbv3_wr_ref_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="clbv3_wr_ref_top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="clbv3_wr_ref_top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="clbv3_wr_ref.xise" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="artix7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-11-30T10:38:33" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8A25E8A3E6524895B535944C55324846" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
board = "clbv4"
target = "xilinx"
action = "synthesis"
syn_device = "xc7k160t"
syn_grade = "-2"
syn_package = "fbg676"
syn_top = "clbv4_wr_ref_top"
syn_project = "clbv4_wr_ref.xpr"
syn_tool = "vivado"
modules = { "local" : "../../top/clbv4_ref_design/"}
......@@ -2,14 +2,13 @@ fetchto = "../../ip_cores"
files = [
"clbv2_wr_ref_top.vhd",
"clbv2_wr_ref_top.ucf",
"clbv2_wr_ref_top.xdc",
"clbv2_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
"../../board/clbv2",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
......
......@@ -30,38 +30,38 @@
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
# ---------------------------------------------------------------------------`
# -- Clocks/resets
# ---------------------------------------------------------------------------
# -- Local oscillators
NET "clk_20m_vcxo_i" LOC = F22 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- 20MHz VCXO clock
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
#NET "clk_125m_pllref_p_i" LOC = F6 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz PLL reference
#NET "clk_125m_pllref_n_i" LOC = F5 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz PLL reference
#NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
#TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
#NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
#TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtx_p_i" LOC = D6 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz GTX reference
NET "clk_125m_gtx_n_i" LOC = D5 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz GTX reference
NET "clk_125m_gtx_p_i" TNM_NET = clk_125m_gtx_p_i;
TIMESPEC TS_clk_125m_gtx_p_i = PERIOD "clk_125m_gtx_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtx_n_i" TNM_NET = clk_125m_gtx_n_i;
TIMESPEC TS_clk_125m_gtx_n_i = PERIOD "clk_125m_gtx_n_i" 8 ns HIGH 50%;
# ---------------------------------------------------------------------------
# -- SPI interface to DACs
# ---------------------------------------------------------------------------
NET "pll25dac_cs_n_o" LOC = A14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V -- cs1
NET "pll20dac_cs_n_o" LOC = A15 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V -- cs2
NET "plldac_din_o" LOC = A13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "plldac_sclk_o" LOC = A12 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
NET "sfp_txp_o" LOC = A4; #Bank 116
NET "sfp_txn_o" LOC = A3; #Bank 116
NET "sfp_rxp_i" LOC = B6; #Bank 116
NET "sfp_rxn_i" LOC = B5; #Bank 116
NET "sfp_mod_def0_i" LOC = E26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sfp detect
NET "sfp_mod_def1_b" LOC = J26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- scl
NET "sfp_mod_def2_b" LOC = H26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sda
NET "sfp_rate_select_o" LOC = G26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_fault_i" LOC = C26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_disable_o" LOC = D26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_los_i" LOC = F25 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- Onewire interface
# ---------------------------------------------------------------------------
NET "onewire_b" LOC = L23 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- UART
# ---------------------------------------------------------------------------
#TEST & DEBUG
# Signal uart_txd_o is an output in the design and must be connected to pin 20/12 (RXD_I) of U34 (CP2105GM)
# Signal uart_rxd_i is an input in the design and must be connected to pin 21/13 (TXD_O) of U34 (CP2105GM)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
NET "uart_rxd_i" LOC = D19 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
NET "uart_txd_o" LOC = D20 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "USB_RX2" LOC = C19 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
#NET "USB_TX2" LOC = B19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#USB Connection on Test&Debug Connector (J35)
#NET "USBEXT_RX1" LOC = F14 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX1" LOC = F13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_RX2" LOC = C14 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX2" LOC = C13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- Flash memory SPI interface
# ---------------------------------------------------------------------------
# flash_sclk_o : out std_logic;
# flash_ncs_o : out std_logic;
# flash_mosi_o : out std_logic;
# flash_miso_i : in std_logic;
# ---------------------------------------------------------------------------
# -- Miscellanous CLBv2 pins
# ---------------------------------------------------------------------------
#NET "GPIO_LED[0]" LOC = C16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
NET "led_act_o" LOC = C16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V -- LED D2: blinking indicates that packets are being transferred.
#NET "GPIO_LED[1]" LOC = B16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[2]" LOC = B17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[3]" LOC = A17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[4]" LOC = A18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[5]" LOC = A19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
NET "led_link_o" LOC = A19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V -- LED D7: indicates if the link is up.
NET "reset_i" LOC = E11 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V --Reset
# ---------------------------------------------------------------------------
# -- Digital I/O FMC Pins
# -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
# -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
# ---------------------------------------------------------------------------
# -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
# -- external reference input.
NET "dio_clk_p_i" LOC = Y22 | IOSTANDARD=LVDS_25; #CLK1_M2C_P
NET "dio_clk_n_i" LOC = AA22 | IOSTANDARD=LVDS_25; #CLK1_M2C_N
# -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
# -- the mezzanine front panel.
NET "dio_p_i[4]" LOC = N21 | IOSTANDARD=LVDS_25; #LA00_P
NET "dio_n_i[4]" LOC = N22 | IOSTANDARD=LVDS_25; #LA00_N
NET "dio_p_i[3]" LOC = P16 | IOSTANDARD=LVDS_25; #LA03_P
NET "dio_n_i[3]" LOC = N17 | IOSTANDARD=LVDS_25; #LA03_N
NET "dio_p_i[2]" LOC = AB26 | IOSTANDARD=LVDS_25; #LA16_P
NET "dio_n_i[2]" LOC = AC26 | IOSTANDARD=LVDS_25; #LA16_N
NET "dio_p_i[1]" LOC = K20 | IOSTANDARD=LVDS_25; #LA20_P
NET "dio_n_i[1]" LOC = J20 | IOSTANDARD=LVDS_25; #LA20_N
NET "dio_p_i[0]" LOC = P19 | IOSTANDARD=LVDS_25; #LA33_P
NET "dio_n_i[0]" LOC = P20 | IOSTANDARD=LVDS_25; #LA33_N
# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
# -- of I/O (N+1) on the front panel of the mezzanine
NET "dio_p_o[4]" LOC = N18 | IOSTANDARD=LVDS_25; #LA04_P
NET "dio_n_o[4]" LOC = M19 | IOSTANDARD=LVDS_25; #LA04_N
NET "dio_p_o[3]" LOC = U19 | IOSTANDARD=LVDS_25; #LA07_P
NET "dio_n_o[3]" LOC = U20 | IOSTANDARD=LVDS_25; #LA07_N
NET "dio_p_o[2]" LOC = W20 | IOSTANDARD=LVDS_25; #LA08_P
NET "dio_n_o[2]" LOC = Y21 | IOSTANDARD=LVDS_25; #LA08_N
NET "dio_p_o[1]" LOC = M21 | IOSTANDARD=LVDS_25; #LA28_P
NET "dio_n_o[1]" LOC = M22 | IOSTANDARD=LVDS_25; #LA28_N
NET "dio_p_o[0]" LOC = N19 | IOSTANDARD=LVDS_25; #LA29_P
NET "dio_n_o[0]" LOC = M20 | IOSTANDARD=LVDS_25; #LA29_N
# -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
# -- panel is configured as an output.
NET "dio_oe_n_o[4]" LOC = AE22 | IOSTANDARD=LVCMOS25; #LA05_P
NET "dio_oe_n_o[3]" LOC = U26 | IOSTANDARD=LVCMOS25; #LA11_P
NET "dio_oe_n_o[2]" LOC = AB25 | IOSTANDARD=LVCMOS25; #LA15_N
NET "dio_oe_n_o[1]" LOC = N23 | IOSTANDARD=LVCMOS25; #LA24_N
NET "dio_oe_n_o[0]" LOC = P24 | IOSTANDARD=LVCMOS25; #LA30_P
# -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
# -- panel is 50-ohm terminated
NET "dio_term_en_o[4]" LOC = P25 | IOSTANDARD=LVCMOS25; #LA09_N
NET "dio_term_en_o[3]" LOC = R25 | IOSTANDARD=LVCMOS25; #LA09_P
NET "dio_term_en_o[2]" LOC = AF22 | IOSTANDARD=LVCMOS25; #LA05_N
NET "dio_term_en_o[1]" LOC = AF25 | IOSTANDARD=LVCMOS25; #LA06_N
NET "dio_term_en_o[0]" LOC = N24 | IOSTANDARD=LVCMOS25; #LA30_N
# -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
# -- blink 1-PPS.
NET "dio_led_top_o" LOC = R21 | IOSTANDARD=LVCMOS25; #LA01_P
NET "dio_led_bot_o" LOC = P21 | IOSTANDARD=LVCMOS25; #LA01_N
# -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
# -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
NET "dio_scl_b" LOC = D24 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "dio_sda_b" LOC = D23 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- GPIO connector
# ---------------------------------------------------------------------------
#NET "GPIO[1]" LOC = H8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[2]" LOC = J8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[3]" LOC = G9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[4]" LOC = H9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[5]" LOC = F8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[6]" LOC = G10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[7]" LOC = F9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[8]" LOC = F10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[9]" LOC = D9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[10]" LOC = D8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[11]" LOC = B9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[12]" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[13]" LOC = A9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[14]" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[15]" LOC = A10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "GPIO[16]" LOC = B10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#FMC SIGNALS CLK LPC
#NET "FMC_CLK0_M2C_P" LOC = Y23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_CLK0_M2C_N" LOC = AA24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_P" LOC = Y22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_N" LOC = AA22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA00_CC_P" LOC = N21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA00_CC_N" LOC = N22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA01_CC_P" LOC = R21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA01_CC_N" LOC = P21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA17_CC_P" LOC = R22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA17_CC_N" LOC = R23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA18_CC_P" LOC = AA23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA18_CC_N" LOC = AB24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#FMC SIGNALS CLK HPC
#NET "FMC_HA00_CC_P" LOC = AC23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA00_CC_N" LOC = AC24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA01_CC_P" LOC = F17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA01_CC_N" LOC = E17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA17_CC_P" LOC = E18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA17_CC_N" LOC = D18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
########################################################
#FMC SIGNALS LPC
#NET "FMC_PRSNT_B" LOC = K21 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "FMC_LA02_P" LOC = H19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA02_N" LOC = G20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA03_P" LOC = P16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA03_N" LOC = N17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA04_P" LOC = N18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA04_N" LOC = M19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA05_P" LOC = AE22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA05_N" LOC = AF22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 23
#NET "FMC_LA06_P" LOC = AF24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 25
#NET "FMC_LA06_N" LOC = AF25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 27
#NET "FMC_LA07_P" LOC = U19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 29
#NET "FMC_LA07_N" LOC = U20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 31
#NET "FMC_LA08_P" LOC = W20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 33
#NET "FMC_LA08_N" LOC = Y21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 35
#NET "FMC_LA09_P" LOC = R25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
#NET "FMC_LA09_N" LOC = P25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
#NET "FMC_LA10_P" LOC = U24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA10_N" LOC = U25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA11_P" LOC = U26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA11_N" LOC = V26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA12_P" LOC = R26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA12_N" LOC = P26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA13_P" LOC = AE23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA13_N" LOC = AF23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA14_P" LOC = AD23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA14_N" LOC = AD24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA15_P" LOC = AA25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA15_N" LOC = AB25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA16_P" LOC = AB26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA16_N" LOC = AC26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA19_P" LOC = W23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 38
#NET "FMC_LA19_N" LOC = W24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 40
#NET "FMC_LA20_P" LOC = K20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA20_N" LOC = J20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA21_P" LOC = M25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA21_N" LOC = L25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA22_P" LOC = L19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA22_N" LOC = L20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA23_P" LOC = K25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA23_N" LOC = K26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA24_P" LOC = P23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA24_N" LOC = N23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_P" LOC = N26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_N" LOC = M26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA26_P" LOC = T22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA26_N" LOC = T23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA27_P" LOC = V23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA27_N" LOC = V24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_LA28_P" LOC = M21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA28_N" LOC = M22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_P" LOC = N19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_N" LOC = M20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA30_P" LOC = P24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA30_N" LOC = N24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA31_P" LOC = M24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA31_N" LOC = L24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA32_P" LOC = T20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA32_N" LOC = R20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA33_P" LOC = P19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA33_N" LOC = P20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#FMC SIGNALS HPC
#NET "FMC_HA02_P" LOC = J18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA02_N" LOC = J19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA03_P" LOC = G19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA03_N" LOC = F20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA04_P" LOC = F19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA04_N" LOC = E20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA05_P" LOC = H17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA05_N" LOC = H18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA06_P" LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA06_N" LOC = K17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA07_P" LOC = M17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA07_N" LOC = L18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA08_P" LOC = R16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA08_N" LOC = R17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA09_P" LOC = R18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA09_N" LOC = P18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA10_P" LOC = T18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA10_N" LOC = T19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA11_P" LOC = U17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA11_N" LOC = T17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA12_P" LOC = AB21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA12_N" LOC = AC21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA13_P" LOC = AD21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA13_N" LOC = AE21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA14_P" LOC = V21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA14_N" LOC = W21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA15_P" LOC = U22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA15_N" LOC = V22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA16_P" LOC = T24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA16_N" LOC = T25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
#NET "FMC_HA18_P" LOC = W25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA18_N" LOC = W26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA19_P" LOC = AD26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA19_N" LOC = AE26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA20_P" LOC = AD25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA20_N" LOC = AE25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA21_P" LOC = Y25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA21_N" LOC = Y26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA22_P" LOC = AB22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA22_N" LOC = AC22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
#NET "FMC_HA23_P" LOC = L17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#NET "FMC_HA23_N" LOC = K18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
#OCTOPUS SMALL
#NET "IIC1_SDA" LOC = J13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "IIC1_SCL" LOC = H13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "EN_SCLK" LOC = H12 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "PMT_P[0]" LOC = AD16 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[0]" LOC = AE16 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[1]" LOC = Y17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[1]" LOC = Y18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[2]" LOC = W18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[2]" LOC = W19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[3]" LOC = AD15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[3]" LOC = AE15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[4]" LOC = AA17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[4]" LOC = AA18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[5]" LOC = AA19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[5]" LOC = AA20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[6]" LOC = AC14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[6]" LOC = AD14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[7]" LOC = AC18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[7]" LOC = AD18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[8]" LOC = AB19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[8]" LOC = AB20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[9]" LOC = AF14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[9]" LOC = AF15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[10]" LOC = AB17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[10]" LOC = AC17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_P[11]" LOC = AD20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "PMT_N[11]" LOC = AE20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA0P" LOC = AE17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA0N" LOC = AF17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA1P" LOC = AE18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA1N" LOC = AF18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA2P" LOC = AF19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA2N" LOC = AF20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
#OCTOPUS LARGE
#NET "IIC2_SDA" LOC = H14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "IIC2_SCL" LOC = G14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "EN_LCLK" LOC = H11 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "PMT_P[12]" LOC = AE7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[12]" LOC = AF7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[13]" LOC = AF5 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[13]" LOC = AF4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[14]" LOC = AD1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[14]" LOC = AE1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[15]" LOC = AE8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[15]" LOC = AF8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[16]" LOC = AE6 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[16]" LOC = AE5 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[17]" LOC = AF3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[17]" LOC = AF2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[18]" LOC = AC8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[18]" LOC = AD8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[19]" LOC = AD4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[19]" LOC = AD3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[20]" LOC = AE3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[20]" LOC = AE2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[21]" LOC = AB7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[21]" LOC = AC7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[22]" LOC = AD6 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[22]" LOC = AD5 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[23]" LOC = AB1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[23]" LOC = AC1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[24]" LOC = AF10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[24]" LOC = AF9 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[25]" LOC = AC4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[25]" LOC = AC3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[26]" LOC = AB2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[26]" LOC = AC2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[27]" LOC = AC9 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[27]" LOC = AD9 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_P[28]" LOC = AA4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[28]" LOC = AB4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[29]" LOC = AA3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_N[29]" LOC = AA2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
#NET "PMT_P[30]" LOC = AD10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
#NET "PMT_N[30]" LOC = AE10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
\ No newline at end of file
......@@ -8,7 +8,7 @@
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Last update: 2019-06-28
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the CLBv2.
......@@ -54,14 +54,16 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv2_pkg.all;
--use work.gn4124_core_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clbv2_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy16.bram";
g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16.bram";
-- In Vivado Project-Mode, during a Synthesis run or an Implementation run, the Vivado working
-- directory temporarily changes to the "project_name/project_name.runs/run_name" directory.
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
......@@ -125,11 +127,20 @@ entity clbv2_wr_ref_top is
---------------------------------------------------------------------------
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
led_link_o : out std_logic;
-- Reset control
reset_i : in std_logic;
suicide : out std_logic;
reset_i : in std_logic;
-- Monitoring signals output on test-pads and External Debug Connector J35
pll_oe_out_b : out std_logic;
pps_p : out std_logic;
pps_n : out std_logic;
ref_clk_p : out std_logic;
ref_clk_n : out std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC Pins
......@@ -176,35 +187,6 @@ end entity clbv2_wr_ref_top;
architecture top of clbv2_wr_ref_top is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 2;
-- Number of slaves on the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_PCIE : integer := 0;
constant c_WB_MASTER_ETHBONE : integer := 1;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_WRC : integer := 0;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00040000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"));
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
......@@ -248,12 +230,13 @@ architecture top of clbv2_wr_ref_top is
begin -- architecture top
suicide<= '1';
reset_n <= not reset_i; -- Reset = high active on CLB
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
reset_n <= not reset_i; -- Reset = high active on CLB
cmp_xwrc_board_clbv2 : xwrc_board_clbv2
generic map (
g_simulation => g_simulation,
......@@ -338,13 +321,13 @@ begin -- architecture top
O => dio_p_o(i),
OB => dio_n_o(i));
end generate;
-- Configure Digital I/Os 0 to 3 as outputs
-- Configure Digital I/Os 0 to 2 as outputs
dio_oe_n_o(2 downto 0) <= (others => '0');
-- Configure Digital I/Os 3 and 4 as inputs for external reference
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
-- All DIO connectors are not terminated
dio_term_en_o <= (others => '0');
-- Configure Digital I/Os 3 to 4 inputs to be terminated.
dio_term_en_o <= "11000";
-- EEPROM I2C tri-states
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
......@@ -373,6 +356,21 @@ begin -- architecture top
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
-- Enable test-pad TP17, TP18 driver
pll_oe_out_b <= '0';
U_pps_mon_obuf : OBUFDS
port map (
I => wrc_pps_out,
O => pps_p,
OB => pps_n);
U_ref_clk_mon_obuf : OBUFDS
port map (
I => clk_ref_62m5,
O => ref_clk_p,
OB => ref_clk_n);
-- LEDs
U_Extend_PPS : gc_extend_pulse
generic map (
......
# ---------------------------------------------------------------------------`
# ---------------------------------------------------------------------------
# -- Clocks/resets
# ---------------------------------------------------------------------------
# -- Local oscillators
NET "clk_125m_dmtd_p_i" LOC = J19 | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V -- CVPD-922-124.992 MHz PLL reference
NET "clk_125m_dmtd_n_i" LOC = H19 | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V
#NET "clk_125m_dmtd_p_i" LOC = K18 | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V -- FRETHE025 5x25 MHz PLL reference
#NET "clk_125m_dmtd_n_i" LOC = K19 | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V
NET "clk_125m_dmtd_p_i" TNM_NET = clk_125m_dmtd_p_i;
TIMESPEC TS_dmtd_clk_p_i = PERIOD "clk_125m_dmtd_p_i" 8 ns HIGH 50%;
NET "clk_125m_dmtd_n_i" TNM_NET = clk_125m_dmtd_n_i;
TIMESPEC TS_dmtd_clk_n_i = PERIOD "clk_125m_dmtd_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" LOC = F6 | IOSTANDARD = "LVDS_25"; #Bank 216 -- 125.000 MHz GTP reference
NET "clk_125m_gtp_n_i" LOC = E6 | IOSTANDARD = "LVDS_25"; #Bank 216
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
#Bank 14 VCCO - 3.3 V -- 20MHz VCXO clock
set_property PACKAGE_PIN F22 [get_ports clk_20m_vcxo_i]
set_property IOSTANDARD LVCMOS33 [get_ports clk_20m_vcxo_i]
#Bank 116 -- 125 MHz GTX reference
set_property PACKAGE_PIN D6 [get_ports clk_125m_gtx_p_i]
set_property PACKAGE_PIN D5 [get_ports clk_125m_gtx_n_i]
create_clock -period 50.000 -name clk_20m_vcxo_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]
create_clock -period 8.000 -name clk_125m_gtx_p_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
#create_clock -period 8.000 -name clk_125m_gtx_n_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
set_clock_groups -asynchronous \
-group {clk_sys } \
-group {clk_dmtd } \
-group {clk_20m_vcxo_i } \
-group {clk_125m_gtx_p_i } \
-group {RXOUTCLK} \
-group {TXOUTCLK} \
-group {clk_ext_mul } \
-group {dio_clk_p_i}
# ---------------------------------------------------------------------------
# -- SPI interface to DACs
# ---------------------------------------------------------------------------
NET "dac_dmtd_din_o" LOC = G21 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_dmtd_sclk_o" LOC = G22 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_dmtd_cs_n_o" LOC = D22 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_refclk_din_o" LOC = E21 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_refclk_sclk_o" LOC = D21 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_refclk_cs_n_o" LOC = B22 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN A13 [get_ports plldac_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports plldac_din_o]
set_property PACKAGE_PIN A12 [get_ports plldac_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports plldac_sclk_o]
set_property PACKAGE_PIN A14 [get_ports pll25dac_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports pll25dac_cs_n_o]
set_property PACKAGE_PIN A15 [get_ports pll20dac_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports pll20dac_cs_n_o]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
NET "sfp_txp_o" LOC = B4; #Bank 216
NET "sfp_txn_o" LOC = A4; #Bank 216
NET "sfp_rxp_i" LOC = B8; #Bank 216
NET "sfp_rxn_i" LOC = A8; #Bank 216
NET "sfp_mod_def0_i" LOC = W17 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sfp detect
NET "sfp_mod_def1_b" LOC = AA18 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- scl
NET "sfp_mod_def2_b" LOC = AB18 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sda
NET "sfp_rate_select_o" LOC = AB20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_fault_i" LOC = R19 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_disable_o" LOC = P19 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_los_i" LOC = V17 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#Bank 116
set_property PACKAGE_PIN A4 [get_ports sfp_txp_o]
set_property PACKAGE_PIN A3 [get_ports sfp_txn_o]
set_property PACKAGE_PIN B6 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN B5 [get_ports sfp_rxn_i]
#Bank 14 VCCO - 3.3 V -- sfp detect
set_property PACKAGE_PIN E26 [get_ports sfp_mod_def0_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def0_i]
#Bank 14 VCCO - 3.3 V -- scl
set_property PACKAGE_PIN J26 [get_ports sfp_mod_def1_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def1_b]
#Bank 14 VCCO - 3.3 V -- sda
set_property PACKAGE_PIN H26 [get_ports sfp_mod_def2_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def2_b]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN G26 [get_ports sfp_rate_select_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_rate_select_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN C26 [get_ports sfp_tx_fault_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_fault_i]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN D26 [get_ports sfp_tx_disable_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_disable_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN F25 [get_ports sfp_los_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_los_i]
# ---------------------------------------------------------------------------
# -- Onewire interface
# ---------------------------------------------------------------------------
NET "onewire_b" LOC = P16 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN L23 [get_ports onewire_b]
set_property IOSTANDARD LVCMOS33 [get_ports onewire_b]
# ---------------------------------------------------------------------------
# -- UART
# ---------------------------------------------------------------------------
#TEST & DEBUG
# Signal USB_TX is an output in the design and must be connected to pin 20/12 (RXD_I) of U26 (CP2105GM)
# Signal USB_RX is an input in the design and must be connected to pin 21/13 (TXD_O) of U26 (CP2105GM)
# Signal USB_TX is an output in the design and must be connected to pin 20/12 (RXD_I) of U34 (CP2105GM)
# Signal USB_RX is an input in the design and must be connected to pin 21/13 (TXD_O) of U34 (CP2105GM)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
NET "uart_rxd_i" LOC = W6 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 34 VCCO - 1.8 V
NET "uart_txd_o" LOC = W5 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 1.8 V
#NET "USB_RX2" LOC = U6 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 34 VCCO - 1.8 V
#NET "USB_TX2" LOC = V5 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 1.8 V
#USB Connection on Test&Debug Connector (J20)
#NET "USBEXT_RX1" LOC = D19 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX1" LOC = E19 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_RX2" LOC = F19 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX2" LOC = F20 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#Bank 15 VCCO - 2.5 V
set_property PACKAGE_PIN D19 [get_ports uart_rxd_i]
set_property IOSTANDARD LVCMOS25 [get_ports uart_rxd_i]
set_property PULLDOWN true [get_ports uart_rxd_i]
set_property PACKAGE_PIN D20 [get_ports uart_txd_o]
set_property IOSTANDARD LVCMOS25 [get_ports uart_txd_o]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN C19 [get_ports USB_RX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_RX2]
#set_property PULLDOWN true [get_ports USB_RX2]
#set_property PACKAGE_PIN B19 [get_ports USB_TX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_TX2]
#USB Connection on Test&Debug Connector (J35)
#Bank 16 VCCO - 3.3 V
#set_property PACKAGE_PIN F14 [get_ports USBEXT_RX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX1]
#set_property PULLDOWN true [get_ports USBEXT_RX1]
#set_property PACKAGE_PIN F13 [get_ports USBEXT_TX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX1]
#set_property PACKAGE_PIN C14 [get_ports USBEXT_RX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX2]
#set_property PULLDOWN true [get_ports USBEXT_RX2]
#set_property PACKAGE_PIN C13 [get_ports USBEXT_TX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX2]
# ---------------------------------------------------------------------------
# -- Flash memory SPI interface
......@@ -80,20 +128,48 @@ NET "uart_txd_o" LOC = W5 | IOSTANDARD = LVCMOS25;
# flash_miso_i : in std_logic;
# ---------------------------------------------------------------------------
# -- Miscellanous CLBv3 pins
# -- Miscellaneous clbv2 pins
# ---------------------------------------------------------------------------
#NET "GPIO_LED[0]" LOC = T20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "led_act_o" LOC = T20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[1]" LOC = W21 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[2]" LOC = W22 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[3]" LOC = Y21 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[4]" LOC = AA21 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[5]" LOC = AA20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "led_link_o" LOC = AA20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "reset_i" LOC = C18 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN C16 [get_ports {GPIO_LED[0]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[0]}]
set_property PACKAGE_PIN C16 [get_ports led_act_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_act_o]
#set_property PACKAGE_PIN B16 [get_ports {GPIO_LED[1]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[1]}]
#set_property PACKAGE_PIN B17 [get_ports {GPIO_LED[2]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[2]}]
#set_property PACKAGE_PIN A17 [get_ports {GPIO_LED[3]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[3]}]
#set_property PACKAGE_PIN A18 [get_ports {GPIO_LED[4]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[4]}]
#set_property PACKAGE_PIN A19 [get_ports {GPIO_LED[5]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[5]}]
set_property PACKAGE_PIN A19 [get_ports led_link_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_link_o]
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN E11 [get_ports reset_i]
set_property IOSTANDARD LVCMOS33 [get_ports reset_i]
#Bank 15 VCCO - 2.5 V
set_property PACKAGE_PIN K15 [get_ports suicide]
set_property IOSTANDARD LVCMOS25 [get_ports suicide]
#Bank 16 VCCO - 3.3 V Enable test-pad TP17, TP18 driver
set_property PACKAGE_PIN B11 [get_ports pll_oe_out_b]
set_property IOSTANDARD LVCMOS33 [get_ports pll_oe_out_b]
#Bank 15 VCCO - 2.5 V Monitoring signals output on test-pads and External Debug Connector J35
set_property PACKAGE_PIN C17 [get_ports pps_p]
set_property IOSTANDARD LVDS_25 [get_ports pps_p]
set_property PACKAGE_PIN C18 [get_ports pps_n]
set_property IOSTANDARD LVDS_25 [get_ports pps_n]
set_property PACKAGE_PIN D15 [get_ports ref_clk_p]
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_p]
set_property PACKAGE_PIN D16 [get_ports ref_clk_n]
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_n]
# ---------------------------------------------------------------------------
# -- Digital I/O FMC Pins
......@@ -103,179 +179,405 @@ NET "reset_i" LOC = C18 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
# -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
# -- external reference input.
NET "dio_clk_p_i" LOC = R4 | IOSTANDARD=LVDS_25; #CLK1_M2C_P
NET "dio_clk_n_i" LOC = T4 | IOSTANDARD=LVDS_25; #CLK1_M2C_N
#CLK1_M2C_P
set_property PACKAGE_PIN Y22 [get_ports dio_clk_p_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_p_i]
#CLK1_M2C_N
set_property PACKAGE_PIN AA22 [get_ports dio_clk_n_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_n_i]
# -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
# -- the mezzanine front panel.
NET "dio_p_i[4]" LOC = J22 | IOSTANDARD=LVDS_25; #LA00_P
NET "dio_n_i[4]" LOC = H22 | IOSTANDARD=LVDS_25; #LA00_N
NET "dio_p_i[3]" LOC = M13 | IOSTANDARD=LVDS_25; #LA03_P
NET "dio_n_i[3]" LOC = L13 | IOSTANDARD=LVDS_25; #LA03_N
NET "dio_p_i[2]" LOC = T16 | IOSTANDARD=LVDS_25; #LA16_P
NET "dio_n_i[2]" LOC = U16 | IOSTANDARD=LVDS_25; #LA16_N
NET "dio_p_i[1]" LOC = AA10 | IOSTANDARD=LVDS_25; #LA20_P
NET "dio_n_i[1]" LOC = AA11 | IOSTANDARD=LVDS_25; #LA20_N
NET "dio_p_i[0]" LOC = R6 | IOSTANDARD=LVDS_25; #LA33_P
NET "dio_n_i[0]" LOC = T6 | IOSTANDARD=LVDS_25; #LA33_N
#LA00_P
set_property PACKAGE_PIN N21 [get_ports {dio_p_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[4]}]
#LA00_N
set_property PACKAGE_PIN N22 [get_ports {dio_n_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[4]}]
#LA03_P
set_property PACKAGE_PIN P16 [get_ports {dio_p_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[3]}]
#LA03_N
set_property PACKAGE_PIN N17 [get_ports {dio_n_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[3]}]
#LA16_P
set_property PACKAGE_PIN AB26 [get_ports {dio_p_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[2]}]
#LA16_N
set_property PACKAGE_PIN AC26 [get_ports {dio_n_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[2]}]
#LA20_P
set_property PACKAGE_PIN K20 [get_ports {dio_p_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[1]}]
#LA20_N
set_property PACKAGE_PIN J20 [get_ports {dio_n_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[1]}]
#LA33_P
set_property PACKAGE_PIN P19 [get_ports {dio_p_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[0]}]
#LA33_N
set_property PACKAGE_PIN P20 [get_ports {dio_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
# -- of I/O (N+1) on the front panel of the mezzanine
NET "dio_p_o[4]" LOC = M18 | IOSTANDARD=LVDS_25; #LA04_P
NET "dio_n_o[4]" LOC = L18 | IOSTANDARD=LVDS_25; #LA04_N
NET "dio_p_o[3]" LOC = N20 | IOSTANDARD=LVDS_25; #LA07_P
NET "dio_n_o[3]" LOC = M20 | IOSTANDARD=LVDS_25; #LA07_N
NET "dio_p_o[2]" LOC = N22 | IOSTANDARD=LVDS_25; #LA08_P
NET "dio_n_o[2]" LOC = M22 | IOSTANDARD=LVDS_25; #LA08_N
NET "dio_p_o[1]" LOC = AA9 | IOSTANDARD=LVDS_25; #LA28_P
NET "dio_n_o[1]" LOC = AB10 | IOSTANDARD=LVDS_25; #LA28_N
NET "dio_p_o[0]" LOC = W11 | IOSTANDARD=LVDS_25; #LA29_P
NET "dio_n_o[0]" LOC = W12 | IOSTANDARD=LVDS_25; #LA29_N
#LA04_P
set_property PACKAGE_PIN N18 [get_ports {dio_p_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[4]}]
#LA04_N
set_property PACKAGE_PIN M19 [get_ports {dio_n_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[4]}]
#LA07_P
set_property PACKAGE_PIN U19 [get_ports {dio_p_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[3]}]
#LA07_N
set_property PACKAGE_PIN U20 [get_ports {dio_n_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[3]}]
#LA08_P
set_property PACKAGE_PIN W20 [get_ports {dio_p_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[2]}]
#LA08_N
set_property PACKAGE_PIN Y21 [get_ports {dio_n_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[2]}]
#LA28_P
set_property PACKAGE_PIN M21 [get_ports {dio_p_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[1]}]
#LA28_N
set_property PACKAGE_PIN M22 [get_ports {dio_n_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[1]}]
#LA29_P
set_property PACKAGE_PIN N19 [get_ports {dio_p_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[0]}]
#LA29_N
set_property PACKAGE_PIN M20 [get_ports {dio_n_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[0]}]
# -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
# -- panel is configured as an output.
NET "dio_oe_n_o[4]" LOC = V10 | IOSTANDARD=LVCMOS25; #LA05_P
NET "dio_oe_n_o[3]" LOC = M15 | IOSTANDARD=LVCMOS25; #LA11_P
NET "dio_oe_n_o[2]" LOC = W16 | IOSTANDARD=LVCMOS25; #LA15_N
NET "dio_oe_n_o[1]" LOC = AB13 | IOSTANDARD=LVCMOS25; #LA24_N
NET "dio_oe_n_o[0]" LOC = G17 | IOSTANDARD=LVCMOS25; #LA30_P
#LA05_P
set_property PACKAGE_PIN AE22 [get_ports {dio_oe_n_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[4]}]
#LA11_P
set_property PACKAGE_PIN U26 [get_ports {dio_oe_n_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[3]}]
#LA15_N
set_property PACKAGE_PIN AB25 [get_ports {dio_oe_n_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[2]}]
#LA24_N
set_property PACKAGE_PIN N23 [get_ports {dio_oe_n_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[1]}]
#LA30_P
set_property PACKAGE_PIN P24 [get_ports {dio_oe_n_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[0]}]
# -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
# -- panel is 50-ohm terminated
NET "dio_term_en_o[4]" LOC = V14 | IOSTANDARD=LVCMOS25; #LA09_N
NET "dio_term_en_o[3]" LOC = V13 | IOSTANDARD=LVCMOS25; #LA09_P
NET "dio_term_en_o[2]" LOC = W10 | IOSTANDARD=LVCMOS25; #LA05_N
NET "dio_term_en_o[1]" LOC = Y12 | IOSTANDARD=LVCMOS25; #LA06_N
NET "dio_term_en_o[0]" LOC = G18 | IOSTANDARD=LVCMOS25; #LA30_N
#LA09_N
set_property PACKAGE_PIN P25 [get_ports {dio_term_en_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[4]}]
#LA09_P
set_property PACKAGE_PIN R25 [get_ports {dio_term_en_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[3]}]
#LA05_N
set_property PACKAGE_PIN AF22 [get_ports {dio_term_en_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[2]}]
#LA06_N
set_property PACKAGE_PIN AF25 [get_ports {dio_term_en_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[1]}]
#LA30_N
set_property PACKAGE_PIN N24 [get_ports {dio_term_en_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[0]}]
# -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
# -- blink 1-PPS.
NET "dio_led_top_o" LOC = AB11 | IOSTANDARD=LVCMOS25; #LA01_P
NET "dio_led_bot_o" LOC = AB12 | IOSTANDARD=LVCMOS25; #LA01_N
#LA01_P
set_property PACKAGE_PIN R21 [get_ports dio_led_top_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_top_o]
#LA01_N
set_property PACKAGE_PIN P21 [get_ports dio_led_bot_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
# -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
# -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
NET "dio_scl_b" LOC = P17 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "dio_sda_b" LOC = N17 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
# ---------------------------------------------------------------------------
# -- Bulls-eye connector outputs
# ---------------------------------------------------------------------------
NET "txts_p_o" LOC = H13 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 1
NET "txts_n_o" LOC = G13 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 2
NET "rxts_p_o" LOC = G15 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 3
NET "rxts_n_o" LOC = G16 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 4
NET "pps_p_o" LOC = J15 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 5
NET "pps_n_o" LOC = H15 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 6
NET "clk_ref_62m5_p_o" LOC = H17 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 7
NET "clk_ref_62m5_n_o" LOC = H18 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 8
NET "clk_dmtd_62m5_p_o" LOC = K21 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 12
NET "clk_dmtd_62m5_n_o" LOC = K22 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 13
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN D24 [get_ports dio_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_scl_b]
set_property PACKAGE_PIN D23 [get_ports dio_sda_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_sda_b]
# ---------------------------------------------------------------------------
# -- GPIO connector
# ---------------------------------------------------------------------------
#NET "GPIO[1]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[2]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[3]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[4]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[5]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[6]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[7]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[8]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[9]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[10]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[11]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[12]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[13]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[14]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[15]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[16]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#Bank 16 VCCO - 3.3 V
#set_property PACKAGE_PIN H8 [get_ports {GPIO[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[1]}]
#set_property PACKAGE_PIN J8 [get_ports {GPIO[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[2]}]
#set_property PACKAGE_PIN G9 [get_ports {GPIO[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[3]}]
#set_property PACKAGE_PIN H9 [get_ports {GPIO[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[4]}]
#set_property PACKAGE_PIN F8 [get_ports {GPIO[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[5]}]
#set_property PACKAGE_PIN G10 [get_ports {GPIO[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[6]}]
#set_property PACKAGE_PIN F9 [get_ports {GPIO[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[7]}]
#set_property PACKAGE_PIN F10 [get_ports {GPIO[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[8]}]
#set_property PACKAGE_PIN D9 [get_ports {GPIO[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[9]}]
#set_property PACKAGE_PIN D8 [get_ports {GPIO[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[10]}]
#set_property PACKAGE_PIN B9 [get_ports {GPIO[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[11]}]
#set_property PACKAGE_PIN C9 [get_ports {GPIO[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[12]}]
#set_property PACKAGE_PIN A9 [get_ports {GPIO[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[13]}]
#set_property PACKAGE_PIN A8 [get_ports {GPIO[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[14]}]
#set_property PACKAGE_PIN A10 [get_ports {GPIO[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[15]}]
#set_property PACKAGE_PIN B10 [get_ports {GPIO[16]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[16]}]
#FMC SIGNALS CLK LPC
#NET "FMC_CLK0_M2C_P" LOC = T5 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 2.5 V
#NET "FMC_CLK0_M2C_N" LOC = U5 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_P" LOC = R4 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_N" LOC = T4 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA00_CC_P" LOC = J22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 1
#NET "FMC_LA00_CC_N" LOC = H22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 3
#NET "FMC_LA01_CC_P" LOC = AB11 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 5
#NET "FMC_LA01_CC_N" LOC = AB12 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 7
#NET "FMC_LA17_CC_P" LOC = J20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 30
#NET "FMC_LA17_CC_N" LOC = J21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 32 *
#NET "FMC_LA18_CC_P" LOC = L19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 34 *
#NET "FMC_LA18_CC_N" LOC = L20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 36 *
#Bank 12 VCCO - 2.5 V
#set_property PACKAGE_PIN Y23 [get_ports FMC_CLK0_M2C_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK0_M2C_P]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK0_M2C_P]
#set_property PACKAGE_PIN AA24 [get_ports FMC_CLK0_M2C_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK0_M2C_N]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK0_M2C_N]
#set_property PACKAGE_PIN Y22 [get_ports FMC_CLK1_M2C_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK1_M2C_P]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK1_M2C_P]
#set_property PACKAGE_PIN AA22 [get_ports FMC_CLK1_M2C_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK1_M2C_N]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK1_M2C_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 1
#set_property PACKAGE_PIN N21 [get_ports FMC_LA00_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA00_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA00_CC_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 3
#set_property PACKAGE_PIN N22 [get_ports FMC_LA00_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA00_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA00_CC_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 5
#set_property PACKAGE_PIN R21 [get_ports FMC_LA01_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA01_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA01_CC_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 7
#set_property PACKAGE_PIN P21 [get_ports FMC_LA01_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA01_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA01_CC_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 30
#set_property PACKAGE_PIN R22 [get_ports FMC_LA17_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA17_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA17_CC_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 32 *
#set_property PACKAGE_PIN R23 [get_ports FMC_LA17_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA17_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA17_CC_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 34 *
#set_property PACKAGE_PIN AA23 [get_ports FMC_LA18_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA18_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA18_CC_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 36 *
#set_property PACKAGE_PIN AB24 [get_ports FMC_LA18_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA18_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA18_CC_N]
########################################################
#FMC SIGNALS LPC
#NET "FMC_PRSNT_B" LOC = W20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "FMC_LA02_P" LOC = K17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 9 *
#NET "FMC_LA02_N" LOC = J17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 11 *
#NET "FMC_LA03_P" LOC = M13 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 13
#NET "FMC_LA03_N" LOC = L13 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 15
#NET "FMC_LA04_P" LOC = M18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 17
#NET "FMC_LA04_N" LOC = L18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 19
#NET "FMC_LA05_P" LOC = V10 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 21
#NET "FMC_LA05_N" LOC = W10 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 23
#NET "FMC_LA06_P" LOC = Y11 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 25 *
#NET "FMC_LA06_N" LOC = Y12 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 27
#NET "FMC_LA07_P" LOC = N20 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 29
#NET "FMC_LA07_N" LOC = M20 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 31
#NET "FMC_LA08_P" LOC = N22 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 33
#NET "FMC_LA08_N" LOC = M22 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 35
#NET "FMC_LA09_P" LOC = V13 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
#NET "FMC_LA09_N" LOC = V14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
#NET "FMC_LA10_P" LOC = W14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 2 *
#NET "FMC_LA10_N" LOC = Y14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 4 *
#NET "FMC_LA11_P" LOC = M15 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 6
#NET "FMC_LA11_N" LOC = M16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 8 *
#NET "FMC_LA12_P" LOC = N18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 10 *
#NET "FMC_LA12_N" LOC = N19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 12 *
#NET "FMC_LA13_P" LOC = U15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 14 *
#NET "FMC_LA13_N" LOC = V15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 16 *
#NET "FMC_LA14_P" LOC = T14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 18 *
#NET "FMC_LA14_N" LOC = T15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 20 *
#NET "FMC_LA15_P" LOC = W15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 22 *
#NET "FMC_LA15_N" LOC = W16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 24
#NET "FMC_LA16_P" LOC = T16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 26
#NET "FMC_LA16_N" LOC = U16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 28
#NET "FMC_LA19_P" LOC = Y16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 38 *
#NET "FMC_LA19_N" LOC = AA16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 40 *
#NET "FMC_LA20_P" LOC = AA10 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA20_N" LOC = AA11 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA21_P" LOC = Y13 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA21_N" LOC = AA14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA22_P" LOC = AB16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA22_N" LOC = AB17 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA23_P" LOC = K13 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA23_N" LOC = K14 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA24_P" LOC = AA13 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA24_N" LOC = AB13 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_P" LOC = AA15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_N" LOC = AB15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA26_P" LOC = L14 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA26_N" LOC = L15 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA27_P" LOC = L16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA27_N" LOC = K16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA28_P" LOC = AA9 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA28_N" LOC = AB10 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_P" LOC = W11 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_N" LOC = W12 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA30_P" LOC = G17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA30_N" LOC = G18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA31_P" LOC = R3 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA31_N" LOC = R2 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA32_P" LOC = W2 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA32_N" LOC = Y2 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA33_P" LOC = R6 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA33_N" LOC = T6 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#Bank 14 VCCO - 3.3 V
#set_property PACKAGE_PIN K21 [get_ports FMC_PRSNT_B]
#set_property IOSTANDARD LVCMOS33 [get_ports FMC_PRSNT_B]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 9 *
#set_property PACKAGE_PIN H19 [get_ports FMC_LA02_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA02_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 11 *
#set_property PACKAGE_PIN G20 [get_ports FMC_LA02_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA02_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 13
#set_property PACKAGE_PIN P16 [get_ports FMC_LA03_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA03_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 15
#set_property PACKAGE_PIN N17 [get_ports FMC_LA03_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA03_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 17
#set_property PACKAGE_PIN N18 [get_ports FMC_LA04_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA04_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 19
#set_property PACKAGE_PIN M19 [get_ports FMC_LA04_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA04_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 21
#set_property PACKAGE_PIN AE22 [get_ports FMC_LA05_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA05_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 23
#set_property PACKAGE_PIN AF22 [get_ports FMC_LA05_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA05_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 25 *
#set_property PACKAGE_PIN AF24 [get_ports FMC_LA06_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA06_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 27
#set_property PACKAGE_PIN AF25 [get_ports FMC_LA06_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA06_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 29
#set_property PACKAGE_PIN U19 [get_ports FMC_LA07_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA07_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 31
#set_property PACKAGE_PIN U20 [get_ports FMC_LA07_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA07_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 33
#set_property PACKAGE_PIN W20 [get_ports FMC_LA08_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA08_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 35
#set_property PACKAGE_PIN Y21 [get_ports FMC_LA08_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA08_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
#set_property PACKAGE_PIN R25 [get_ports FMC_LA09_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA09_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
#set_property PACKAGE_PIN P25 [get_ports FMC_LA09_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA09_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 2 *
#set_property PACKAGE_PIN U24 [get_ports FMC_LA10_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA10_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 4 *
#set_property PACKAGE_PIN U25 [get_ports FMC_LA10_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA10_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 6
#set_property PACKAGE_PIN U26 [get_ports FMC_LA11_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA11_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 8 *
#set_property PACKAGE_PIN V26 [get_ports FMC_LA11_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA11_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 10 *
#set_property PACKAGE_PIN R26 [get_ports FMC_LA12_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA12_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 12 *
#set_property PACKAGE_PIN P26 [get_ports FMC_LA12_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA12_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 14 *
#set_property PACKAGE_PIN AE23 [get_ports FMC_LA13_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA13_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 16 *
#set_property PACKAGE_PIN AF23 [get_ports FMC_LA13_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA13_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 18 *
#set_property PACKAGE_PIN AD23 [get_ports FMC_LA14_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA14_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 20 *
#set_property PACKAGE_PIN AD24 [get_ports FMC_LA14_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA14_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 22 *
#set_property PACKAGE_PIN AA25 [get_ports FMC_LA15_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA15_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 24
#set_property PACKAGE_PIN AB25 [get_ports FMC_LA15_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA15_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 26
#set_property PACKAGE_PIN AB26 [get_ports FMC_LA16_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA16_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 28
#set_property PACKAGE_PIN AC26 [get_ports FMC_LA16_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA16_N]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 38 *
#set_property PACKAGE_PIN W23 [get_ports FMC_LA19_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA19_P]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 40 *
#set_property PACKAGE_PIN W24 [get_ports FMC_LA19_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA19_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN K20 [get_ports FMC_LA20_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA20_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN J20 [get_ports FMC_LA20_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA20_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN M25 [get_ports FMC_LA21_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA21_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN L25 [get_ports FMC_LA21_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA21_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN L19 [get_ports FMC_LA22_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA22_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN L20 [get_ports FMC_LA22_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA22_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN K25 [get_ports FMC_LA23_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA23_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN K26 [get_ports FMC_LA23_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA23_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN P23 [get_ports FMC_LA24_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA24_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN N23 [get_ports FMC_LA24_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA24_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN N26 [get_ports FMC_LA25_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA25_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN M26 [get_ports FMC_LA25_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA25_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN T22 [get_ports FMC_LA26_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA26_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN T23 [get_ports FMC_LA26_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA26_N]
#Bank 12 VCCO - 2.5 V
#set_property PACKAGE_PIN V23 [get_ports FMC_LA27_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA27_P]
#Bank 12 VCCO - 2.5 V
#set_property PACKAGE_PIN V24 [get_ports FMC_LA27_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA27_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN M21 [get_ports FMC_LA28_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA28_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN M22 [get_ports FMC_LA28_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA28_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN N19 [get_ports FMC_LA29_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA29_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN M20 [get_ports FMC_LA29_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA29_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN P24 [get_ports FMC_LA30_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA30_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN N24 [get_ports FMC_LA30_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA30_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN M24 [get_ports FMC_LA31_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA31_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN L24 [get_ports FMC_LA31_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA31_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN T20 [get_ports FMC_LA32_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA32_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN R20 [get_ports FMC_LA32_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA32_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN P19 [get_ports FMC_LA33_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA33_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN P20 [get_ports FMC_LA33_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA33_N]
#OCTOPUS SMALL
#NET "IIC1_SDA" LOC = | IOSTANDARD = LVCMOS33; #Bank ?? VCCO - ?.? V
......
......@@ -2,14 +2,13 @@ fetchto = "../../ip_cores"
files = [
"clbv3_wr_ref_top.vhd",
"clbv3_wr_ref_top.ucf",
"clbv3_wr_ref_top.xdc",
"clbv3_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
"../../board/clbv3",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
......
......@@ -29,39 +29,39 @@
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
BUS_BLOCK
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
......@@ -8,7 +8,7 @@
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Last update: 2019-06-28
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the clbv3.
......@@ -54,14 +54,16 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv3_pkg.all;
--use work.gn4124_core_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clbv3_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy16.bram";
g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16_direct_dmtd.bram";
-- In Vivado Project-Mode, during a Synthesis run or an Implementation run, the Vivado working
-- directory temporarily changes to the "project_name/project_name.runs/run_name" directory.
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
......@@ -134,7 +136,15 @@ entity clbv3_wr_ref_top is
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
-- Reset control
reset_i : in std_logic;
suicide : out std_logic;
-- test_lemo outputs PPS
test_lemo : out std_logic;
-- Monitoring signals output on External Debug Connector J35
pps_mon : out std_logic;
ref_clk_mon : out std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC Pins
......@@ -197,35 +207,6 @@ end entity clbv3_wr_ref_top;
architecture top of clbv3_wr_ref_top is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 2;
-- Number of slaves on the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_PCIE : integer := 0;
constant c_WB_MASTER_ETHBONE : integer := 1;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_WRC : integer := 0;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00040000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"));
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
......@@ -277,12 +258,13 @@ architecture top of clbv3_wr_ref_top is
begin -- architecture top
suicide<= '1';
reset_n <= not reset_i; -- Reset = high active on CLB
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
reset_n <= not reset_i; -- Reset = high active on CLB
cmp_xwrc_board_clbv3 : xwrc_board_clbv3
generic map (
g_simulation => g_simulation,
......@@ -371,13 +353,13 @@ begin -- architecture top
O => dio_p_o(i),
OB => dio_n_o(i));
end generate;
-- Configure Digital I/Os 0 to 3 as outputs
-- Configure Digital I/Os 0 to 2 as outputs
dio_oe_n_o(2 downto 0) <= (others => '0');
-- Configure Digital I/Os 3 and 4 as inputs for external reference
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
-- All DIO connectors are not terminated
dio_term_en_o <= (others => '0');
-- Configure Digital I/Os 3 to 4 inputs to be terminated.
dio_term_en_o <= "11000";
-- EEPROM I2C tri-states
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
......@@ -406,6 +388,10 @@ begin -- architecture top
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
test_lemo <= wrc_pps_out;
pps_mon <= wrc_pps_out;
ref_clk_mon <= clk_ref_62m5;
-- LEDs
U_Extend_PPS : gc_extend_pulse
generic map (
......
# ---------------------------------------------------------------------------`
# -- Clocks/resets
# ---------------------------------------------------------------------------
# -- Local oscillators
#Bank 15 VCCO - 2.5 V -- CVPD-922-124.992 MHz PLL reference
set_property PACKAGE_PIN J19 [get_ports clk_125m_dmtd_p_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_p_i]
set_property PACKAGE_PIN H19 [get_ports clk_125m_dmtd_n_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_n_i]
#Bank 15 VCCO - 2.5 V -- FRETHE025 5x25 MHz PLL reference
#set_property PACKAGE_PIN K18 [get_ports clk_125m_dmtd_p_i]
#set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_p_i]
#set_property PACKAGE_PIN K19 [get_ports clk_125m_dmtd_n_i]
#set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_n_i]
create_clock -period 8.000 -name clk_125m_dmtd_p_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i]
#create_clock -period 8.000 -name clk_125m_dmtd_n_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_n_i] # AR57109: "Only P side needs constraint"
create_generated_clock -name clk_dmtd -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_clbv3/cmp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.clk_dmtd_reg/Q]
#Bank 216 -- 125.000 MHz GTP reference
set_property PACKAGE_PIN F6 [get_ports clk_125m_gtp_p_i]
set_property PACKAGE_PIN E6 [get_ports clk_125m_gtp_n_i]
create_clock -period 8.000 -name clk_125m_gtp_p_i -waveform {0.000 4.000} [get_ports clk_125m_gtp_p_i]
#create_clock -period 8.000 -name clk_125m_gtp_n_i -waveform {0.000 4.000} [get_ports clk_125m_gtp_n_i] # AR57109: "Only P side needs constraint"
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv3/cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/GT_INST/gtpe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv3/cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/GT_INST/gtpe2_i/TXOUTCLK]
create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
set_clock_groups -asynchronous \
-group {clk_sys } \
-group {clk_dmtd } \
-group {clk_125m_dmtd_p_i } \
-group {clk_125m_gtp_p_i } \
-group {RXOUTCLK} \
-group {TXOUTCLK} \
-group {clk_ext_mul } \
-group {dio_clk_p_i}
# ---------------------------------------------------------------------------
# -- SPI interface to DACs
# ---------------------------------------------------------------------------
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN G21 [get_ports dac_dmtd_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_din_o]
set_property PACKAGE_PIN G22 [get_ports dac_dmtd_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_sclk_o]
set_property PACKAGE_PIN D22 [get_ports dac_dmtd_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_cs_n_o]
set_property PACKAGE_PIN E21 [get_ports dac_refclk_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_din_o]
set_property PACKAGE_PIN D21 [get_ports dac_refclk_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_sclk_o]
set_property PACKAGE_PIN B22 [get_ports dac_refclk_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_cs_n_o]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
#Bank 216
set_property PACKAGE_PIN B4 [get_ports sfp_txp_o]
set_property PACKAGE_PIN A4 [get_ports sfp_txn_o]
set_property PACKAGE_PIN B8 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN A8 [get_ports sfp_rxn_i]
#Bank 14 VCCO - 3.3 V -- sfp detect
set_property PACKAGE_PIN W17 [get_ports sfp_mod_def0_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def0_i]
#Bank 14 VCCO - 3.3 V -- scl
set_property PACKAGE_PIN AA18 [get_ports sfp_mod_def1_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def1_b]
#Bank 14 VCCO - 3.3 V -- sda
set_property PACKAGE_PIN AB18 [get_ports sfp_mod_def2_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def2_b]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN AB20 [get_ports sfp_rate_select_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_rate_select_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN R19 [get_ports sfp_tx_fault_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_fault_i]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN P19 [get_ports sfp_tx_disable_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_disable_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN V17 [get_ports sfp_los_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_los_i]
# ---------------------------------------------------------------------------
# -- Onewire interface
# ---------------------------------------------------------------------------
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN P16 [get_ports onewire_b]
set_property IOSTANDARD LVCMOS33 [get_ports onewire_b]
# ---------------------------------------------------------------------------
# -- UART
# ---------------------------------------------------------------------------
#TEST & DEBUG
# Signal USB_TX is an output in the design and must be connected to pin 20/12 (RXD_I) of U26 (CP2105GM)
# Signal USB_RX is an input in the design and must be connected to pin 21/13 (TXD_O) of U26 (CP2105GM)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
#Bank 34 VCCO - 1.8 V
set_property PACKAGE_PIN W6 [get_ports uart_rxd_i]
set_property IOSTANDARD LVCMOS25 [get_ports uart_rxd_i]
set_property PULLDOWN true [get_ports uart_rxd_i]
set_property PACKAGE_PIN W5 [get_ports uart_txd_o]
set_property IOSTANDARD LVCMOS25 [get_ports uart_txd_o]
#Bank 34 VCCO - 1.8 V
#set_property PACKAGE_PIN U6 [get_ports USB_RX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_RX2]
#set_property PULLDOWN true [get_ports USB_RX2]
#set_property PACKAGE_PIN V5 [get_ports USB_TX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_TX2]
#USB Connection on Test&Debug Connector (J20)
#Bank 16 VCCO - 3.3 V
#set_property PACKAGE_PIN D19 [get_ports USBEXT_RX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX1]
#set_property PULLDOWN true [get_ports USBEXT_RX1]
#set_property PACKAGE_PIN E19 [get_ports USBEXT_TX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX1]
#set_property PACKAGE_PIN F19 [get_ports USBEXT_RX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX2]
#set_property PULLDOWN true [get_ports USBEXT_RX2]
#set_property PACKAGE_PIN F20 [get_ports USBEXT_TX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX2]
# ---------------------------------------------------------------------------
# -- Flash memory SPI interface
# ---------------------------------------------------------------------------
# flash_sclk_o : out std_logic;
# flash_ncs_o : out std_logic;
# flash_mosi_o : out std_logic;
# flash_miso_i : in std_logic;
# ---------------------------------------------------------------------------
# -- Miscellanous CLBv3 pins
# ---------------------------------------------------------------------------
#Bank 14 VCCO - 3.3 V
#set_property PACKAGE_PIN T20 [get_ports {GPIO_LED[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[0]}]
set_property PACKAGE_PIN T20 [get_ports led_act_o]
set_property IOSTANDARD LVCMOS33 [get_ports led_act_o]
#set_property PACKAGE_PIN W21 [get_ports {GPIO_LED[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[1]}]
#set_property PACKAGE_PIN W22 [get_ports {GPIO_LED[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[2]}]
#set_property PACKAGE_PIN Y21 [get_ports {GPIO_LED[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[3]}]
#set_property PACKAGE_PIN AA21 [get_ports {GPIO_LED[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[4]}]
#set_property PACKAGE_PIN AA20 [get_ports {GPIO_LED[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[5]}]
set_property PACKAGE_PIN AA20 [get_ports led_link_o]
set_property IOSTANDARD LVCMOS33 [get_ports led_link_o]
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN C18 [get_ports reset_i]
set_property IOSTANDARD LVCMOS33 [get_ports reset_i]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN AB21 [get_ports suicide]
set_property IOSTANDARD LVCMOS33 [get_ports suicide]
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN B20 [get_ports test_lemo]
set_property IOSTANDARD LVCMOS33 [get_ports test_lemo]
#Bank 16 VCCO - 3.3 V Monitoring signals output on External Debug Connector J35
set_property PACKAGE_PIN F18 [get_ports pps_mon]
set_property IOSTANDARD LVCMOS33 [get_ports pps_mon]
set_property PACKAGE_PIN E18 [get_ports ref_clk_mon]
set_property IOSTANDARD LVCMOS33 [get_ports ref_clk_mon]
# ---------------------------------------------------------------------------
# -- Digital I/O FMC Pins
# -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
# -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
# ---------------------------------------------------------------------------
# -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
# -- external reference input.
#CLK1_M2C_P
set_property PACKAGE_PIN R4 [get_ports dio_clk_p_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_p_i]
#CLK1_M2C_N
set_property PACKAGE_PIN T4 [get_ports dio_clk_n_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_n_i]
# -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
# -- the mezzanine front panel.
#LA00_P
set_property PACKAGE_PIN J22 [get_ports {dio_p_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[4]}]
#LA00_N
set_property PACKAGE_PIN H22 [get_ports {dio_n_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[4]}]
#LA03_P
set_property PACKAGE_PIN M13 [get_ports {dio_p_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[3]}]
#LA03_N
set_property PACKAGE_PIN L13 [get_ports {dio_n_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[3]}]
#LA16_P
set_property PACKAGE_PIN T16 [get_ports {dio_p_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[2]}]
#LA16_N
set_property PACKAGE_PIN U16 [get_ports {dio_n_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[2]}]
#LA20_P
set_property PACKAGE_PIN AA10 [get_ports {dio_p_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[1]}]
#LA20_N
set_property PACKAGE_PIN AA11 [get_ports {dio_n_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[1]}]
#LA33_P
set_property PACKAGE_PIN R6 [get_ports {dio_p_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[0]}]
#LA33_N
set_property PACKAGE_PIN T6 [get_ports {dio_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
# -- of I/O (N+1) on the front panel of the mezzanine
#LA04_P
set_property PACKAGE_PIN M18 [get_ports {dio_p_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[4]}]
#LA04_N
set_property PACKAGE_PIN L18 [get_ports {dio_n_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[4]}]
#LA07_P
set_property PACKAGE_PIN N20 [get_ports {dio_p_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[3]}]
#LA07_N
set_property PACKAGE_PIN M20 [get_ports {dio_n_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[3]}]
#LA08_P
set_property PACKAGE_PIN N22 [get_ports {dio_p_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[2]}]
#LA08_N
set_property PACKAGE_PIN M22 [get_ports {dio_n_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[2]}]
#LA28_P
set_property PACKAGE_PIN AA9 [get_ports {dio_p_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[1]}]
#LA28_N
set_property PACKAGE_PIN AB10 [get_ports {dio_n_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[1]}]
#LA29_P
set_property PACKAGE_PIN W11 [get_ports {dio_p_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[0]}]
#LA29_N
set_property PACKAGE_PIN W12 [get_ports {dio_n_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[0]}]
# -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
# -- panel is configured as an output.
#LA05_P
set_property PACKAGE_PIN V10 [get_ports {dio_oe_n_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[4]}]
#LA11_P
set_property PACKAGE_PIN M15 [get_ports {dio_oe_n_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[3]}]
#LA15_N
set_property PACKAGE_PIN W16 [get_ports {dio_oe_n_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[2]}]
#LA24_N
set_property PACKAGE_PIN AB13 [get_ports {dio_oe_n_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[1]}]
#LA30_P
set_property PACKAGE_PIN G17 [get_ports {dio_oe_n_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[0]}]
# -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
# -- panel is 50-ohm terminated
#LA09_N
set_property PACKAGE_PIN V14 [get_ports {dio_term_en_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[4]}]
#LA09_P
set_property PACKAGE_PIN V13 [get_ports {dio_term_en_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[3]}]
#LA05_N
set_property PACKAGE_PIN W10 [get_ports {dio_term_en_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[2]}]
#LA06_N
set_property PACKAGE_PIN Y12 [get_ports {dio_term_en_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[1]}]
#LA30_N
set_property PACKAGE_PIN G18 [get_ports {dio_term_en_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[0]}]
# -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
# -- blink 1-PPS.
#LA01_P
set_property PACKAGE_PIN AB11 [get_ports dio_led_top_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_top_o]
#LA01_N
set_property PACKAGE_PIN AB12 [get_ports dio_led_bot_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
# -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
# -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN P17 [get_ports dio_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_scl_b]
set_property PACKAGE_PIN N17 [get_ports dio_sda_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_sda_b]
# ---------------------------------------------------------------------------
# -- Bulls-eye connector outputs
# ---------------------------------------------------------------------------
#Bank 15 VCCO - 2.5 V -- BullsEye 1
set_property PACKAGE_PIN H13 [get_ports txts_p_o]
set_property IOSTANDARD LVDS_25 [get_ports txts_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 2
set_property PACKAGE_PIN G13 [get_ports txts_n_o]
set_property IOSTANDARD LVDS_25 [get_ports txts_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 3
set_property PACKAGE_PIN G15 [get_ports rxts_p_o]
set_property IOSTANDARD LVDS_25 [get_ports rxts_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 4
set_property PACKAGE_PIN G16 [get_ports rxts_n_o]
set_property IOSTANDARD LVDS_25 [get_ports rxts_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 5
set_property PACKAGE_PIN J15 [get_ports pps_p_o]
set_property IOSTANDARD LVDS_25 [get_ports pps_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 6
set_property PACKAGE_PIN H15 [get_ports pps_n_o]
set_property IOSTANDARD LVDS_25 [get_ports pps_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 7
set_property PACKAGE_PIN H17 [get_ports clk_ref_62m5_p_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_ref_62m5_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 8
set_property PACKAGE_PIN H18 [get_ports clk_ref_62m5_n_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_ref_62m5_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 12
set_property PACKAGE_PIN K21 [get_ports clk_dmtd_62m5_p_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_dmtd_62m5_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 13
set_property PACKAGE_PIN K22 [get_ports clk_dmtd_62m5_n_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_dmtd_62m5_n_o]
# ---------------------------------------------------------------------------
# -- GPIO connector
# ---------------------------------------------------------------------------
#Bank ?? VCCO - ?.? V
#set_property PACKAGE_PIN ?? [get_ports {GPIO[1]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[1]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[2]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[2]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[3]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[3]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[4]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[4]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[5]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[5]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[6]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[6]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[7]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[7]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[8]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[8]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[9]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[9]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[10]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[10]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[11]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[11]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[12]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[12]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[13]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[13]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[14]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[14]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[15]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[15]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[16]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[16]}]
#FMC SIGNALS CLK LPC
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN T5 [get_ports FMC_CLK0_M2C_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK0_M2C_P]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK0_M2C_P]
#set_property PACKAGE_PIN T5 [get_ports FMC_CLK0_M2C_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK0_M2C_N]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK0_M2C_N]
#set_property PACKAGE_PIN T5 [get_ports FMC_CLK1_M2C_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK1_M2C_P]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK1_M2C_P]
#set_property PACKAGE_PIN T5 [get_ports FMC_CLK1_M2C_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK1_M2C_N]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK1_M2C_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 1
#set_property PACKAGE_PIN J22 [get_ports FMC_LA00_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA00_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA00_CC_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 3
#set_property PACKAGE_PIN H22 [get_ports FMC_LA00_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA00_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA00_CC_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 5
#set_property PACKAGE_PIN AB11 [get_ports FMC_LA01_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA01_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA01_CC_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 7
#set_property PACKAGE_PIN AB12 [get_ports FMC_LA01_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA01_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA01_CC_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 30
#set_property PACKAGE_PIN J20 [get_ports FMC_LA17_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA17_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA17_CC_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 32 *
#set_property PACKAGE_PIN J21 [get_ports FMC_LA17_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA17_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA17_CC_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 34 *
#set_property PACKAGE_PIN L19 [get_ports FMC_LA18_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA18_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA18_CC_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 36 *
#set_property PACKAGE_PIN L20 [get_ports FMC_LA18_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA18_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA18_CC_N]
########################################################
#FMC SIGNALS LPC
#Bank 14 VCCO - 3.3 V
#set_property PACKAGE_PIN W20 [get_ports FMC_PRSNT_B]
#set_property IOSTANDARD LVCMOS33 [get_ports FMC_PRSNT_B]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 9 *
#set_property PACKAGE_PIN K17 [get_ports FMC_LA02_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA02_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 11 *
#set_property PACKAGE_PIN J17 [get_ports FMC_LA02_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA02_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 13
#set_property PACKAGE_PIN M13 [get_ports FMC_LA03_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA03_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 15
#set_property PACKAGE_PIN L13 [get_ports FMC_LA03_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA03_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 17
#set_property PACKAGE_PIN M18 [get_ports FMC_LA04_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA04_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 19
#set_property PACKAGE_PIN L18 [get_ports FMC_LA04_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA04_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 21
#set_property PACKAGE_PIN V10 [get_ports FMC_LA05_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA05_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 23
#set_property PACKAGE_PIN W10 [get_ports FMC_LA05_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA05_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 25 *
#set_property PACKAGE_PIN Y11 [get_ports FMC_LA06_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA06_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 27
#set_property PACKAGE_PIN Y12 [get_ports FMC_LA06_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA06_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 29
#set_property PACKAGE_PIN N20 [get_ports FMC_LA07_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA07_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 31
#set_property PACKAGE_PIN M20 [get_ports FMC_LA07_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA07_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 33
#set_property PACKAGE_PIN N22 [get_ports FMC_LA08_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA08_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 35
#set_property PACKAGE_PIN M22 [get_ports FMC_LA08_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA08_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
#set_property PACKAGE_PIN V13 [get_ports FMC_LA09_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA09_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
#set_property PACKAGE_PIN V14 [get_ports FMC_LA09_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA09_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 2 *
#set_property PACKAGE_PIN W14 [get_ports FMC_LA10_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA10_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 4 *
#set_property PACKAGE_PIN Y14 [get_ports FMC_LA10_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA10_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 6
#set_property PACKAGE_PIN M15 [get_ports FMC_LA11_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA11_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 8 *
#set_property PACKAGE_PIN M16 [get_ports FMC_LA11_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA11_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 10 *
#set_property PACKAGE_PIN N18 [get_ports FMC_LA12_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA12_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 12 *
#set_property PACKAGE_PIN N19 [get_ports FMC_LA12_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA12_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 14 *
#set_property PACKAGE_PIN U15 [get_ports FMC_LA13_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA13_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 16 *
#set_property PACKAGE_PIN V15 [get_ports FMC_LA13_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA13_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 18 *
#set_property PACKAGE_PIN T14 [get_ports FMC_LA14_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA14_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 20 *
#set_property PACKAGE_PIN T15 [get_ports FMC_LA14_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA14_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 22 *
#set_property PACKAGE_PIN W15 [get_ports FMC_LA15_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA15_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 24
#set_property PACKAGE_PIN W16 [get_ports FMC_LA15_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA15_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 26
#set_property PACKAGE_PIN T16 [get_ports FMC_LA16_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA16_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 28
#set_property PACKAGE_PIN U16 [get_ports FMC_LA16_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA16_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 38 *
#set_property PACKAGE_PIN Y16 [get_ports FMC_LA19_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA19_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 40 *
#set_property PACKAGE_PIN AA16 [get_ports FMC_LA19_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA19_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA10 [get_ports FMC_LA20_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA20_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA11 [get_ports FMC_LA20_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA20_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN Y13 [get_ports FMC_LA21_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA21_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA14 [get_ports FMC_LA21_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA21_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB16 [get_ports FMC_LA22_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA22_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB17 [get_ports FMC_LA22_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA22_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN K13 [get_ports FMC_LA23_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA23_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN K14 [get_ports FMC_LA23_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA23_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA13 [get_ports FMC_LA24_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA24_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB13 [get_ports FMC_LA24_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA24_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA15 [get_ports FMC_LA25_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA25_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB15 [get_ports FMC_LA25_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA25_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN L14 [get_ports FMC_LA26_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA26_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN L15 [get_ports FMC_LA26_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA26_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN L16 [get_ports FMC_LA27_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA27_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN K16 [get_ports FMC_LA27_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA27_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA9 [get_ports FMC_LA28_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA28_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB10 [get_ports FMC_LA28_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA28_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN W11 [get_ports FMC_LA29_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA29_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN W12 [get_ports FMC_LA29_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA29_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN G17 [get_ports FMC_LA30_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA30_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN G18 [get_ports FMC_LA30_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA30_N]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN R3 [get_ports FMC_LA31_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA31_P]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN R2 [get_ports FMC_LA31_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA31_N]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN W2 [get_ports FMC_LA32_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA32_P]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN Y2 [get_ports FMC_LA32_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA32_N]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN R6 [get_ports FMC_LA33_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA33_P]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN T6 [get_ports FMC_LA33_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA33_N]
#OCTOPUS SMALL
#NET "IIC1_SDA" LOC = | IOSTANDARD = LVCMOS33; #Bank ?? VCCO - ?.? V
#NET "IIC1_SCL" LOC = | IOSTANDARD = LVCMOS33; #Bank ?? VCCO - ?.? V
#NET "EN_SCLK" LOC = | IOSTANDARD = LVCMOS33; #Bank ?? VCCO - ?.? V
#NET "PMT_P[0]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[0]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[1]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[1]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[2]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[2]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[3]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[3]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[4]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[4]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[5]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[5]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[6]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[6]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[7]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[7]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[8]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[8]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[9]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[9]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[10]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[10]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[11]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[11]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA0P" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA0N" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA1P" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA1N" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA2P" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA2N" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#OCTOPUS LARGE
#NET "IIC2_SDA" LOC = | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - ?.? V
#NET "IIC2_SCL" LOC = | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - ?.? V
#NET "EN_LCLK" LOC = | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - ?.? V
#NET "PMT_P[12]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[12]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[13]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[13]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[14]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[14]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[15]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[15]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[16]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[16]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[17]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[17]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[18]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[18]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[19]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[19]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[20]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[20]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[21]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[21]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[22]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[22]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[23]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[23]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[24]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[24]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[25]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[25]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[26]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[26]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[27]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[27]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[28]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[28]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[29]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[29]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_P[30]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
#NET "PMT_N[30]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
\ No newline at end of file
fetchto = "../../ip_cores"
files = [
"clbv4_wr_ref_top.vhd",
"clbv4_wr_ref_top.xdc",
"clbv4_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
/* FILE : clbv4_wr_ref_top.bmm
* Define a BRAM map for the LM32 memory.
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory
* g_dpram_size = 90112/4 = 22528
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
*
* ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command
* "data2mem -bm clbv4_wr_ref_top_bd.bmm -bt clbv4_wr_ref_top_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
-------------------------------------------------------------------------------
-- Title : WRPC reference design for KM3NeT Central Logic Board (CLBv4)
-- : based on kintex-7
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : clbv4_wr_ref_top.vhd
-- Author(s) : Pascal Bos <bosp@nikhef.nl>
-- Company : Nikhef
-- Created : 2019-05-06
-- Last update: 2019-05-06
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the clbv4.
--
-- This is a reference top HDL that instanciates the WR PTP Core together with
-- its peripherals to be run on a CLB card.
--
-- There are two main usecases for this HDL file:
-- * let new users easily synthesize a WR PTP Core bitstream that can be run on
-- reference hardware
-- * provide a reference top HDL file showing how the WRPC can be instantiated
-- in HDL projects.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv4_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clbv4_wr_ref_top is
generic (
g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16_direct_dmtd.bram";
-- In Vivado Project-Mode, during a Synthesis run or an Implementation run, the Vivado working
-- directory temporarily changes to the "project_name/project_name.runs/run_name" directory.
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0
);
port (
---------------------------------------------------------------------------`
-- Clocks/resets
---------------------------------------------------------------------------
-- Local oscillators
clk_125m_dmtd_p_i : in std_logic; -- 124.992 MHz PLL reference
clk_125m_dmtd_n_i : in std_logic;
clk_125m_gtx_n_i : in std_logic; -- 125.000 MHz GTX reference
clk_125m_gtx_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
--sfp_mod_def0_i : in std_logic; -- sfp detect not present on GlenAir module
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Miscellanous clbv3 pins
---------------------------------------------------------------------------
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
-- Reset control
reset_i : in std_logic;
suicide : out std_logic;
WDI : out std_logic;
WD_SET : out std_logic_vector(2 downto 0);
-- test_lemo outputs PPS
test_lemo : out std_logic;
-- Monitoring signals output on External Debug Connector J35
pps_mon : out std_logic;
ref_clk_mon : out std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC Pins
-- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
-- 10MHz & 1-PPS from external reference (in GrandMaster mode).
---------------------------------------------------------------------------
-- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
-- external reference input.
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
-- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
-- the mezzanine front panel.
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
-- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
-- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
-- of I/O (N+1) on the front panel of the mezzanine
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
-- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
-- panel is configured as an output.
dio_oe_n_o : out std_logic_vector(4 downto 0);
-- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
-- panel is 50-ohm terminated
dio_term_en_o : out std_logic_vector(4 downto 0);
-- Two LEDs on the mezzanine panel. Only Top one is currently used - to
-- blink 1-PPS.
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic;
-- I2C interface for accessing FMC EEPROM. Deprecated, was used in
-- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic;
-- Bulls-eye connector outputs
txts_p_o : out std_logic;
txts_n_o : out std_logic;
rxts_p_o : out std_logic;
rxts_n_o : out std_logic;
pps_p_o : out std_logic;
pps_n_o : out std_logic;
clk_ref_62m5_p_o : out std_logic;
clk_ref_62m5_n_o : out std_logic;
clk_dmtd_62m5_p_o : out std_logic;
clk_dmtd_62m5_n_o : out std_logic
);
end entity clbv4_wr_ref_top;
architecture top of clbv4_wr_ref_top is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- clock and reset
signal reset_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_62m5_n : std_logic;
signal clk_ref_62m5 : std_logic;
signal clk_dmtd_62m5 : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_ext_10m : std_logic;
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
signal wrc_pps_out : std_logic;
signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
-- DIO Mezzanine
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
-- BullsEye connector outputs
signal txts_oddr : std_logic;
signal rxts_oddr : std_logic;
signal pps_oddr : std_logic;
signal clk_ref_62m5_oddr : std_logic;
signal clk_dmtd_62m5_oddr : std_logic;
begin -- architecture top
suicide<= '1';
reset_n <= not reset_i; -- Reset = high active on CLB
WDI <= '0';
WD_SET <="001"; --disable Watchdog
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
cmp_xwrc_board_clbv4 : xwrc_board_clbv4
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_dpram_initf,
g_fabric_iface => PLAIN)
port map (
areset_n_i => reset_n,
clk_125m_dmtd_n_i => clk_125m_dmtd_n_i,
clk_125m_dmtd_p_i => clk_125m_dmtd_p_i,
clk_125m_gtx_n_i => clk_125m_gtx_n_i,
clk_125m_gtx_p_i => clk_125m_gtx_p_i,
clk_10m_ext_i => clk_ext_10m,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_62m5_o => clk_ref_62m5,
clk_dmtd_62m5_o => clk_dmtd_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_62m5_n_o => rst_ref_62m5_n,
dac_refclk_cs_n_o => dac_refclk_cs_n_o,
dac_refclk_sclk_o => dac_refclk_sclk_o,
dac_refclk_din_o => dac_refclk_din_o,
dac_dmtd_cs_n_o => dac_dmtd_cs_n_o,
dac_dmtd_sclk_o => dac_dmtd_sclk_o,
dac_dmtd_din_o => dac_dmtd_din_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => '0',
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
pps_ext_i => wrc_pps_in,
pps_p_o => wrc_pps_out,
pps_led_o => wrc_pps_led,
led_link_o => led_link_o,
led_act_o => led_act_o);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- tri-state onewire access
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
------------------------------------------------------------------------------
-- Digital I/O FMC Mezzanine connections
------------------------------------------------------------------------------
gen_dio_iobufs: for I in 0 to 4 generate
U_ibuf: IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_in(i),
I => dio_p_i(i),
IB => dio_n_i(i));
U_obuf : OBUFDS
port map (
I => dio_out(i),
O => dio_p_o(i),
OB => dio_n_o(i));
end generate;
-- Configure Digital I/Os 0 to 2 as outputs
dio_oe_n_o(2 downto 0) <= (others => '0');
-- Configure Digital I/Os 3 and 4 as inputs for external reference
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
-- Configure Digital I/Os 3 to 4 inputs to be terminated.
dio_term_en_o <= "11000";
-- EEPROM I2C tri-states
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
eeprom_sda_in <= dio_sda_b;
dio_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
eeprom_scl_in <= dio_scl_b;
-- Div by 2 reference clock to LEMO connector
process(clk_ref_62m5)
begin
if rising_edge(clk_ref_62m5) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
cmp_ibugds_extref: IBUFGDS
generic map (
DIFF_TERM => true)
port map (
O => clk_ext_10m,
I => dio_clk_p_i,
IB => dio_clk_n_i);
wrc_pps_in <= dio_in(3);
dio_out(0) <= wrc_pps_out;
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
test_lemo <= wrc_pps_out;
pps_mon <= wrc_pps_out;
ref_clk_mon <= clk_ref_62m5;
-- LEDs
U_Extend_PPS : gc_extend_pulse
generic map (
g_width => 10000000)
port map (
clk_i => clk_ref_62m5,
rst_n_i => rst_ref_62m5_n,
pulse_i => wrc_pps_led,
extended_o => dio_led_top_o);
dio_led_bot_o <= '0';
------------------------------------------------------------------------------
-- BullsEye connector outputs
------------------------------------------------------------------------------
-- tx timestamp for absolute calibration
oddr_txts: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => txts_oddr,
C => clk_ref_62m5,
CE => '1',
D1 => wrc_abscal_txts_out,
D2 => wrc_abscal_txts_out,
R => '0',
S => '0');
obuf_txts: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => txts_p_o,
OB => txts_n_o,
I => txts_oddr);
-- rx timestamp for absolute calibration
oddr_rxts: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => rxts_oddr,
C => clk_ref_62m5,
CE => '1',
D1 => wrc_abscal_rxts_out,
D2 => wrc_abscal_rxts_out,
R => '0',
S => '0');
obuf_rxts: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => rxts_p_o,
OB => rxts_n_o,
I => rxts_oddr);
-- PPS (also used for absolute calibration)
oddr_pps: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => pps_oddr,
C => clk_ref_62m5,
CE => '1',
D1 => wrc_pps_out,
D2 => wrc_pps_out,
R => '0',
S => '0');
obuf_pps: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => pps_p_o,
OB => pps_n_o,
I => pps_oddr);
-- clk_ref_62m5
oddr_clk_ref_62m5: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => clk_ref_62m5_oddr,
C => clk_ref_62m5,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0');
obuf_clk_ref_62m5: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => clk_ref_62m5_p_o,
OB => clk_ref_62m5_n_o,
I => clk_ref_62m5_oddr);
-- clk_dmtd_62m5 (debug purposes)
oddr_clk_dmtd_62m5: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => clk_dmtd_62m5_oddr,
C => clk_dmtd_62m5,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0');
obuf_clk_dmtd_62m5: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => clk_dmtd_62m5_p_o,
OB => clk_dmtd_62m5_n_o,
I => clk_dmtd_62m5_oddr);
end architecture top;
# ---------------------------------------------------------------------------`
# -- Clocks/resets
# ---------------------------------------------------------------------------
# -- Local oscillators
#Bank 15 VCCO - 2.5 V -- CVPD-922-124.992 MHz PLL reference
set_property PACKAGE_PIN F17 [get_ports clk_125m_dmtd_p_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_p_i]
set_property PACKAGE_PIN E17 [get_ports clk_125m_dmtd_n_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_n_i]
create_clock -period 8.000 -name clk_125m_dmtd_p_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i]
#create_clock -period 8.000 -name clk_125m_dmtd_n_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_n_i] # AR57109: "Only P side needs constraint"
create_generated_clock -name clk_dmtd -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_clbv4/cmp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.clk_dmtd_reg/Q]
#Bank 116 -- 125.000 MHz GTP reference
set_property PACKAGE_PIN D6 [get_ports clk_125m_gtx_p_i]
set_property PACKAGE_PIN D5 [get_ports clk_125m_gtx_n_i]
create_clock -period 8.000 -name clk_125m_gtx_p_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
#create_clock -period 8.000 -name clk_125m_gtx_n_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
set_clock_groups -asynchronous \
-group {clk_sys } \
-group {clk_dmtd } \
-group {clk_125m_dmtd_p_i } \
-group {clk_125m_gtx_p_i } \
-group {RXOUTCLK} \
-group {TXOUTCLK} \
-group {clk_ext_mul } \
-group {dio_clk_p_i}
# ---------------------------------------------------------------------------
# -- SPI interface to DACs
# ---------------------------------------------------------------------------
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN B15 [get_ports dac_dmtd_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_din_o]
set_property PACKAGE_PIN B14 [get_ports dac_dmtd_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_sclk_o]
set_property PACKAGE_PIN A15 [get_ports dac_dmtd_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_cs_n_o]
set_property PACKAGE_PIN A13 [get_ports dac_refclk_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_din_o]
set_property PACKAGE_PIN A12 [get_ports dac_refclk_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_sclk_o]
set_property PACKAGE_PIN A14 [get_ports dac_refclk_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_cs_n_o]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
#Bank 116
set_property PACKAGE_PIN B5 [get_ports sfp_rxn_i]
set_property PACKAGE_PIN B6 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN A3 [get_ports sfp_txn_o]
set_property PACKAGE_PIN A4 [get_ports sfp_txp_o]
##Bank 14 VCCO - 3.3 V -- sfp detect NOT PRESENT
#set_property PACKAGE_PIN E26 [get_ports sfp_mod_def0_i]
#set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def0_i]
#Bank 14 VCCO - 3.3 V -- scl
set_property PACKAGE_PIN J26 [get_ports sfp_mod_def1_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def1_b]
#Bank 14 VCCO - 3.3 V -- sda
set_property PACKAGE_PIN H26 [get_ports sfp_mod_def2_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def2_b]
#Bank 14 VCCO - 3.3 V NOT PRESENT
set_property PACKAGE_PIN G26 [get_ports sfp_rate_select_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_rate_select_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN C26 [get_ports sfp_tx_fault_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_fault_i]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN D26 [get_ports sfp_tx_disable_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_disable_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN F25 [get_ports sfp_los_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_los_i]
# ---------------------------------------------------------------------------
# -- Onewire interface
# ---------------------------------------------------------------------------
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN L23 [get_ports onewire_b]
set_property IOSTANDARD LVCMOS33 [get_ports onewire_b]
# ---------------------------------------------------------------------------
# -- UART
# ---------------------------------------------------------------------------
#TEST & DEBUG
# Signal uart_rxd_i is an input in the design and must be connected to pin 21/13 (TXD_SCI) of U26 (CP2105)
# Signal uart_txd_o is an output in the design and must be connected to pin 20/12 (RXD_SCI) of U26 (CP2105)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
#Bank 15 VCCO - 2.5 V
set_property PACKAGE_PIN D19 [get_ports uart_rxd_i]
set_property IOSTANDARD LVCMOS25 [get_ports uart_rxd_i]
set_property PULLDOWN true [get_ports uart_rxd_i]
set_property PACKAGE_PIN D20 [get_ports uart_txd_o]
set_property IOSTANDARD LVCMOS25 [get_ports uart_txd_o]
#Bank 15 VCCO - 1.8 V
#set_property PACKAGE_PIN B19 [get_ports USB_RX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_RX2]
#set_property PULLDOWN true [get_ports USB_RX2]
#set_property PACKAGE_PIN C19 [get_ports USB_TX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_TX2]
#USB Connection on Test&Debug Connector (J35)
#Bank 16 VCCO - 3.3 V
#set_property PACKAGE_PIN F13 [get_ports USBEXT_RX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX1]
#set_property PULLDOWN true [get_ports USBEXT_RX1]
#set_property PACKAGE_PIN F14 [get_ports USBEXT_TX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX1]
#set_property PACKAGE_PIN C13 [get_ports USBEXT_RX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX2]
#set_property PULLDOWN true [get_ports USBEXT_RX2]
#set_property PACKAGE_PIN C14 [get_ports USBEXT_TX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX2]
# ---------------------------------------------------------------------------
# -- WATCHDOG
# ---------------------------------------------------------------------------
set_property PACKAGE_PIN G12 [get_ports WDI]
set_property IOSTANDARD LVCMOS33 [get_ports WDI]
set_property PACKAGE_PIN F12 [get_ports {WD_SET[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WD_SET[0]}]
set_property PACKAGE_PIN D14 [get_ports {WD_SET[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WD_SET[1]}]
set_property PACKAGE_PIN D13 [get_ports {WD_SET[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WD_SET[2]}]
# ---------------------------------------------------------------------------
# -- Miscellanous CLBv4 pins
# ---------------------------------------------------------------------------
#Bank 15 VCCO - 3.3 V
set_property PACKAGE_PIN C16 [get_ports led_act_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_act_o]
#set_property PACKAGE_PIN C16 [get_ports {GPIO_LED[0]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[0]}]
#set_property PACKAGE_PIN B16 [get_ports {GPIO_LED[1]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[1]}]
#set_property PACKAGE_PIN B17 [get_ports {GPIO_LED[2]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[2]}]
#set_property PACKAGE_PIN A17 [get_ports {GPIO_LED[3]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[3]}]
#set_property PACKAGE_PIN A18 [get_ports {GPIO_LED[4]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[4]}]
#set_property PACKAGE_PIN A19 [get_ports {GPIO_LED[5]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[5]}]
set_property PACKAGE_PIN B16 [get_ports led_link_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_link_o]
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN E11 [get_ports reset_i]
set_property IOSTANDARD LVCMOS33 [get_ports reset_i]
#Bank 15 VCCO - 2.5 V
set_property PACKAGE_PIN K15 [get_ports suicide]
set_property IOSTANDARD LVCMOS25 [get_ports suicide]
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN B11 [get_ports test_lemo]
set_property IOSTANDARD LVCMOS33 [get_ports test_lemo]
#Bank 14 VCCO - 3.3 V Monitoring signals output on External Debug Connector J35
set_property PACKAGE_PIN D25 [get_ports pps_mon]
set_property IOSTANDARD LVCMOS33 [get_ports pps_mon]
set_property PACKAGE_PIN F23 [get_ports ref_clk_mon]
set_property IOSTANDARD LVCMOS33 [get_ports ref_clk_mon]
# ---------------------------------------------------------------------------
# -- Digital I/O FMC Pins
# -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
# -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
# ---------------------------------------------------------------------------
# -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
# -- external reference input.
#CLK1_M2C_P
set_property PACKAGE_PIN Y22 [get_ports dio_clk_p_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_p_i]
#CLK1_M2C_N
set_property PACKAGE_PIN AA22 [get_ports dio_clk_n_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_n_i]
# -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
# -- the mezzanine front panel.
#LA00_P
set_property PACKAGE_PIN N21 [get_ports {dio_p_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[4]}]
#LA00_N
set_property PACKAGE_PIN N22 [get_ports {dio_n_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[4]}]
#LA03_P
set_property PACKAGE_PIN P16 [get_ports {dio_p_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[3]}]
#LA03_N
set_property PACKAGE_PIN N17 [get_ports {dio_n_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[3]}]
#LA16_P
set_property PACKAGE_PIN AB26 [get_ports {dio_p_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[2]}]
#LA16_N
set_property PACKAGE_PIN AC26 [get_ports {dio_n_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[2]}]
#LA20_P
set_property PACKAGE_PIN K20 [get_ports {dio_p_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[1]}]
#LA20_N
set_property PACKAGE_PIN J20 [get_ports {dio_n_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[1]}]
#LA33_P
set_property PACKAGE_PIN P19 [get_ports {dio_p_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[0]}]
#LA33_N
set_property PACKAGE_PIN P20 [get_ports {dio_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
# -- of I/O (N+1) on the front panel of the mezzanine
#LA04_P
set_property PACKAGE_PIN N18 [get_ports {dio_p_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[4]}]
#LA04_N
set_property PACKAGE_PIN M19 [get_ports {dio_n_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[4]}]
#LA07_P
set_property PACKAGE_PIN U19 [get_ports {dio_p_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[3]}]
#LA07_N
set_property PACKAGE_PIN U20 [get_ports {dio_n_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[3]}]
#LA08_P
set_property PACKAGE_PIN W20 [get_ports {dio_p_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[2]}]
#LA08_N
set_property PACKAGE_PIN Y21 [get_ports {dio_n_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[2]}]
#LA28_P
set_property PACKAGE_PIN M21 [get_ports {dio_p_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[1]}]
#LA28_N
set_property PACKAGE_PIN M22 [get_ports {dio_n_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[1]}]
#LA29_P
set_property PACKAGE_PIN N19 [get_ports {dio_p_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[0]}]
#LA29_N
set_property PACKAGE_PIN M20 [get_ports {dio_n_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[0]}]
# -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
# -- panel is configured as an output.
#LA05_P
set_property PACKAGE_PIN AE22 [get_ports {dio_oe_n_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[4]}]
#LA11_P
set_property PACKAGE_PIN U26 [get_ports {dio_oe_n_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[3]}]
#LA15_N
set_property PACKAGE_PIN AB25 [get_ports {dio_oe_n_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[2]}]
#LA24_N
set_property PACKAGE_PIN N23 [get_ports {dio_oe_n_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[1]}]
#LA30_P
set_property PACKAGE_PIN P24 [get_ports {dio_oe_n_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[0]}]
# -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
# -- panel is 50-ohm terminated
#LA09_N
set_property PACKAGE_PIN P25 [get_ports {dio_term_en_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[4]}]
#LA09_P
set_property PACKAGE_PIN R25 [get_ports {dio_term_en_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[3]}]
#LA05_N
set_property PACKAGE_PIN AF22 [get_ports {dio_term_en_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[2]}]
#LA06_N
set_property PACKAGE_PIN AF25 [get_ports {dio_term_en_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[1]}]
#LA30_N
set_property PACKAGE_PIN N24 [get_ports {dio_term_en_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[0]}]
# -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
# -- blink 1-PPS.
#LA01_P
set_property PACKAGE_PIN R21 [get_ports dio_led_top_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_top_o]
#LA01_N
set_property PACKAGE_PIN P21 [get_ports dio_led_bot_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
# -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
# -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN J25 [get_ports dio_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_scl_b]
set_property PACKAGE_PIN J24 [get_ports dio_sda_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_sda_b]
# ---------------------------------------------------------------------------
# -- Bulls-eye connector outputs
# ---------------------------------------------------------------------------
#Bank 34 VCCO - 1.8 V -- BullsEye 1
set_property PACKAGE_PIN U6 [get_ports txts_p_o]
set_property IOSTANDARD LVDS [get_ports txts_p_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 2
set_property PACKAGE_PIN U5 [get_ports txts_n_o]
set_property IOSTANDARD LVDS [get_ports txts_n_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 3
set_property PACKAGE_PIN U2 [get_ports rxts_p_o]
set_property IOSTANDARD LVDS [get_ports rxts_p_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 4
set_property PACKAGE_PIN U1 [get_ports rxts_n_o]
set_property IOSTANDARD LVDS [get_ports rxts_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 5
set_property PACKAGE_PIN D15 [get_ports clk_ref_62m5_p_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_ref_62m5_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 6
set_property PACKAGE_PIN D16 [get_ports clk_ref_62m5_n_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_ref_62m5_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 7
set_property PACKAGE_PIN C17 [get_ports pps_p_o]
set_property IOSTANDARD LVDS_25 [get_ports pps_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 8
set_property PACKAGE_PIN C18 [get_ports pps_n_o]
set_property IOSTANDARD LVDS_25 [get_ports pps_n_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 12
set_property PACKAGE_PIN V3 [get_ports clk_dmtd_62m5_p_o]
set_property IOSTANDARD LVDS [get_ports clk_dmtd_62m5_p_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 13
set_property PACKAGE_PIN W3 [get_ports clk_dmtd_62m5_n_o]
set_property IOSTANDARD LVDS [get_ports clk_dmtd_62m5_n_o]
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