Commit 783cb73c authored by Mattia Rizzi's avatar Mattia Rizzi Committed by Maciej Lipinski

Added support for the external board

parent 3c2a6c72
......@@ -70,6 +70,10 @@ entity wr_softpll_ng is
-- for wideband locking of the local oscillator to an external stable reference
-- (e.g. GPSDO/Cesium 10 MHz)
g_with_ext_clock_input : boolean := false;
-- When true, an additional DDMTD tagger is instantiated for wideband locking the
-- local oscillator to the reference provided from the daughterboard
g_with_ext_daughterboard : boolean := true;
-- When true, DDMTD inputs are reversed (so that the DDMTD offset clocks is
-- being sampled by the measured clock). This is functionally equivalent to
......@@ -114,6 +118,9 @@ entity wr_softpll_ng is
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
-- External 10 MHz reference, multiplied to 62.5 MHz using external AD9516
clk_ext_db_i : in std_logic;
-- External clock sync/alignment singnal. SoftPLL will align clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i.
......@@ -165,7 +172,7 @@ architecture rtl of wr_softpll_ng is
constant c_DBG_FIFO_THRESHOLD : integer := 8180;
constant c_DBG_FIFO_COALESCE : integer := 100;
constant c_BB_ERROR_BITS : integer := 16;
component dmtd_with_deglitcher
generic (
g_counter_bits : natural;
......@@ -235,12 +242,30 @@ architecture rtl of wr_softpll_ng is
return integer is
begin
if(g_with_ext_clock_input) then
return g_num_ref_inputs + g_num_outputs + 1;
else
if (g_with_ext_daughterboard) then
return g_num_ref_inputs + g_num_outputs + 2;
else
return g_num_ref_inputs + g_num_outputs + 1;
end if;
else
return g_num_ref_inputs + g_num_outputs;
end if;
end f_num_total_channels;
function f_num_ext_ref_channels
return integer is
begin
if(g_with_ext_clock_input) then
if (g_with_ext_daughterboard) then
return 2;
else
return 1;
end if;
else
return 0;
end if;
end f_num_ext_ref_channels;
function f_pick (
cond : boolean;
if_true : std_logic;
......@@ -322,6 +347,7 @@ architecture rtl of wr_softpll_ng is
signal aligner_sample_valid, aligner_sample_ack : std_logic_vector(g_num_outputs downto 0);
signal aligner_sample_cref, aligner_sample_cin : t_aligner_sample_array;
begin -- rtl
U_Adapter : wb_slave_adapter
......@@ -479,7 +505,7 @@ begin -- rtl
debug_o(1) <= tags_p(g_num_ref_inputs + g_num_outputs);
debug_o(2) <= tags_p(g_num_ref_inputs);
U_DMTD_EXT : dmtd_with_deglitcher
U_DMTD_EXT_internal : dmtd_with_deglitcher
generic map (
g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2,
......@@ -507,6 +533,39 @@ begin -- rtl
dbg_dmtdout_o => debug_o(3),
dbg_clk_d3_o => debug_o(5));
gen_with_ext_daughterboard: if (g_with_ext_daughterboard) generate
U_DMTD_EXT_daughterboard : dmtd_with_deglitcher
generic map (
g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2,
g_reverse => g_reverse_dmtds)
port map (
rst_n_dmtdclk_i => rst_n_i, -- FIXME!
rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => clk_dmtd_i,
clk_dmtd_en_i => '1',
clk_sys_i => clk_sys_i,
clk_in_i => clk_ext_db_i,
resync_done_o => open,
resync_start_p_i => '0',
resync_p_a_i => fb_resync_out(0),
resync_p_o => open,
tag_o => tags(g_num_ref_inputs + g_num_outputs + 1),
tag_stb_p1_o => tags_p(g_num_ref_inputs + g_num_outputs + 1),
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open,
dbg_clk_d3_o => open);
end generate gen_with_ext_daughterboard;
U_Aligner_EXT : spll_aligner
generic map (
g_counter_width => 28,
......@@ -631,11 +690,25 @@ begin -- rtl
end if;
end loop; -- i
if(g_with_ext_clock_input and tags_p(f_num_total_channels-1) = '1') then
tags_req(f_num_total_channels-1) <= regs_in.eccr_ext_en_o;
elsif(g_with_ext_clock_input and tags_grant(f_num_total_channels-1) = '1') then
if (f_num_ext_ref_channels = 1) then
if(tags_p(f_num_total_channels-1) = '1') then
tags_req(f_num_total_channels-1) <= regs_in.eccr_ext_en_o;
elsif(tags_grant(f_num_total_channels-1) = '1') then
tags_req(f_num_total_channels-1) <= '0';
end if;
end if;
end if;
if (f_num_ext_ref_channels = 2) then
if(tags_p(f_num_total_channels-2) = '1') then
tags_req(f_num_total_channels-2) <= regs_in.eccr_ext_en_o;
elsif(tags_grant(f_num_total_channels-1) = '1') then
tags_req(f_num_total_channels-2) <= '0';
end if;
if(tags_p(f_num_total_channels-1) = '1') then
tags_req(f_num_total_channels-1) <= regs_in.eccr_ext_en_o;
elsif(tags_grant(f_num_total_channels-1) = '1') then
tags_req(f_num_total_channels-1) <= '0';
end if;
end if;
end if;
end if;
......
......@@ -103,6 +103,10 @@ entity xwr_softpll_ng is
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
-- External 10 MHz reference, multiplied to 62.5 MHz using external AD9516
clk_ext_db_i : in std_logic;
-- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i.
......@@ -158,6 +162,7 @@ architecture wrapper of xwr_softpll_ng is
clk_ext_mul_locked_i : in std_logic;
clk_ext_stopped_i : in std_logic;
clk_ext_rst_o : out std_logic;
clk_ext_db_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
......@@ -210,6 +215,7 @@ begin -- behavioral
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_stopped_i => clk_ext_stopped_i,
clk_ext_rst_o => clk_ext_rst_o,
clk_ext_db_i => clk_ext_db_i,
pps_csync_p1_i => pps_csync_p1_i,
pps_ext_a_i => pps_ext_a_i,
dac_dmtd_data_o => dac_dmtd_data_o,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment