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White Rabbit core collection
Commit 77e5f494 authored by Antonin Broquet's avatar Antonin Broquet
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wip, fix for last general-cores modules + remove resync from same clock domain

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board/common/xwrc_board_common.vhd
View file @ 77e5f494
......@@ -318,7 +318,7 @@ begin -- architecture struct
-- The WR PTP core itself
-----------------------------------------------------------------------------
cmp_xwr_core : xwr_core
cmp_xwr_core : entity work.xwr_core
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input,
......
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @ 77e5f494
......@@ -7,7 +7,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2021-06-24
-- Last update: 2021-07-08
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -77,7 +77,7 @@ entity ep_timestamping_unit is
-- resets
rst_n_rx_i : in std_logic;
---- rst_n_ref_i : in std_logic;
rst_n_ref_i : in std_logic;
rst_n_sys_i : in std_logic;
-- PPS pulse input (active HI for 1 clk_ref_i cycle) for internal TS counter synchronization
......@@ -200,7 +200,7 @@ begin -- syn
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_sys_i,
rst_n_i => rst_n_ref_i,
pps_p_i => pps_csync_p1_i,
overflow_o => open,
value_r_o => cntr_r,
......@@ -259,96 +259,57 @@ begin -- syn
rx_trigger_a <= (rx_timestamp_trigger_p_a_i and rx_trigger_mask) or rx_cal_pulse_a;
-- Sync chains for timestamp strobes: 4 combinations - (TX-RX) -> (rising/falling)
---- sync_ffs_tx_r : gc_sync_ffs
---- generic map (
---- g_sync_edge => "positive")
---- port map (
---- clk_i => clk_ref_i,
---- rst_n_i => rst_n_sys_i,
---- data_i => tx_timestamp_trigger_p_a_i,
---- synced_o => open,
---- npulse_o => open,
---- ppulse_o => take_tx_synced_p);
----
----
----
---- sync_ffs_rx_r : gc_sync_ffs
---- generic map (
---- g_sync_edge => "positive")
---- port map (
---- clk_i => clk_ref_i,
---- rst_n_i => rst_n_sys_i,
---- data_i => rx_trigger_a,
---- synced_o => open,
---- npulse_o => open,
---- ppulse_o => take_rx_synced_p);
----
----
---- sync_ffs_tx_f : gc_sync_ffs
---- generic map (
---- g_sync_edge => "negative")
---- port map (
---- clk_i => clk_ref_i,
---- rst_n_i => rst_n_sys_i,
---- data_i => tx_timestamp_trigger_p_a_i,
---- synced_o => open,
---- npulse_o => open,
---- ppulse_o => take_tx_synced_p_fedge);
----
---- sync_ffs_rx_f : gc_sync_ffs
---- generic map (
---- g_sync_edge => "negative")
---- port map (
---- clk_i => clk_ref_i,
---- rst_n_i => rst_n_sys_i,
---- data_i => rx_trigger_a,
---- synced_o => open,
---- npulse_o => open,
---- ppulse_o => take_rx_synced_p_fedge);
sync_ffs_tx_r : gc_edge_detect
sync_ffs_tx_r : gc_sync_ffs
generic map (
g_pulse_edge => "positive",
g_clock_edge => "positive")
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
data_i => tx_timestamp_trigger_p_a_i,
pulse_o => take_tx_synced_p);
sync_ffs_rx_r : gc_edge_detect
clk_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
data_i => tx_timestamp_trigger_p_a_i,
synced_o => open,
npulse_o => open,
ppulse_o => take_tx_synced_p);
sync_ffs_rx_r : gc_sync_ffs
generic map (
g_pulse_edge => "positive",
g_clock_edge => "positive")
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
data_i => rx_trigger_a,
pulse_o => take_rx_synced_p);
clk_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
data_i => rx_trigger_a,
synced_o => open,
npulse_o => open,
ppulse_o => take_rx_synced_p);
sync_ffs_tx_f : gc_edge_detect
sync_ffs_tx_f : gc_sync_ffs
generic map (
g_pulse_edge => "positive",
g_clock_edge => "negative")
g_sync_edge => "negative")
port map (
clk_i => clk_ref_i,
data_i => tx_timestamp_trigger_p_a_i,
pulse_o => take_tx_synced_p_fedge);
clk_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
data_i => tx_timestamp_trigger_p_a_i,
synced_o => open,
npulse_o => open,
ppulse_o => take_tx_synced_p_fedge);
sync_ffs_rx_f : gc_edge_detect
sync_ffs_rx_f : gc_sync_ffs
generic map (
g_pulse_edge => "positive",
g_clock_edge => "negative")
g_sync_edge => "negative")
port map (
clk_i => clk_ref_i,
data_i => rx_trigger_a,
pulse_o => take_rx_synced_p_fedge);
clk_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
data_i => rx_trigger_a,
synced_o => open,
npulse_o => open,
ppulse_o => take_rx_synced_p_fedge);
take_r : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if(rst_n_sys_i = '0') then
if(rst_n_ref_i = '0') then
cntr_rx_r <= (others => '0');
cntr_tx_r <= (others => '0');
......@@ -380,7 +341,7 @@ begin -- syn
take_f : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
if rst_n_sys_i = '0' then
if rst_n_ref_i = '0' then
cntr_rx_f <= (others => '0');
cntr_tx_f <= (others => '0');
else
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 77e5f494
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2021-06-24
-- Last update: 2021-07-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -93,9 +93,9 @@ entity wr_endpoint is
-- resets for various clock domains
rst_sys_n_i : in std_logic;
---- rst_ref_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
---- rst_txclk_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
-- PPS input (1 clk_ref_i cycle HI) for synchronizing timestamp counter
......@@ -475,7 +475,7 @@ begin
port map (
rst_sys_n_i => rst_sys_n_i,
rst_rxclk_n_i => rst_rxclk_n_i,
rst_txclk_n_i => rst_sys_n_i,
rst_txclk_n_i => rst_txclk_n_i,
clk_sys_i => clk_sys_i,
rxpcs_fab_o => rxpcs_fab,
......@@ -699,7 +699,7 @@ begin
clk_sys_i => clk_sys_i,
rst_n_rx_i => rst_rxclk_n_i,
rst_n_sys_i => rst_sys_n_i,
---- rst_n_ref_i => rst_ref_n_i,
rst_n_ref_i => rst_ref_n_i,
pps_csync_p1_i => pps_csync_p1_i,
pps_valid_i => pps_valid_i,
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 77e5f494
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2021-06-23
-- Last update: 2021-07-08
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -83,9 +83,9 @@ entity xwr_endpoint is
-- resets for various clock domains
rst_sys_n_i : in std_logic;
---- rst_ref_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
---- rst_txclk_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
-- PPS input (1 clk_ref_i cycle HI) for synchronizing timestamp counter
......@@ -325,9 +325,9 @@ begin
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
rst_sys_n_i => rst_sys_n_i,
---- rst_ref_n_i => rst_ref_n_i,
rst_ref_n_i => rst_ref_n_i,
rst_dmtd_n_i => rst_dmtd_n_i,
---- rst_txclk_n_i => rst_txclk_n_i,
rst_txclk_n_i => rst_txclk_n_i,
rst_rxclk_n_i => rst_rxclk_n_i,
pps_csync_p1_i => pps_csync_p1_i,
pps_valid_i => pps_valid_i,
......
modules/wr_pps_gen/pps_gen_regs.h
View file @ 77e5f494
......@@ -3,7 +3,7 @@
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Wed Jun 23 23:57:56 2021
* Created : Thu Jul 8 14:05:09 2021
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
......
modules/wr_pps_gen/pps_gen_wb.vhd
View file @ 77e5f494
This diff is collapsed.
modules/wr_pps_gen/pps_gen_wb.wb
View file @ 77e5f494
......@@ -18,7 +18,7 @@ peripheral {
prefix = "CNT_RST";
type = MONOSTABLE;
-- clock = "refclk_i";
clock = "refclk_i";
};
field {
......@@ -29,7 +29,7 @@ peripheral {
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
-- clock = "refclk_i";
clock = "refclk_i";
};
field {
......@@ -44,7 +44,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
-- clock = "refclk_i";
clock = "refclk_i";
};
......@@ -53,7 +53,7 @@ peripheral {
description = "write 1: Sets the UTC/PPS counter to values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers";
prefix = "CNT_SET";
type = MONOSTABLE;
-- clock = "refclk_i";
clock = "refclk_i";
};
......@@ -65,7 +65,7 @@ peripheral {
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
-- clock= "refclk_i";
clock= "refclk_i";
};
};
......@@ -80,7 +80,7 @@ peripheral {
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
-- clock = "refclk_i";
clock = "refclk_i";
};
};
......@@ -96,7 +96,7 @@ peripheral {
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
-- clock = "refclk_i";
clock = "refclk_i";
};
};
......@@ -111,7 +111,7 @@ peripheral {
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
-- clock = "refclk_i";
clock = "refclk_i";
};
};
......@@ -167,7 +167,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
-- clock = "refclk_i";
clock = "refclk_i";
};
field {
......@@ -178,7 +178,7 @@ peripheral {
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
-- clock = "refclk_i";
clock = "refclk_i";
};
field {
......@@ -189,7 +189,7 @@ peripheral {
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
-- clock = "refclk_i";
clock = "refclk_i";
};
field {
......@@ -200,7 +200,7 @@ peripheral {
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
-- clock = "refclk_i";
clock = "refclk_i";
};
field {
......@@ -209,7 +209,7 @@ peripheral {
write 0: no effect";
prefix = "SEC_SET";
type = MONOSTABLE;
-- clock = "refclk_i";
clock = "refclk_i";
};
field {
......@@ -218,7 +218,7 @@ peripheral {
write 0: no effect";
prefix = "NSEC_SET";
type = MONOSTABLE;
-- clock = "refclk_i";
clock = "refclk_i";
};
};
};
modules/wr_pps_gen/wr_pps_gen.vhd
View file @ 77e5f494
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN (BE-CO-HT)
-- Created : 2010-09-02
-- Last update: 2021-06-24
-- Last update: 2021-07-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -59,7 +59,7 @@ entity wr_pps_gen is
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
---- rst_ref_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_sys_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
......@@ -113,7 +113,7 @@ architecture behavioral of wr_pps_gen is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
---- refclk_i : in std_logic;
refclk_i : in std_logic;
ppsg_cr_cnt_rst_o : out std_logic;
ppsg_cr_cnt_en_o : out std_logic;
ppsg_cr_cnt_adj_o : out std_logic;
......@@ -252,7 +252,7 @@ begin -- behavioral
-- loads adjustment values into internal regsiters
p_wishbone_loads : process(clk_sys_i)
p_wishbone_loads : process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
......@@ -285,7 +285,7 @@ begin -- behavioral
p_external_sync : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
if(rst_sys_n_i = '0') then
if(rst_ref_n_i = '0') then
sync_in_progress <= '0';
ppsg_escr_sync_in <= '0';
else
......@@ -312,63 +312,54 @@ begin -- behavioral
p_count_nsec : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_sys_n_i = '0' then
if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
cntr_nsec <= (others => '0');
ns_overflow <= '0';
ns_overflow_adv <= '0';
adjust_in_progress_nsec <= '0';
else
if ppsg_cr_cnt_rst = '1' then
cntr_nsec <= (others => '0');
ns_overflow <= '0';
ns_overflow_adv <= '0';
adjust_in_progress_nsec <= '0';
else
-- counter is enabled?
if(ppsg_cr_cnt_en = '1') then
-- got ADJUST OFFSET command
if(cntr_adjust_p = '1') then
-- start waiting for next counter overflow
adjust_in_progress_nsec <= '1';
end if;
-- got SET TIME command - load the counter with new value
if(ppsg_cr_cnt_set_p = '1' or ext_sync_p = '1' or ppsg_escr_nsec_set = '1') then
cntr_nsec <= adj_nsec;
ns_overflow <= '0';
ns_overflow_adv <= '0';
-- got counter overflow:
elsif(cntr_nsec = to_unsigned(c_PERIOD-3, cntr_nsec'length)) then
ns_overflow <= '0';
ns_overflow_adv <= '1';
cntr_nsec <= cntr_nsec + 1;
elsif(cntr_nsec = to_unsigned(c_PERIOD-2, cntr_nsec'length)) then
ns_overflow <= '1';
ns_overflow_adv <= '0';
cntr_nsec <= cntr_nsec + 1;
elsif(cntr_nsec = to_unsigned(c_PERIOD-1, cntr_nsec'length)) then
ns_overflow <= '0';
ns_overflow_adv <= '0';
-- we're in the middle of offset adjustment - load the counter with
-- offset value instead of resetting it. This equals to subtracting the offset
-- but takes less logic.
if(adjust_in_progress_nsec = '1') then
cntr_nsec <= adj_nsec;
adjust_in_progress_nsec <= '0';
else
-- normal counter reset. Generate overflow pulse.
cntr_nsec <= (others => '0');
end if;
else
ns_overflow <= '0';
ns_overflow_adv <= '0';
cntr_nsec <= cntr_nsec + 1;
end if;
-- counter is enabled?
elsif(ppsg_cr_cnt_en = '1') then
-- got ADJUST OFFSET command
if(cntr_adjust_p = '1') then
-- start waiting for next counter overflow
adjust_in_progress_nsec <= '1';
end if;
-- got SET TIME command - load the counter with new value
if(ppsg_cr_cnt_set_p = '1' or ext_sync_p = '1' or ppsg_escr_nsec_set = '1') then
cntr_nsec <= adj_nsec;
ns_overflow <= '0';
ns_overflow_adv <= '0';
-- got counter overflow:
elsif(cntr_nsec = to_unsigned(c_PERIOD-3, cntr_nsec'length)) then
ns_overflow <= '0';
ns_overflow_adv <= '1';
cntr_nsec <= cntr_nsec + 1;
elsif(cntr_nsec = to_unsigned(c_PERIOD-2, cntr_nsec'length)) then
ns_overflow <= '1';
ns_overflow_adv <= '0';
cntr_nsec <= cntr_nsec + 1;
elsif(cntr_nsec = to_unsigned(c_PERIOD-1, cntr_nsec'length)) then
ns_overflow <= '0';
ns_overflow_adv <= '0';
-- we're in the middle of offset adjustment - load the counter with
-- offset value instead of resetting it. This equals to subtracting the offset
-- but takes less logic.
if(adjust_in_progress_nsec = '1') then
cntr_nsec <= adj_nsec;
adjust_in_progress_nsec <= '0';
else
-- normal counter reset. Generate overflow pulse.
cntr_nsec <= (others => '0');
end if;
else
ns_overflow <= '0';
ns_overflow_adv <= '0';
cntr_nsec <= cntr_nsec + 1;
end if;
end if;
end if;
......@@ -378,24 +369,19 @@ begin -- behavioral
p_drive_pps_valid : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_sys_n_i = '0' then
if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
pps_valid_int <= '0';
ns_overflow_2nd <= '0';
else
if ppsg_cr_cnt_rst = '1' then
if(sync_in_progress = '1' or adjust_in_progress_nsec = '1' or adjust_in_progress_utc = '1') then
pps_valid_int <= '0';
ns_overflow_2nd <= '0';
else
if(sync_in_progress = '1' or adjust_in_progress_nsec = '1' or adjust_in_progress_utc = '1') then
pps_valid_int <= '0';
ns_overflow_2nd <= '0';
elsif(adjust_in_progress_utc = '0' and adjust_in_progress_nsec = '0' and sync_in_progress = '0') then
if(ns_overflow = '1') then
ns_overflow_2nd <= '1';
if(ns_overflow_2nd = '1') then
pps_valid_int <= '1';
end if;
elsif(adjust_in_progress_utc = '0' and adjust_in_progress_nsec = '0' and sync_in_progress = '0') then
if(ns_overflow = '1') then
ns_overflow_2nd <= '1';
if(ns_overflow_2nd = '1') then
pps_valid_int <= '1';
end if;
end if;
end if;
......@@ -406,30 +392,25 @@ begin -- behavioral
p_count_utc : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_sys_n_i = '0' then
if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
cntr_utc <= (others => '0');
adjust_in_progress_utc <= '0';
else
if ppsg_cr_cnt_rst = '1' then
cntr_utc <= (others => '0');
adjust_in_progress_utc <= '0';
elsif(ppsg_cr_cnt_en = '1') then
if(ppsg_cr_cnt_set_p = '1' or ppsg_escr_sec_set = '1') then
cntr_utc <= adj_utc;
elsif(cntr_adjust_p = '1') then
adjust_in_progress_utc <= '1';
if(ns_overflow = '1') then
cntr_utc <= cntr_utc +1;
end if;
elsif(adjust_in_progress_utc = '1' and ns_overflow = '1') then
cntr_utc <= cntr_utc + adj_utc + 1;
adjust_in_progress_utc <= '0';
elsif(ns_overflow = '1') then
cntr_utc <= cntr_utc + 1;
elsif(ppsg_cr_cnt_en = '1') then
if(ppsg_cr_cnt_set_p = '1' or ppsg_escr_sec_set = '1') then
cntr_utc <= adj_utc;
elsif(cntr_adjust_p = '1') then
adjust_in_progress_utc <= '1';
if(ns_overflow = '1') then
cntr_utc <= cntr_utc +1;
end if;
elsif(adjust_in_progress_utc = '1' and ns_overflow = '1') then
cntr_utc <= cntr_utc + adj_utc + 1;
adjust_in_progress_utc <= '0';
elsif(ns_overflow = '1') then
cntr_utc <= cntr_utc + 1;
end if;
end if;
end if;
......@@ -442,7 +423,7 @@ begin -- behavioral
p_gen_pps_out : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_sys_n_i = '0' then
if rst_ref_n_i = '0' then
pps_out_int <= '0';
pps_led_o <= '0';
width_cntr <= (others => '0');
......@@ -470,7 +451,7 @@ begin -- behavioral
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_sys_n_i = '0' then
if rst_ref_n_i = '0' then
pps_out_o <= '0';
else
pps_out_o <= pps_out_int;
......@@ -490,7 +471,7 @@ begin -- behavioral
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
---- refclk_i => clk_ref_i,
refclk_i => clk_ref_i,
ppsg_cr_cnt_rst_o => ppsg_cr_cnt_rst,
ppsg_cr_cnt_en_o => ppsg_cr_cnt_en,
ppsg_cr_cnt_adj_o => ppsg_cr_cnt_adj_o,
......
modules/wr_pps_gen/xwr_pps_gen.vhd
View file @ 77e5f494
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN (BE-CO-HT)
-- Created : 2010-09-02
-- Last update: 2021-06-23
-- Last update: 2021-07-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -58,7 +58,7 @@ entity xwr_pps_gen is
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
---- rst_ref_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_sys_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
......@@ -95,7 +95,7 @@ architecture behavioral of xwr_pps_gen is
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
---- rst_ref_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_sys_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
......@@ -132,7 +132,7 @@ begin -- behavioral
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
---- rst_ref_n_i => rst_ref_n_i,
rst_ref_n_i => rst_ref_n_i,
rst_sys_n_i => rst_sys_n_i,
wb_adr_i => slave_i.adr(4 downto 0),
wb_dat_i => slave_i.dat,
......
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ 77e5f494
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2021-06-23
-- Last update: 2021-07-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -85,7 +85,7 @@ entity xwr_softpll_ng is
port(
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
---- rst_ref_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
......@@ -153,7 +153,7 @@ architecture wrapper of xwr_softpll_ng is
port (
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
---- rst_ref_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
......@@ -207,7 +207,7 @@ begin -- behavioral
port map (
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
---- rst_ref_n_i => rst_ref_n_i,
rst_ref_n_i => rst_ref_n_i,
rst_ext_n_i => rst_ext_n_i,
rst_dmtd_n_i => rst_dmtd_n_i,
clk_ref_i => clk_ref_i,
......
modules/wrc_core/wr_core.vhd
View file @ 77e5f494
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2021-06-25
-- Last update: 2021-07-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -343,11 +343,11 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--Local resets (resynced)
-----------------------------------------------------------------------------
---- signal rst_net_resync_ref_n : std_logic;
signal rst_net_resync_ref_n : std_logic;
signal rst_net_resync_ext_n : std_logic;
signal rst_net_resync_dmtd_n : std_logic;
signal rst_net_resync_rxclk_n : std_logic;
---- signal rst_net_resync_txclk_n : std_logic;
signal rst_net_resync_txclk_n : std_logic;
-----------------------------------------------------------------------------
--PPS generator
......@@ -519,14 +519,14 @@ begin
rst_aux_n_o <= rst_net_n;
---- U_Sync_reset_refclk : entity work.gc_sync_ffs
---- generic map (
---- g_sync_edge => "positive")
---- port map (
---- clk_i => clk_ref_i,
---- rst_n_i => '1',
---- data_i => rst_net_n,
---- synced_o => rst_net_resync_ref_n);
U_Sync_reset_refclk : entity work.gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => rst_net_n,
synced_o => rst_net_resync_ref_n);
U_sync_reset_dmtd : entity work.gc_sync_ffs
generic map (
......@@ -555,14 +555,14 @@ begin
data_i => rst_net_n,
synced_o => rst_net_resync_rxclk_n);
---- U_sync_reset_txclk : entity work.gc_sync_ffs
---- generic map (
---- g_sync_edge => "positive")
---- port map (
---- clk_i => phy_tx_clk,
---- rst_n_i => '1',
---- data_i => rst_net_n,
---- synced_o => rst_net_resync_txclk_n);
U_sync_reset_txclk : entity work.gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk,
rst_n_i => '1',
data_i => rst_net_n,
synced_o => rst_net_resync_txclk_n);
-----------------------------------------------------------------------------
-- PPS generator
......@@ -579,7 +579,7 @@ begin
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_net_n,
---- rst_ref_n_i => rst_net_resync_ref_n,
rst_ref_n_i => rst_net_resync_ref_n,
slave_i => ppsg_wb_in,
slave_o => ppsg_wb_out,
......@@ -620,7 +620,7 @@ begin
port map(
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_net_n,
---- rst_ref_n_i => rst_net_resync_ref_n,
rst_ref_n_i => rst_net_resync_ref_n,
rst_ext_n_i => rst_net_resync_ext_n,
rst_dmtd_n_i => rst_net_resync_dmtd_n,
......@@ -714,9 +714,9 @@ begin
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
rst_sys_n_i => rst_net_n,
---- rst_ref_n_i => rst_net_resync_ref_n,
rst_ref_n_i => rst_net_resync_ref_n,
rst_dmtd_n_i => rst_net_resync_dmtd_n,
---- rst_txclk_n_i => rst_net_resync_txclk_n,
rst_txclk_n_i => rst_net_resync_txclk_n,
rst_rxclk_n_i => rst_net_resync_rxclk_n,
pps_csync_p1_i => s_pps_csync,
pps_valid_i => pps_valid,
......@@ -862,7 +862,7 @@ begin
g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart,
g_cntr_period => 125000,
g_cntr_period => 62500,
g_mem_words => g_dpram_size,
g_vuart_fifo_size => g_vuart_fifo_size,
g_diag_id => g_diag_id,
......
platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
View file @ 77e5f494
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2021-06-18
-- Last update: 2013-12-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -130,101 +130,101 @@ architecture behavioral of gtp_bitslide is
begin -- behavioral
p_do_slide : process(gtp_rx_clk_i)
p_do_slide : process(gtp_rx_clk_i, gtp_rst_i)
begin
if rising_edge(gtp_rx_clk_i) then
if gtp_rst_i = '1' then
state <= S_SYNC_LOST;
gtp_rx_slide_o <= '0';
counter <= (others => '0');
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
else
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
case state is
-- State: synchronization lost. Waits until a comma pattern is detected
when S_SYNC_LOST =>
cur_slide <= (others => '0');
counter <= (others => '0');
gtp_rx_slide_o <= '0';
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
commas_missed <= (others => '0');
if(gtp_rx_comma_det_i = '1') then
state <= S_STABILIZE;
end if;
-- State: stabilize:
when S_STABILIZE =>
if(gtp_rx_comma_det_i = '1') then
counter <= counter + 1;
commas_missed <= (others => '0');
else
commas_missed <= commas_missed + 1;
if(commas_missed(3) = '1') then
state <= S_SYNC_LOST;
end if;
end if;
if(counter = to_unsigned(c_sync_detect_threshold, counter'length)) then
counter <= (others => '0');
state <= S_PAUSE;
end if;
if(serdes_ready_i = '0') then
if gtp_rst_i = '1' then
state <= S_SYNC_LOST;
gtp_rx_slide_o <= '0';
counter <= (others => '0');
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
elsif rising_edge(gtp_rx_clk_i) then
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
case state is
-- State: synchronization lost. Waits until a comma pattern is detected
when S_SYNC_LOST =>
cur_slide <= (others => '0');
counter <= (others => '0');
gtp_rx_slide_o <= '0';
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
commas_missed <= (others => '0');
if(gtp_rx_comma_det_i = '1') then
state <= S_STABILIZE;
end if;
-- State: stabilize:
when S_STABILIZE =>
if(gtp_rx_comma_det_i = '1') then
counter <= counter + 1;
commas_missed <= (others => '0');
else
commas_missed <= commas_missed + 1;
if(commas_missed(3) = '1') then
state <= S_SYNC_LOST;
end if;
when S_SLIDE =>
if (cur_slide < c_max_bts-1) then
cur_slide <= cur_slide + 1;
end if;
if(counter = to_unsigned(c_sync_detect_threshold, counter'length)) then
counter <= (others => '0');
state <= S_PAUSE;
end if;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_SLIDE =>
if (cur_slide < c_max_bts-1) then
cur_slide <= cur_slide + 1;
else
cur_slide <= (others=>'0');
end if;
gtp_rx_slide_o <= '1';
counter <= (others => '0');
state <= S_PAUSE;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_PAUSE =>
counter <= counter + 1;
gtp_rx_slide_o <= '0';
if(counter = to_unsigned(c_pause_tics, counter'length)) then
if(gtp_rx_byte_is_aligned_i = '0') then
state <= S_SLIDE;
else
cur_slide <= (others=>'0');
state <= S_GOT_SYNC;
end if;
gtp_rx_slide_o <= '1';
counter <= (others => '0');
state <= S_PAUSE;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_PAUSE =>
counter <= counter + 1;
gtp_rx_slide_o <= '0';
if(counter = to_unsigned(c_pause_tics, counter'length)) then
if(gtp_rx_byte_is_aligned_i = '0') then
state <= S_SLIDE;
else
state <= S_GOT_SYNC;
end if;
end if;
when S_GOT_SYNC =>
gtp_rx_slide_o <= '0';
bitslide_o <= std_logic_vector(cur_slide(4 downto 0));
synced_o <= '1';
if(gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0') then
gtp_rx_cdr_rst_o <= '1';
state <= S_SYNC_LOST;
end if;
when others => null;
end case;
end if;
end if;
when S_GOT_SYNC =>
gtp_rx_slide_o <= '0';
bitslide_o <= std_logic_vector(cur_slide(4 downto 0));
synced_o <= '1';
if(gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0') then
gtp_rx_cdr_rst_o <= '1';
state <= S_SYNC_LOST;
end if;
when others => null;
end case;
end if;
end process;
end behavioral;
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