Merge branch 'wrpc-v4.2_gsi' of ssh://ohwr.org:7999/project/wr-cores into wrpc-v4.1_a10

72021622 · A. Hahn · d4590b9d · db2c3118 · 72021622 · 72021622
Commit 72021622 authored Jun 05, 2019 by A. Hahn
166 changed files
--- a/.gitignore
+++ b/.gitignore
@@ -17,3 +17,5 @@ doc/
 *.elf
 *.ucdb
 Makefile
+*.xml
+xgui/
--- a/bin/wrpc/wrc_phy16.bram
+++ b/bin/wrpc/wrc_phy16.bram
--- a/bin/wrpc/wrc_phy8.bram
+++ b/bin/wrpc/wrc_phy8.bram
--- a/bin/wrpc/wrc_phy8.mif
+++ b/bin/wrpc/wrc_phy8.mif
--- a/bin/wrpc/wrc_phy8_sim.bram
+++ b/bin/wrpc/wrc_phy8_sim.bram
--- a/bin/wrpc/wrc_phy8_sim.mif
+++ b/bin/wrpc/wrc_phy8_sim.mif
--- a/board/clbv2/Manifest.py
+++ b/board/clbv2/Manifest.py
+files = [
+    "wr_clbv2_pkg.vhd",
+    "xwrc_board_clbv2.vhd",
+    "wrc_board_clbv2.vhd",
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/clbv2/wr_clbv2_pkg.vhd
+++ b/board/clbv2/wr_clbv2_pkg.vhd
--- a/board/clbv2/wrc_board_clbv2.vhd
+++ b/board/clbv2/wrc_board_clbv2.vhd
--- a/board/clbv2/xwrc_board_clbv2.vhd
+++ b/board/clbv2/xwrc_board_clbv2.vhd
--- a/board/clbv3/Manifest.py
+++ b/board/clbv3/Manifest.py
+files = [
+    "wr_clbv3_pkg.vhd",
+    "xwrc_board_clbv3.vhd",
+    "wrc_board_clbv3.vhd",
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/clbv3/wr_clbv3_pkg.vhd
+++ b/board/clbv3/wr_clbv3_pkg.vhd
--- a/board/clbv3/wrc_board_clbv3.vhd
+++ b/board/clbv3/wrc_board_clbv3.vhd
--- a/board/clbv3/xwrc_board_clbv3.vhd
+++ b/board/clbv3/xwrc_board_clbv3.vhd
--- a/board/common/wr_board_pkg.vhd
+++ b/board/common/wr_board_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : Common WRPC Wrapper package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_common.vhd
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;

@@ -64,6 +96,8 @@ package wr_board_pkg is
      g_simulation                : integer                        := 0;
      g_with_external_clock_input : boolean                        := TRUE;
      g_board_name                : string                         := "NA  ";
+      g_flash_secsz_kb            : integer                        := 256;        -- default for M25P128
+      g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for M25P128
      g_phys_uart                 : boolean                        := TRUE;
      g_virtual_uart              : boolean                        := TRUE;
      g_aux_clks                  : integer                        := 0;

--- a/board/common/xwrc_board_common.vhd
+++ b/board/common/xwrc_board_common.vhd
@@ -4,18 +4,16 @@
 -- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
 -------------------------------------------------------------------------------
 -- File       : xwrc_board_common.vhd
-- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
-- Created    : 2017-02-22
-- Last update: 2017-05-29
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Wrapper for WR PTP core with common features shared between
 -- the various supported boards. These include the core itself, as well as
 -- a selection of fabric interfaces between the core and the application.
 -------------------------------------------------------------------------------
+--
 -- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
+--
 -- GNU LESSER GENERAL PUBLIC LICENSE
 --
 -- This source file is free software; you can redistribute it   
@@ -54,6 +52,8 @@ entity xwrc_board_common is
    g_simulation                : integer                        := 0;
    g_with_external_clock_input : boolean                        := TRUE;
    g_board_name                : string                         := "NA  ";
+    g_flash_secsz_kb            : integer                        := 256;        -- default for M25P128
+    g_flash_sdbfs_baddr         : integer                        := 16#600000#; -- default for M25P128
    g_phys_uart                 : boolean                        := TRUE;
    g_virtual_uart              : boolean                        := TRUE;
    g_aux_clks                  : integer                        := 0;
@@ -323,6 +323,8 @@ begin  -- architecture struct
      g_simulation                => g_simulation,
      g_with_external_clock_input => g_with_external_clock_input,
      g_board_name                => g_board_name,
+      g_flash_secsz_kb            => g_flash_secsz_kb,
+      g_flash_sdbfs_baddr         => g_flash_sdbfs_baddr,
      g_phys_uart                 => g_phys_uart,
      g_virtual_uart              => g_virtual_uart,
      g_aux_clks                  => g_aux_clks,

--- a/board/fasec/Manifest.py
+++ b/board/fasec/Manifest.py
+files = [
+    "wr_fasec_pkg.vhd",
+    "xwrc_board_fasec.vhd",
+    "wrc_board_fasec.vhd",
+    "wrc_board_fasec_ip.xdc"
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/fasec/component.xml
+++ b/board/fasec/component.xml
--- a/board/fasec/wr_fasec_pkg.vhd
+++ b/board/fasec/wr_fasec_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for FASEC package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_fasec_pkg.vhd
+-- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-08-02
+-- Last update: 2017-09-07
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_board_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_fasec_pkg is
+
+  component xwrc_board_fasec
+    generic(
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := TRUE;
+      g_aux_clks                  : integer              := 0;
+      g_fabric_iface              : t_board_fabric_iface := plain;
+      g_streamers_op_mode         : t_streamers_op_mode  := TX_AND_RX;
+      g_tx_streamer_params        : t_tx_streamer_params := c_tx_streamer_params_defaut;
+      g_rx_streamer_params        : t_rx_streamer_params := c_rx_streamer_params_defaut;
+      g_dpram_initf               : string               := "default_xilinx";
+      g_diag_id                   : integer              := 0;
+      g_diag_ver                  : integer              := 0;
+      g_diag_ro_size              : integer              := 0;
+      g_diag_rw_size              : integer              := 0);
+    port (
+      areset_n_i          : in  std_logic;
+      areset_edge_n_i     : in  std_logic := '1';
+      clk_20m_vcxo_i      : in  std_logic;
+      clk_125m_pllref_p_i : in  std_logic;
+      clk_125m_pllref_n_i : in  std_logic;
+      clk_125m_gtp_n_i    : in  std_logic;
+      clk_125m_gtp_p_i    : in  std_logic;
+      clk_aux_i           : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      clk_10m_ext_i       : in  std_logic                               := '0';
+      pps_ext_i           : in  std_logic                               := '0';
+      clk_sys_62m5_o      : out std_logic;
+      clk_ref_125m_o      : out std_logic;
+      rst_sys_62m5_n_o    : out std_logic;
+      rst_ref_125m_n_o    : out std_logic;
+  
+      plldac_sclk_o   : out std_logic;
+      plldac_din_o    : out std_logic;
+      pll25dac_cs_n_o : out std_logic;
+      pll20dac_cs_n_o : out std_logic;
+  
+      sfp_txp_o         : out std_logic;
+      sfp_txn_o         : out std_logic;
+      sfp_rxp_i         : in  std_logic;
+      sfp_rxn_i         : in  std_logic;
+      sfp_det_i         : in  std_logic := '1';
+      sfp_sda_i         : in  std_logic;
+      sfp_sda_o         : out std_logic;
+      sfp_sda_t         : out std_logic;
+      sfp_scl_i         : in  std_logic;
+      sfp_scl_o         : out std_logic;
+      sfp_scl_t         : out std_logic;
+      sfp_rate_select_o : out std_logic;
+      sfp_tx_fault_i    : in  std_logic := '0';
+      sfp_tx_disable_o  : out std_logic;
+      sfp_los_i         : in  std_logic := '0';
+  
+      eeprom_sda_i : in  std_logic;
+      eeprom_sda_o : out std_logic;
+      eeprom_sda_t : out std_logic;
+      eeprom_scl_i : in  std_logic;
+      eeprom_scl_o : out std_logic;
+      eeprom_scl_t : out std_logic;
+    
+      thermo_id_i : in  std_logic;
+      thermo_id_o : out std_logic;
+      thermo_id_t : out std_logic;
+      uart_rxd_i : in  std_logic;
+      uart_txd_o : out std_logic;
+  
+      flash_sclk_o : out std_logic;
+      flash_ncs_o  : out std_logic;
+      flash_mosi_o : out std_logic;
+      flash_miso_i : in  std_logic := '0';
+  
+      aux_master_o : out t_wishbone_master_out;
+      aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      s00_axi_aclk_o  : out std_logic;
+      s00_axi_aresetn : in  std_logic;
+      s00_axi_awaddr  : in std_logic_vector(31 downto 0);
+      s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+      s00_axi_awvalid : in  std_logic;
+      s00_axi_awready : out std_logic;
+      s00_axi_wdata   : in std_logic_vector(31 downto 0);
+      s00_axi_wstrb   : in std_logic_vector(3 downto 0);
+      s00_axi_wvalid  : in  std_logic;
+      s00_axi_wready  : out std_logic;
+      s00_axi_bresp   : out std_logic_vector(1 downto 0);
+      s00_axi_bvalid  : out std_logic;
+      s00_axi_bready  : in std_logic;
+      s00_axi_araddr  : in std_logic_vector(31 downto 0);
+      s00_axi_arprot  : in std_logic_vector(2 downto 0);
+      s00_axi_arvalid : in std_logic;
+      s00_axi_arready : out std_logic;
+      s00_axi_rdata   : out std_logic_vector(31 downto 0);
+      s00_axi_rresp   : out std_logic_vector(1 downto 0);
+      s00_axi_rvalid  : out std_logic;
+      s00_axi_rready  : in std_logic;
+      s00_axi_rlast   : out std_logic;
+      axi_int_o       : out std_logic;
+  
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+  
+      wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+      wrs_tx_valid_i : in  std_logic                                        := '0';
+      wrs_tx_dreq_o  : out std_logic;
+      wrs_tx_last_i  : in  std_logic                                        := '1';
+      wrs_tx_flush_i : in  std_logic                                        := '0';
+      wrs_tx_cfg_i   : in  t_tx_streamer_cfg                                := c_tx_streamer_cfg_default;
+      wrs_rx_first_o : out std_logic;
+      wrs_rx_last_o  : out std_logic;
+      wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+      wrs_rx_valid_o : out std_logic;
+      wrs_rx_dreq_i  : in  std_logic                                        := '0';
+      wrs_rx_cfg_i   : in t_rx_streamer_cfg                                 := c_rx_streamer_cfg_default;
+
+      wb_eth_master_o : out t_wishbone_master_out;
+      wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+  
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+  
+      timestamps_o     : out t_txtsu_timestamp;
+      timestamps_ack_i : in  std_logic := '1';
+  
+      abscal_txts_o       : out std_logic;
+      abscal_rxts_o       : out std_logic;
+  
+      fc_tx_pause_req_i   : in  std_logic                     := '0';
+      fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o : out std_logic;
+  
+      tm_link_up_o    : out std_logic;
+      tm_time_valid_o : out std_logic;
+      tm_tai_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+  
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      btn1_i     : in  std_logic := '1';
+      btn2_i     : in  std_logic := '1';
+      pps_p_o    : out std_logic;
+      pps_led_o  : out std_logic;
+      link_ok_o  : out std_logic);
+  end component xwrc_board_fasec;
+
+end wr_fasec_pkg;
--- a/board/fasec/wrc_board_fasec.vhd
+++ b/board/fasec/wrc_board_fasec.vhd
--- a/board/fasec/wrc_board_fasec_ip.xdc
+++ b/board/fasec/wrc_board_fasec_ip.xdc
+create_clock -period 50.000 -name clk_20m_vcxo -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]
+create_clock -period 8.000 -name clk_125m_pllref -waveform {0.000 4.000} [get_ports clk_125m_pllref_p_i]
+create_clock -period 8.000 -name clk_125m_gtp -waveform {0.000 4.000} [get_ports clk_125m_gtp_p_i]
+create_clock -period 100.000 -name clk_10m_ext -waveform {0.000 50.000} [get_ports clk_10m_ext_i]
+create_clock -period 16.000 -name clk_gtx_rx -waveform {0.000 8.000} [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
+create_generated_clock -name clk_gtx_tx -source [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtp_dedicated_clk/O] -divide_by 2 [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
+
+set_clock_groups -asynchronous -group [get_clocks clk_gtx_rx] -group [get_clocks [get_clocks -of_objects [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_dmtd_clk_pll/CLKOUT0]]]
+set_clock_groups -asynchronous -group [get_clocks clk_gtx_tx] -group [get_clocks [get_clocks -of_objects [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_dmtd_clk_pll/CLKOUT0]]]
+
+set_clock_groups -asynchronous -group [get_clocks clk_sys] -group [get_clocks clk_gtx_rx]
+
+
+
--- a/board/fasec/wrc_board_fasec_v4_1.tcl
+++ b/board/fasec/wrc_board_fasec_v4_1.tcl
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+proc update_PARAM_VALUE.g_aux_clks { PARAM_VALUE.g_aux_clks } {
+	# Procedure called to update g_aux_clks when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_aux_clks { PARAM_VALUE.g_aux_clks } {
+	# Procedure called to validate g_aux_clks
+	return true
+}
+
+proc update_PARAM_VALUE.g_diag_id { PARAM_VALUE.g_diag_id } {
+	# Procedure called to update g_diag_id when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_diag_id { PARAM_VALUE.g_diag_id } {
+	# Procedure called to validate g_diag_id
+	return true
+}
+
+proc update_PARAM_VALUE.g_diag_ro_vector_width { PARAM_VALUE.g_diag_ro_vector_width } {
+	# Procedure called to update g_diag_ro_vector_width when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_diag_ro_vector_width { PARAM_VALUE.g_diag_ro_vector_width } {
+	# Procedure called to validate g_diag_ro_vector_width
+	return true
+}
+
+proc update_PARAM_VALUE.g_diag_rw_vector_width { PARAM_VALUE.g_diag_rw_vector_width } {
+	# Procedure called to update g_diag_rw_vector_width when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_diag_rw_vector_width { PARAM_VALUE.g_diag_rw_vector_width } {
+	# Procedure called to validate g_diag_rw_vector_width
+	return true
+}
+
+proc update_PARAM_VALUE.g_diag_ver { PARAM_VALUE.g_diag_ver } {
+	# Procedure called to update g_diag_ver when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_diag_ver { PARAM_VALUE.g_diag_ver } {
+	# Procedure called to validate g_diag_ver
+	return true
+}
+
+proc update_PARAM_VALUE.g_dpram_initf { PARAM_VALUE.g_dpram_initf } {
+	# Procedure called to update g_dpram_initf when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_dpram_initf { PARAM_VALUE.g_dpram_initf } {
+	# Procedure called to validate g_dpram_initf
+	return true
+}
+
+proc update_PARAM_VALUE.g_fabric_iface { PARAM_VALUE.g_fabric_iface } {
+	# Procedure called to update g_fabric_iface when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_fabric_iface { PARAM_VALUE.g_fabric_iface } {
+	# Procedure called to validate g_fabric_iface
+	return true
+}
+
+proc update_PARAM_VALUE.g_simulation { PARAM_VALUE.g_simulation } {
+	# Procedure called to update g_simulation when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_simulation { PARAM_VALUE.g_simulation } {
+	# Procedure called to validate g_simulation
+	return true
+}
+
+proc update_PARAM_VALUE.g_with_external_clock_input { PARAM_VALUE.g_with_external_clock_input } {
+	# Procedure called to update g_with_external_clock_input when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_with_external_clock_input { PARAM_VALUE.g_with_external_clock_input } {
+	# Procedure called to validate g_with_external_clock_input
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.g_simulation { MODELPARAM_VALUE.g_simulation PARAM_VALUE.g_simulation } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_simulation}] ${MODELPARAM_VALUE.g_simulation}
+}
+
+proc update_MODELPARAM_VALUE.g_with_external_clock_input { MODELPARAM_VALUE.g_with_external_clock_input PARAM_VALUE.g_with_external_clock_input } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_with_external_clock_input}] ${MODELPARAM_VALUE.g_with_external_clock_input}
+}
+
+proc update_MODELPARAM_VALUE.g_aux_clks { MODELPARAM_VALUE.g_aux_clks PARAM_VALUE.g_aux_clks } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_aux_clks}] ${MODELPARAM_VALUE.g_aux_clks}
+}
+
+proc update_MODELPARAM_VALUE.g_fabric_iface { MODELPARAM_VALUE.g_fabric_iface PARAM_VALUE.g_fabric_iface } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_fabric_iface}] ${MODELPARAM_VALUE.g_fabric_iface}
+}
+
+proc update_MODELPARAM_VALUE.g_dpram_initf { MODELPARAM_VALUE.g_dpram_initf PARAM_VALUE.g_dpram_initf } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_dpram_initf}] ${MODELPARAM_VALUE.g_dpram_initf}
+}
+
+proc update_MODELPARAM_VALUE.g_diag_id { MODELPARAM_VALUE.g_diag_id PARAM_VALUE.g_diag_id } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_diag_id}] ${MODELPARAM_VALUE.g_diag_id}
+}
+
+proc update_MODELPARAM_VALUE.g_diag_ver { MODELPARAM_VALUE.g_diag_ver PARAM_VALUE.g_diag_ver } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_diag_ver}] ${MODELPARAM_VALUE.g_diag_ver}
+}
+
+proc update_MODELPARAM_VALUE.g_diag_ro_vector_width { MODELPARAM_VALUE.g_diag_ro_vector_width PARAM_VALUE.g_diag_ro_vector_width } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_diag_ro_vector_width}] ${MODELPARAM_VALUE.g_diag_ro_vector_width}
+}
+
+proc update_MODELPARAM_VALUE.g_diag_rw_vector_width { MODELPARAM_VALUE.g_diag_rw_vector_width PARAM_VALUE.g_diag_rw_vector_width } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_diag_rw_vector_width}] ${MODELPARAM_VALUE.g_diag_rw_vector_width}
+}
+
--- a/board/fasec/xwrc_board_fasec.vhd
+++ b/board/fasec/xwrc_board_fasec.vhd
--- a/board/spec/wr_spec_pkg.vhd
+++ b/board/spec/wr_spec_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for SPEC package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_spec_pkg.vhd
+-- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-02-17
+-- Last update: 2017-07-04
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;

@@ -57,9 +91,9 @@ package wr_spec_pkg is
      sfp_tx_fault_i       : in  std_logic                                        := '0';
      sfp_tx_disable_o     : out std_logic;
      sfp_los_i            : in  std_logic                                        := '0';
-      eeprom_sda_i         : in  std_logic;
+      eeprom_sda_i         : in  std_logic                                        := '1';
      eeprom_sda_o         : out std_logic;
-      eeprom_scl_i         : in  std_logic;
+      eeprom_scl_i         : in  std_logic                                        := '1';
      eeprom_scl_o         : out std_logic;
      onewire_i            : in  std_logic;
      onewire_oen_o        : out std_logic;

--- a/board/spec/xwrc_board_spec.vhd
+++ b/board/spec/xwrc_board_spec.vhd
@@ -420,6 +420,8 @@ begin  -- architecture struct
      g_simulation                => g_simulation,
      g_with_external_clock_input => g_with_external_clock_input,
      g_board_name                => "SPEC",
+      g_flash_secsz_kb            => 64,         -- sector size for M25P32
+      g_flash_sdbfs_baddr         => 16#2e0000#, -- sdbfs after multiboot bitstream
      g_phys_uart                 => TRUE,
      g_virtual_uart              => TRUE,
      g_aux_clks                  => g_aux_clks,

--- a/board/svec/wr_svec_pkg.vhd
+++ b/board/svec/wr_svec_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for SVEC package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_svec_pkg.vhd
+-- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-02-16
+-- Last update: 2017-07-04
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;

@@ -59,9 +93,9 @@ package wr_svec_pkg is
      sfp_tx_fault_i       : in  std_logic                                        := '0';
      sfp_tx_disable_o     : out std_logic;
      sfp_los_i            : in  std_logic                                        := '0';
-      eeprom_sda_i         : in  std_logic;
+      eeprom_sda_i         : in  std_logic                                        := '1';
      eeprom_sda_o         : out std_logic;
-      eeprom_scl_i         : in  std_logic;
+      eeprom_scl_i         : in  std_logic                                        := '1';
      eeprom_scl_o         : out std_logic;
      onewire_i            : in  std_logic;
      onewire_oen_o        : out std_logic;

--- a/board/svec/xwrc_board_svec.vhd
+++ b/board/svec/xwrc_board_svec.vhd
@@ -426,6 +426,8 @@ begin  -- architecture struct
      g_simulation                => g_simulation,
      g_with_external_clock_input => g_with_external_clock_input,
      g_board_name                => "SVEC",
+      g_flash_secsz_kb            => 256,        -- default for M25P128
+      g_flash_sdbfs_baddr         => 16#600000#, -- default for M25P128
      g_phys_uart                 => TRUE,
      g_virtual_uart              => TRUE,
      g_aux_clks                  => g_aux_clks,

--- a/board/vfchd/wr_vfchd_pkg.vhd
+++ b/board/vfchd/wr_vfchd_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for VFC-HD package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_vfchd_pkg.vhd
+-- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2016-07-26
+-- Last update: 2017-07-04
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2016-2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/general-cores @ 5205d975
+++ b/general-cores @ 5205d975
-Subproject commit 96295346bb6742b03b43930a4e8a5c73028f4572
+Subproject commit 5205d9754b1e0887df5914a47f8aa745e4f3c2fe
--- a/gn4124-core @ 9b9625bb
+++ b/gn4124-core @ 9b9625bb
-Subproject commit 2710742b178f8ba9a4c2d163c1bf67c99e267102
+Subproject commit 9b9625bb4270114266cd357f199d649f3d799f04
--- a/vme64x-core @ fa34d06e
+++ b/vme64x-core @ fa34d06e
-Subproject commit 6994f35bdbe717f3df69e7226ee35d507ea87f5f
+Subproject commit fa34d06e35ca0bfad8eac24aa51713e81639da64
--- a/modules/fabric/wr_fabric_pkg.vhd
+++ b/modules/fabric/wr_fabric_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Packet Fabric package
+-- Project    : WR Cores Collection
+-------------------------------------------------------------------------------
+-- File       : wr_fabric_pkg.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use work.wishbone_pkg.all;

--- a/modules/fabric/xwb_fabric_source.vhd
+++ b/modules/fabric/xwb_fabric_source.vhd
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Packet Fabric buffered packet source
+-- Project    : WR Cores Collection
+-------------------------------------------------------------------------------
+-- File       : xwb_fabric_source.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2012-01-16
+-- Last update: 2012-01-22
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/fabric/xwrf_mux.vhd
+++ b/modules/fabric/xwrf_mux.vhd
@@ -2,7 +2,7 @@
 -- Title      : Simple Pipelined Wishbone MUX/DEMUX for WRPC
 -- Project    : WhiteRabbit
 -------------------------------------------------------------------------------
-- File       : wrf_mux.vhd
+-- File       : xwrf_mux.vhd
 -- Author     : Grzegorz Daniluk
 -- Company    : CERN BE-CO-HT
 -- Created    : 2011-08-11
@@ -18,7 +18,24 @@
 -- has to be forwarded to Mini-NIC (if it is the PTP message) or to the 
 -- external interface (others).
 -------------------------------------------------------------------------------
-- Copyright (c) 2012 Grzegorz Daniluk
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/fabric/xwrf_reg.vhd
+++ b/modules/fabric/xwrf_reg.vhd
+-------------------------------------------------------------------------------
+-- Title      : Simple WB Fabric register
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwrf_mux.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Copyright (c) 2014 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/timing/hpll_period_detect.vhd
+++ b/modules/timing/hpll_period_detect.vhd
@@ -18,7 +18,7 @@
 -- - positive when clk_fbck_i is slower than selected frequency setpoint
 -- - negative when clk_fbck_i is faster than selected frequency setpoint
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/timing/multi_dmtd_with_deglitcher.vhd
+++ b/modules/timing/multi_dmtd_with_deglitcher.vhd
+-------------------------------------------------------------------------------
+-- Title      : Multi Digital DMTD Phase Measurement Unit
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : multi_dmtd_with_deglitcher.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.NUMERIC_STD.all;

--- a/modules/wr_dacs/spec_serial_dac.vhd
+++ b/modules/wr_dacs/spec_serial_dac.vhd
 -------------------------------------------------------------------------------
 -- Title      : Serial DAC interface
-- Project    : White Rabbit Switch
+-- Project    : White Rabbit
 -------------------------------------------------------------------------------
-- File       : serial_dac.vhd
+-- File       : spec_serial_dac.vhd
 -- Author     : paas, slayer
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-02-25
@@ -10,10 +10,29 @@
 -- Platform   : fpga-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible) 
+-- Description: The dac unit provides an interface to a 16 bit serial Digital
+-- to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible) 
 --
 -------------------------------------------------------------------------------
+--
 -- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
 -------------------------------------------------------------------------------
 -- Revisions  :1
 -- Date        Version  Author  Description

--- a/modules/wr_dacs/spec_serial_dac_arb.vhd
+++ b/modules/wr_dacs/spec_serial_dac_arb.vhd
+-------------------------------------------------------------------------------
+-- Title      : SPEC serial DAC interface with arbiter
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : spec_serial_dac.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Platform   : fpga-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/wr_endpoint/endpoint_pkg.vhd
+++ b/modules/wr_endpoint/endpoint_pkg.vhd
@@ -14,7 +14,7 @@
 -- structures and component declarations.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+-- Copyright (c) 2011-2017 CERN / BE-CO-HT
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/modules/wr_endpoint/ep_crc32_pkg.vhd
+++ b/modules/wr_endpoint/ep_crc32_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : CRC32 package
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_crc32_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2013 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/wr_endpoint/ep_leds_controller.vhd
+++ b/modules/wr_endpoint/ep_leds_controller.vhd
+-------------------------------------------------------------------------------
+-- Title      : Endpoint LEDs controller
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_leds_controller.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+++ b/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ep_pcs_tbi_mdio_wb.vhd
 -- Author         : auto-generated by wbgen2 from pcs_regs.wb
-- Created        : Thu Aug  6 09:50:34 2015
+-- Created        : Wed Aug 16 22:43:42 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
@@ -120,22 +120,12 @@ signal mdio_ectrl_tx_prbs_sel_int               : std_logic_vector(2 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
-signal bwsel_reg                                : std_logic_vector(3 downto 0);
 signal rwaddr_reg                               : std_logic_vector(4 downto 0);
 signal ack_in_progress                          : std_logic      ;
-signal wr_int                                   : std_logic      ;
-signal rd_int                                   : std_logic      ;
-signal allones                                  : std_logic_vector(31 downto 0);
-signal allzeros                                 : std_logic_vector(31 downto 0);

 begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
  wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
  process (clk_sys_i, rst_n_i)

--- a/modules/wr_endpoint/ep_registers_pkg.vhd
+++ b/modules/wr_endpoint/ep_registers_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ep_registers_pkg.vhd
 -- Author         : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created        : Thu Aug  6 15:57:28 2015
+-- Created        : Wed Aug 16 22:43:41 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb

--- a/modules/wr_endpoint/ep_rtu_header_extract.vhd
+++ b/modules/wr_endpoint/ep_rtu_header_extract.vhd
+-------------------------------------------------------------------------------
+-- Title      : RTU header extract
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rtu_header_extract.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use work.endpoint_private_pkg.all;

--- a/modules/wr_endpoint/ep_rx_crc_size_check.vhd
+++ b/modules/wr_endpoint/ep_rx_crc_size_check.vhd
+-------------------------------------------------------------------------------
+-- Title      : Rx CRC checker
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_crc_size_check.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wr_endpoint/ep_rx_early_address_match.vhd
+++ b/modules/wr_endpoint/ep_rx_early_address_match.vhd
+-------------------------------------------------------------------------------
+-- Title      : Rx Early Address Match
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_early_address_match.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2015 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wr_endpoint/ep_rx_oob_insert.vhd
+++ b/modules/wr_endpoint/ep_rx_oob_insert.vhd
+-------------------------------------------------------------------------------
+-- Title      : RX OOB inserter
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_oob_insert.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
+++ b/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
@@ -17,7 +17,7 @@
 -- It also generates deterministic timestamping pulses for RXed packets.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2011-2017 Tomasz Wlostowski / CERN
+-- Copyright (c) 2011-2017 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
+++ b/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
@@ -17,7 +17,7 @@
 -- pulses for RXed packets.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009-2017 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009-2017 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
+++ b/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
+-------------------------------------------------------------------------------
+-- Title      : RX Status Register Inserter
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_status_reg_insert.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wr_endpoint/ep_rx_vlan_unit.vhd
+++ b/modules/wr_endpoint/ep_rx_vlan_unit.vhd
+-------------------------------------------------------------------------------
+-- Title      : RX VLAN unit
+-- Project    : White Rabbit 
+-------------------------------------------------------------------------------
+-- File       : ep_rx_vlan_unit.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2015 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wr_endpoint/ep_rx_wb_master.vhd
+++ b/modules/wr_endpoint/ep_rx_wb_master.vhd
--- a/modules/wr_endpoint/ep_sync_detect.vhd
+++ b/modules/wr_endpoint/ep_sync_detect.vhd
--- a/modules/wr_endpoint/ep_sync_detect_16bit.vhd
+++ b/modules/wr_endpoint/ep_sync_detect_16bit.vhd
--- a/modules/wr_endpoint/ep_timestamping_unit.vhd
+++ b/modules/wr_endpoint/ep_timestamping_unit.vhd
--- a/modules/wr_endpoint/ep_ts_counter.vhd
+++ b/modules/wr_endpoint/ep_ts_counter.vhd
--- a/modules/wr_endpoint/ep_tx_framer.vhd
+++ b/modules/wr_endpoint/ep_tx_framer.vhd
--- a/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+++ b/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
--- a/modules/wr_endpoint/ep_wishbone_controller.vhd
+++ b/modules/wr_endpoint/ep_wishbone_controller.vhd
--- a/modules/wr_mini_nic/minic_packet_buffer.vhd
+++ b/modules/wr_mini_nic/minic_packet_buffer.vhd
--- a/modules/wr_mini_nic/minic_wb_slave.vhd
+++ b/modules/wr_mini_nic/minic_wb_slave.vhd
--- a/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+++ b/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
--- a/modules/wr_mini_nic/wr_mini_nic.vhd
+++ b/modules/wr_mini_nic/wr_mini_nic.vhd
--- a/modules/wr_mini_nic/xwr_mini_nic.vhd
+++ b/modules/wr_mini_nic/xwr_mini_nic.vhd
--- a/modules/wr_pps_gen/pps_gen_regs.h
+++ b/modules/wr_pps_gen/pps_gen_regs.h
--- a/modules/wr_pps_gen/pps_gen_wb.vhd
+++ b/modules/wr_pps_gen/pps_gen_wb.vhd
--- a/modules/wr_pps_gen/wr_pps_gen.vhd
+++ b/modules/wr_pps_gen/wr_pps_gen.vhd
--- a/modules/wr_pps_gen/xwr_pps_gen.vhd
+++ b/modules/wr_pps_gen/xwr_pps_gen.vhd
--- a/modules/wr_softpll_ng/spll_aligner.vhd
+++ b/modules/wr_softpll_ng/spll_aligner.vhd
--- a/modules/wr_softpll_ng/spll_bangbang_pd.vhd
+++ b/modules/wr_softpll_ng/spll_bangbang_pd.vhd
--- a/modules/wr_softpll_ng/spll_period_detect.vhd
+++ b/modules/wr_softpll_ng/spll_period_detect.vhd
--- a/modules/wr_softpll_ng/spll_wb_slave.vhd
+++ b/modules/wr_softpll_ng/spll_wb_slave.vhd
--- a/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
+++ b/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
--- a/modules/wr_streamers/wr_streamers_wb.vhd
+++ b/modules/wr_streamers/wr_streamers_wb.vhd
--- a/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
+++ b/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
--- a/modules/wr_streamers/xtx_streamer.vhd
+++ b/modules/wr_streamers/xtx_streamer.vhd
--- a/modules/wr_tbi_phy/Manifest.py
+++ b/modules/wr_tbi_phy/Manifest.py
--- a/modules/wr_tbi_phy/wr_tbi_phy.vhd
+++ b/modules/wr_tbi_phy/wr_tbi_phy.vhd
--- a/modules/wrc_core/Manifest.py
+++ b/modules/wrc_core/Manifest.py
--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
--- a/modules/wrc_core/wrc_diags_pkg.vhd
+++ b/modules/wrc_core/wrc_diags_pkg.vhd
--- a/modules/wrc_core/wrc_diags_wb.vhd
+++ b/modules/wrc_core/wrc_diags_wb.vhd
--- a/modules/wrc_core/wrc_dpram.vhd
+++ b/modules/wrc_core/wrc_dpram.vhd
--- a/modules/wrc_core/wrc_periph.vhd
+++ b/modules/wrc_core/wrc_periph.vhd
--- a/modules/wrc_core/wrc_syscon_pkg.vhd
+++ b/modules/wrc_core/wrc_syscon_pkg.vhd
--- a/modules/wrc_core/wrc_syscon_regs.h
+++ b/modules/wrc_core/wrc_syscon_regs.h
--- a/modules/wrc_core/wrc_syscon_wb.vhd
+++ b/modules/wrc_core/wrc_syscon_wb.vhd
--- a/modules/wrc_core/wrc_syscon_wb.wb
+++ b/modules/wrc_core/wrc_syscon_wb.wb
--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
--- a/modules/wrc_core/xwr_syscon_wb.vhd
+++ b/modules/wrc_core/xwr_syscon_wb.vhd
--- a/platform/altera/wr_altera_pkg.vhd
+++ b/platform/altera/wr_altera_pkg.vhd
--- a/platform/xilinx/wr_gtp_phy/Manifest.py
+++ b/platform/xilinx/wr_gtp_phy/Manifest.py
--- a/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gt.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gt.vhd
--- a/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gtrxreset_seq.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gtrxreset_seq.vhd
--- a/top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_62_5m.vhd
+++ b/top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_62_5m.vhd
--- a/platform/xilinx/wr_gtp_phy/family7-gth/wr_gth_phy_family7.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gth/wr_gth_phy_family7.vhd
--- a/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
--- a/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
--- a/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
--- a/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
--- a/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
--- a/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+++ b/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
--- a/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
+++ b/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
--- a/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
--- a/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
+++ b/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
--- a/platform/xilinx/wr_gtp_phy/gtx_reset.vhd
+++ b/platform/xilinx/wr_gtp_phy/gtx_reset.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
--- a/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd
--- a/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd
--- a/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/platform/xilinx/wr_xilinx_pkg.vhd
--- a/platform/xilinx/xwrc_platform_xilinx.vhd
+++ b/platform/xilinx/xwrc_platform_xilinx.vhd
--- a/sim/wrc_syscon_regs.vh
+++ b/sim/wrc_syscon_regs.vh
--- a/syn/clbv2_ref_design/Manifest.py
+++ b/syn/clbv2_ref_design/Manifest.py
--- a/syn/clbv2_ref_design/clbv2_wr_ref.xise
+++ b/syn/clbv2_ref_design/clbv2_wr_ref.xise
--- a/syn/clbv3_ref_design/Manifest.py
+++ b/syn/clbv3_ref_design/Manifest.py
--- a/syn/clbv3_ref_design/clbv3_wr_ref.xise.xise
+++ b/syn/clbv3_ref_design/clbv3_wr_ref.xise.xise
--- a/syn/fasec_ref_design/build.tcl
+++ b/syn/fasec_ref_design/build.tcl
--- a/syn/fasec_ref_design/fasec_ref_design.tcl
+++ b/syn/fasec_ref_design/fasec_ref_design.tcl
--- a/syn/spec_ref_design/Makefile
+++ b/syn/spec_ref_design/Makefile
--- a/syn/spec_ref_design/spec_wr_ref.xise
+++ b/syn/spec_ref_design/spec_wr_ref.xise
--- a/syn/svec_ref_design/Makefile
+++ b/syn/svec_ref_design/Makefile
--- a/syn/svec_ref_design/svec_wr_ref.xise
+++ b/syn/svec_ref_design/svec_wr_ref.xise
--- a/syn/vfchd_ref_design/quartus_preflow.tcl
+++ b/syn/vfchd_ref_design/quartus_preflow.tcl
--- a/syn/vfchd_ref_design/vfchd_wr_ref.qsf
+++ b/syn/vfchd_ref_design/vfchd_wr_ref.qsf
--- a/syn/wrc_board_fasec_ip/Manifest.py
+++ b/syn/wrc_board_fasec_ip/Manifest.py
--- a/syn/wrc_board_fasec_ip/README.txt
+++ b/syn/wrc_board_fasec_ip/README.txt
--- a/syn/wrc_board_fasec_ip/build.tcl
+++ b/syn/wrc_board_fasec_ip/build.tcl
--- a/syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl
+++ b/syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl
--- a/testbench/wr_endpoint/old_ep/old_ep_1000basex_pcs.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_1000basex_pcs.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_autonegotiation.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_autonegotiation.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_flow_control.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_flow_control.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_rmon_counters.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_rmon_counters.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_rx_buffer.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_rx_buffer.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_rx_deframer.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_rx_deframer.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_rx_pcs_tbi.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_rx_pcs_tbi.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_sync_detect.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_sync_detect.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_timestamping_unit.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_timestamping_unit.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_ts_counter.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_ts_counter.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_tx_framer.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_tx_framer.vhd
--- a/testbench/wr_endpoint/old_ep/old_ep_tx_pcs_tbi.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_tx_pcs_tbi.vhd
--- a/testbench/wr_endpoint/old_ep/old_wrsw_endpoint.vhd
+++ b/testbench/wr_endpoint/old_ep/old_wrsw_endpoint.vhd
--- a/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
+++ b/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
--- a/testbench/wrc_core/main.sv
+++ b/testbench/wrc_core/main.sv
--- a/top/clbv2_ref_design/Manifest.py
+++ b/top/clbv2_ref_design/Manifest.py
--- a/top/clbv2_ref_design/clbv2_wr_ref_top.bmm
+++ b/top/clbv2_ref_design/clbv2_wr_ref_top.bmm
--- a/top/clbv2_ref_design/clbv2_wr_ref_top.ucf
+++ b/top/clbv2_ref_design/clbv2_wr_ref_top.ucf
--- a/top/clbv2_ref_design/clbv2_wr_ref_top.vhd
+++ b/top/clbv2_ref_design/clbv2_wr_ref_top.vhd
--- a/top/clbv3_ref_design/Manifest.py
+++ b/top/clbv3_ref_design/Manifest.py
--- a/top/clbv3_ref_design/clbv3_wr_ref_top.bmm
+++ b/top/clbv3_ref_design/clbv3_wr_ref_top.bmm
--- a/top/clbv3_ref_design/clbv3_wr_ref_top.ucf
+++ b/top/clbv3_ref_design/clbv3_wr_ref_top.ucf
--- a/top/clbv3_ref_design/clbv3_wr_ref_top.vhd
+++ b/top/clbv3_ref_design/clbv3_wr_ref_top.vhd
--- a/top/fasec_ref_design/fasec_ref_design.xdc
+++ b/top/fasec_ref_design/fasec_ref_design.xdc
--- a/top/fasec_ref_design/system_top.tcl
+++ b/top/fasec_ref_design/system_top.tcl
--- a/top/kintex7_ref_design/wr_core_demo/kintex7_top.ucf
+++ b/top/kintex7_ref_design/wr_core_demo/kintex7_top.ucf
--- a/top/kintex7_ref_design/wr_core_demo/kintex7_top.vhd
+++ b/top/kintex7_ref_design/wr_core_demo/kintex7_top.vhd
--- a/top/kintex7_ref_design/wr_core_demo/spec_reset_gen.vhd
+++ b/top/kintex7_ref_design/wr_core_demo/spec_reset_gen.vhd
--- a/top/spec_1_1/wr_streamers_demo/spec_top.vhd
+++ b/top/spec_1_1/wr_streamers_demo/spec_top.vhd
--- a/top/svec_ref_design/svec_wr_ref_top.ucf
+++ b/top/svec_ref_design/svec_wr_ref_top.ucf
--- a/top/svec_ref_design/svec_wr_ref_top.vhd
+++ b/top/svec_ref_design/svec_wr_ref_top.vhd
--- a/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
+++ b/top/vfchd_ref_design/vfchd_wr_ref_top.vhd