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White Rabbit core collection
Commit 6c060087 authored by Pascal Bos's avatar Pascal Bos
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removed ps_uart

parent e6b16736
Pipeline #790 failed with stage
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    board/spidr4/wr_spidr4_pkg.vhd
    View file @ 6c060087
    ......@@ -151,6 +151,7 @@ package wr_spidr4_pkg is
    pps_led_o : out std_logic;
    link_ok_o : out std_logic);
    end component xwrc_board_spidr4;
    component zynq_subsystem is
    port (
    ARESETN : out STD_LOGIC_VECTOR ( 0 to 0 );
    ......@@ -210,9 +211,7 @@ package wr_spidr4_pkg is
    SPI_0_0_ss_o : out STD_LOGIC;
    SPI_0_0_ss_t : out STD_LOGIC;
    SYS_CLK_20MHz : out STD_LOGIC;
    SYS_CLK_40MHz : out STD_LOGIC;
    UART_0_0_rxd : in STD_LOGIC;
    UART_0_0_txd : out STD_LOGIC
    SYS_CLK_40MHz : out STD_LOGIC
    );
    end component zynq_subsystem;
    ......
    top/spidr4_ref_design/spidr4_wr_ref_top.vhd
    View file @ 6c060087
    ......@@ -114,8 +114,8 @@ entity spidr4_wr_ref_top is
    -- UART
    ---------------------------------------------------------------------------
    -- uart_rxd_i : in std_logic;
    -- uart_txd_o : out std_logic;
    uart_rxd_i : in std_logic;
    uart_txd_o : out std_logic;
    ---------------------------------------------------------------------------
    -- EEPROM interface
    ......@@ -329,9 +329,7 @@ begin -- architecture top
    SPI_0_0_ss2_o => PS_SPI_0_0_ss2_o,
    SPI_0_0_ss_i => '1',
    SPI_0_0_ss_o => PS_SPI_0_0_ss_o,
    SPI_0_0_ss_t => PS_SPI_0_0_ss_t,
    uart_0_0_rxd => PS_UART_rxd,
    uart_0_0_txd => PS_UART_txd
    SPI_0_0_ss_t => PS_SPI_0_0_ss_t
    );
    -----------------------------------------------------------------------------
    ......@@ -382,8 +380,8 @@ begin -- architecture top
    onewire_i => '1', -- No onewire, Unique ID now via
    onewire_oen_o => open, -- 24AA025EU48 (I2C Addr 1010.001x)
    -- Uart
    uart_rxd_i => PS_UART_rxd,
    uart_txd_o => PS_UART_txd,
    uart_rxd_i => uart_rxd_i,
    uart_txd_o => uart_txd_o,
    -- Wishbone
    --wb_slave_i => wb_master_o,
    ......
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