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White Rabbit core collection
Commit 6858fe4c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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CI: Adding Quartus synthesis for VFC-HD

parent ef91f1de
Pipeline #432 failed with stages
        in 26 minutes and 56 seconds
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        .gitlab-ci.yml
        View file @ 6858fe4c
        ......@@ -24,6 +24,9 @@ job_wrpc_sim:
        - schedules
        script:
        - source ~/setup_modelsim.sh
        - cp /opt/compiled_libs_ise14.7/modelsim.ini testbench/wr_minic
        - cp /opt/compiled_libs_ise14.7/modelsim.ini testbench/wrc_core
        - cp /opt/compiled_libs_ise14.7/modelsim.ini testbench/wr_streamers/streamers_multi_test
        - cd testbench && make
        artifacts:
        name: WRPC_SIM_CI_$CI_JOB_ID
        ......@@ -84,3 +87,19 @@ job_wrpc_pxie_fmc:
        - syn/pxie_fmc_ref_design/*.rpt
        - syn/pxie_fmc_ref_design/*.dcp
        - syn/pxie_fmc_ref_design/*.bit
        job_wrpc_vfchd:
        stage: wrpc_syn
        tags:
        - quartus
        - "16.0"
        only:
        - schedules
        script:
        - source ~/setup_intel.sh
        - cd syn/vfchd_ref_design
        - hdlmake makefile; make
        artifacts:
        name: WRPC_VFCHD_CI_$CI_JOB_ID
        paths:
        - syn/vfchd_ref_design/*.bin
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