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White Rabbit core collection
Commit 66ee503d authored by Peter Jansweijer's avatar Peter Jansweijer Committed by Grzegorz Daniluk
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kintex-7 reference design updated such that it can do grand-master mode (putting… 

kintex-7 reference design updated such that it can do grand-master mode (putting the DIO card on the CLB FMC connector and inputting 10 MHz and PPS).
parent fd467fd2
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top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_125m.vhd → top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_62_5m.vhd
View file @ 66ee503d
-- file: ext_pll_10_to_125m.vhd
-- -- file: ext_pll_10_to_62_5m.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
......@@ -55,12 +55,12 @@
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___125.000______0.000______50.0_____1014.602____150.000
-- CLK_OUT1____62.500______0.000______50.0______659.593____883.386
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________10.000____________0.010
-- __primary__________10.000____________0.005
library ieee;
use ieee.std_logic_1164.all;
......@@ -71,7 +71,7 @@ use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ext_pll_10_to_125m is
entity ext_pll_10_to_62_5m is
port
(-- Clock in ports
clk_ext_i : in std_logic;
......@@ -81,19 +81,19 @@ port
rst_a_i : in std_logic;
locked_o : out std_logic
);
end ext_pll_10_to_125m;
end ext_pll_10_to_62_5m;
architecture xilinx of ext_pll_10_to_125m is
architecture xilinx of ext_pll_10_to_62_5m is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=true,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=100.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_62_5m,clk_wiz_v3_6,{component_name=ext_pll_10_to_62_5m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=100.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
-- signal clkfbout : std_logic;
-- signal locked_internal : std_logic;
-- signal status_internal : std_logic_vector(7 downto 0);
begin
......@@ -110,7 +110,7 @@ begin
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "LOW",
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
......@@ -118,7 +118,7 @@ begin
CLKFBOUT_MULT_F => 62.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 5.000,
CLKOUT0_DIVIDE_F => 10.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
......@@ -140,7 +140,7 @@ begin
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfbout,
CLKFBIN => clkfb,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
......@@ -159,7 +159,7 @@ begin
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
LOCKED => locked_o,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
......
top/kintex7_ref_design/wr_core_demo/kintex7_top.ucf
View file @ 66ee503d
......@@ -67,6 +67,57 @@ NET "sfp_txp_o" LOC = A4; #Bank 116
NET "sfp_txn_o" LOC = A3; #Bank 116
NET "sfp_rxp_i" LOC = B6; #Bank 116
NET "sfp_rxn_i" LOC = B5; #Bank 116
########################################################
## Pin definitions for FmcDio5chttl + CLB V2.2.1 ##
########################################################
# DIO outputs
NET "dio_p_o[4]" LOC = N18 | IOSTANDARD=LVDS_25;
NET "dio_n_o[4]" LOC = M19 | IOSTANDARD=LVDS_25;
NET "dio_p_o[3]" LOC = U19 | IOSTANDARD=LVDS_25;
NET "dio_n_o[3]" LOC = U20 | IOSTANDARD=LVDS_25;
NET "dio_p_o[2]" LOC = W20 | IOSTANDARD=LVDS_25;
NET "dio_n_o[2]" LOC = Y21 | IOSTANDARD=LVDS_25;
NET "dio_p_o[1]" LOC = M21 | IOSTANDARD=LVDS_25;
NET "dio_n_o[1]" LOC = M22 | IOSTANDARD=LVDS_25;
NET "dio_p_o[0]" LOC = N19 | IOSTANDARD=LVDS_25;
NET "dio_n_o[0]" LOC = M20 | IOSTANDARD=LVDS_25;
NET "dio_sdn_n_o" LOC = AA25 | IOSTANDARD=LVCMOS25;
NET "dio_sdn_ck_n_o" LOC = AF24 | IOSTANDARD=LVCMOS25;
# DIO output enable/termination enable
NET "dio_oe_n_o[4]" LOC = AE22 | IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[3]" LOC = U26 | IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[2]" LOC = AB25 | IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[1]" LOC = N23 | IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[0]" LOC = P24 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[4]" LOC = P25 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[3]" LOC = R25 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[2]" LOC = AF22 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[1]" LOC = AF25 | IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[0]" LOC = N24 | IOSTANDARD=LVCMOS25;
NET "dio_onewire_b" LOC = K26 | IOSTANDARD=LVCMOS25;
# DIO inputs
NET "dio_clk_p_i" LOC = Y22 | IOSTANDARD=LVDS_25;
NET "dio_clk_n_i" LOC = AA22 | IOSTANDARD=LVDS_25;
NET "dio_p_i[4]" LOC = N21 | IOSTANDARD=LVDS_25;
NET "dio_n_i[4]" LOC = N22 | IOSTANDARD=LVDS_25;
NET "dio_p_i[3]" LOC = P16 | IOSTANDARD=LVDS_25;
NET "dio_n_i[3]" LOC = N17 | IOSTANDARD=LVDS_25;
NET "dio_p_i[2]" LOC = AB26 | IOSTANDARD=LVDS_25;
NET "dio_n_i[2]" LOC = AC26 | IOSTANDARD=LVDS_25;
NET "dio_p_i[1]" LOC = K20 | IOSTANDARD=LVDS_25;
NET "dio_n_i[1]" LOC = J20 | IOSTANDARD=LVDS_25;
NET "dio_p_i[0]" LOC = P19 | IOSTANDARD=LVDS_25;
NET "dio_n_i[0]" LOC = P20 | IOSTANDARD=LVDS_25;
NET "dio_led_top_o" LOC = R21 | IOSTANDARD=LVCMOS25;
NET "dio_led_bot_o" LOC = P21 | IOSTANDARD=LVCMOS25;
########################################################
####################################
# Note that the phy_rst_o originates from the clk_sys domain. Synchronization is not needed
......
top/kintex7_ref_design/wr_core_demo/kintex7_top.vhd
View file @ 66ee503d
......@@ -76,18 +76,18 @@ entity kintex7_top is
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
--dio_n_i : in std_logic_vector(4 downto 0);
--dio_p_i : in std_logic_vector(4 downto 0);
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
--dio_n_o : out std_logic_vector(4 downto 0);
--dio_p_o : out std_logic_vector(4 downto 0);
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
--dio_oe_n_o : out std_logic_vector(4 downto 0);
--dio_term_en_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_onewire_b : inout std_logic;
--dio_sdn_n_o : out std_logic;
--dio_sdn_ck_n_o : out std_logic;
dio_onewire_b : inout std_logic;
dio_sdn_n_o : out std_logic;
dio_sdn_ck_n_o : out std_logic;
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic;
......@@ -121,13 +121,13 @@ architecture structure of kintex7_top is
rst_n_o : out std_logic);
end component spec_reset_gen;
component ext_pll_10_to_125m
component ext_pll_10_to_62_5m
port (
clk_ext_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic;
locked_o : out std_logic);
end component ext_pll_10_to_125m;
end component ext_pll_10_to_62_5m;
component wr_gtx_phy_kintex7
generic(
......@@ -218,9 +218,9 @@ architecture structure of kintex7_top is
signal phy_prbs_sel : std_logic_vector(2 downto 0);
signal phy_rdy : std_logic;
--signal dio_in : std_logic_vector(4 downto 0);
--signal dio_out : std_logic_vector(4 downto 0);
--signal dio_clk : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_clk : std_logic;
signal local_reset_n : std_logic;
......@@ -249,8 +249,8 @@ architecture structure of kintex7_top is
signal ext_pll_reset : std_logic;
signal clk_ext : std_ulogic;
signal clk_ext_mul : std_logic;
signal clk_ext_mul_locked : std_logic;
--signal clk_ref_div2 : std_logic;
signal clk_ext_mul_locked : std_logic;
-- signal clk_ref_div2 : std_logic;
signal dac_cs_n_o : std_logic_vector(1 downto 0);
signal button1_n_i : std_logic;
......@@ -260,7 +260,7 @@ begin
local_reset <= not local_reset_n;
button1_n_i <= not button1_i;
U_Ext_PLL: ext_pll_10_to_125m
U_Ext_PLL: ext_pll_10_to_62_5m
port map(
clk_ext_i => clk_ext,
clk_ext_mul_o => clk_ext_mul,
......@@ -515,7 +515,7 @@ begin
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_locked_i => clk_ext_mul_locked,
clk_ext_i => clk_ext,
pps_ext_i => pps_ext_i,
pps_ext_i => dio_in(3),
rst_n_i => local_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1_o,
dac_hpll_data_o => dac_hpll_data_o,
......@@ -638,23 +638,23 @@ begin
pulse_i => pps_led,
extended_o => dio_led_top_o);
-- gen_dio_iobufs : for i in 0 to 4 generate
-- U_ibuf : IBUFDS
-- generic map (
-- DIFF_TERM => true)
-- port map (
-- O => dio_in(i),
-- I => dio_p_i(i),
-- IB => dio_n_i(i)
-- );
--
-- U_obuf : OBUFDS
-- port map (
-- I => dio_out(i),
-- O => dio_p_o(i),
-- OB => dio_n_o(i)
-- );
-- end generate gen_dio_iobufs;
gen_dio_iobufs : for i in 0 to 4 generate
U_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_in(i),
I => dio_p_i(i),
IB => dio_n_i(i)
);
U_obuf : OBUFDS
port map (
I => dio_out(i),
O => dio_p_o(i),
OB => dio_n_o(i)
);
end generate gen_dio_iobufs;
U_input_buffer : IBUFGDS
generic map (
......@@ -682,9 +682,22 @@ begin
thermo_id <= '0' when owr_en(0) = '1' else 'Z';
owr_i(0) <= thermo_id;
dio_out(0) <= pps;
dio_out(1) <= '0';
dio_oe_n_o(0) <= '0';
dio_oe_n_o(2 downto 1) <= (others => '0');
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
dio_onewire_b <= '0' when owr_en(1) = '1' else 'Z';
owr_i(1) <= dio_onewire_b;
dio_term_en_o <= (others => '0');
dio_sdn_ck_n_o <= '1';
dio_sdn_n_o <= '1';
------------------------------------------------------------------------------
-- OE test output (KM3NeT CLB specific)
------------------------------------------------------------------------------
......
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