Commit 654f0387 authored by Maciej Lipinski's avatar Maciej Lipinski

[VXS support] added top level with reference design

parent 027898c7
fetchto = "../../ip_cores"
files = [
"vxs_wr_ref_top.vhd",
"vxs_wr_ref_top.ucf"
]
modules = {
"local" : [
"../../",
"../../board/vxs",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
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################################################################################
# NOTE by Maciej Lipinski
# This UCF file was inherited from the EDA-02299-V2-VXS-Switch project
# 1) first all commeted lines were removed
# 2) then all unneeded lines were commented out)
# 3) then some stuff was added
#
################################################################################
NET "VCXO_MHZ20" CLOCK_DEDICATED_ROUTE = FALSE;
# Pinning for GTP122 tile
# INST "C456/X0Y0_GTPDual/gtp_dual_i" LOC = GTP_DUAL_X0Y0;
# INST "C457/IBUFGDS_inst" LOC = BUFDS_X0Y0;
# NET "FPGA2VXS0_N" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS0_N" LOC = AL2;
# NET "FPGA2VXS0_P" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS0_P" LOC = AK2;
# NET "FPGA2VXS1_N" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS1_N" LOC = AN3;
# NET "FPGA2VXS1_P" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS1_P" LOC = AN4;
# NET "GTP122_CLK_N" LOC = AL4;
# NET "GTP122_CLK_P" LOC = AL5;
# NET "GTP122_CLK_N" IOSTANDARD = LVPECL_25;
# NET "GTP122_CLK_P" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA0_N" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA0_N" LOC = AM1;
# NET "VXS2FPGA0_P" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA0_P" LOC = AL1;
# NET "VXS2FPGA1_N" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA1_N" LOC = AP2;
# NET "VXS2FPGA1_P" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA1_P" LOC = AP3;
# Pinning for GTP118 tile (Added for V2)
#INST "C227/U_GTP_TILE_INST/gtp_dual_i" LOC = GTP_DUAL_X0Y1;
#INST "GTP118_CLK_IBUFGDS/IBUFGDS_inst" LOC = BUFDS_X0Y1;
NET "FPGA2SFP_N" IOSTANDARD = LVPECL_25;
NET "FPGA2SFP_N" LOC = AH2;
NET "FPGA2SFP_P" IOSTANDARD = LVPECL_25;
NET "FPGA2SFP_P" LOC = AJ2;
# NET "FPGA2VXS2_N" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS2_N" LOC = AE2;
# NET "FPGA2VXS2_P" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS2_P" LOC = AD2;
NET "GTP118_CLK_N" LOC = AF3;
NET "GTP118_CLK_P" LOC = AF4;
NET "GTP118_CLK_N" IOSTANDARD = LVPECL_25;
NET "GTP118_CLK_P" IOSTANDARD = LVPECL_25;
NET "SFP2FPGA_N" IOSTANDARD = LVPECL_25;
NET "SFP2FPGA_N" LOC = AG1;
NET "SFP2FPGA_P" IOSTANDARD = LVPECL_25;
NET "SFP2FPGA_P" LOC = AH1;
# NET "VXS2FPGA2_N" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA2_N" LOC = AF1;
# NET "VXS2FPGA2_P" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA2_P" LOC = AE1;
# Clocking
# NET "FPGA_MHZ100_N" LOC = AG16;
# NET "FPGA_MHZ100_P" LOC = AH17;
# NET "FPGA_MHZ100_N" IOSTANDARD = LVDS_25;
# NET "FPGA_MHZ100_P" IOSTANDARD = LVDS_25;
# NET "FPGA_MHZ200_N" LOC = AG15;
# NET "FPGA_MHZ200_P" LOC = AH15;
# NET "FPGA_MHZ200_N" IOSTANDARD = LVPECL_25;
# NET "FPGA_MHZ200_P" IOSTANDARD = LVPECL_25;
# NET "FPGA_MHZ50_N" LOC = AG17;
# NET "FPGA_MHZ50_P" LOC = AH18;
# NET "FPGA_MHZ50_N" IOSTANDARD = LVDS_25;
# NET "FPGA_MHZ50_P" IOSTANDARD = LVDS_25;
# NET "RF_CLK_FPGA_N" LOC = AG13;
# NET "RF_CLK_FPGA_P" LOC = AH12;
# NET "RF_CLK_FPGA_N" IOSTANDARD = LVPECL_25;
# NET "RF_CLK_FPGA_P" IOSTANDARD = LVPECL_25;
# NET "TAG_FPGA_N" LOC = AH13;
# NET "TAG_FPGA_P" LOC = AH14;
# NET "TAG_FPGA_N" IOSTANDARD = LVPECL_25;
# NET "TAG_FPGA_P" IOSTANDARD = LVPECL_25;
NET "VCXO_MHZ125_N" LOC = AH19;
NET "VCXO_MHZ125_P" LOC = AH20;
NET "VCXO_MHZ125_N" IOSTANDARD = LVPECL_25;
NET "VCXO_MHZ125_P" IOSTANDARD = LVPECL_25;
NET "VCXO_MHZ20" IOSTANDARD = LVCMOS33;
NET "VCXO_MHZ20" LOC = H20;
# General I/O
# NET "ACE_TCK_O" IOSTANDARD = LVCMOS33;
# NET "ACE_TCK_O" LOC = AN33;
# NET "ACE_TDI_O" IOSTANDARD = LVCMOS33;
# NET "ACE_TDI_O" LOC = AN34;
NET "ACE_TDO_I" IOSTANDARD = LVCMOS33;
NET "ACE_TDO_I" LOC = AM32;
# NET "ACE_TMS_O" IOSTANDARD = LVCMOS33;
# NET "ACE_TMS_O" LOC = AN32;
NET "DAC_PLL125_SYNC_N" IOSTANDARD = LVCMOS33;
NET "DAC_PLL125_SYNC_N" LOC = AM13;
NET "DAC_PLL20_SYNC_N" IOSTANDARD = LVCMOS33;
NET "DAC_PLL20_SYNC_N" LOC = AN13;
NET "DAC_PLL_DIN" IOSTANDARD = LVCMOS33;
NET "DAC_PLL_DIN" LOC = AM12;
NET "DAC_PLL_SCLK" IOSTANDARD = LVCMOS33;
NET "DAC_PLL_SCLK" LOC = AL11;
NET "DQ" IOSTANDARD = LVCMOS33;
NET "DQ" LOC = L4;
# NET "FPGA_IO_OUT2" IOSTANDARD = LVCMOS33;
# NET "FPGA_IO_OUT2" LOC = AK9;
NET "FPGA_IO_OUT1" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_OUT1" LOC = AK8;
NET "FP_JTAG_ENA_N" IOSTANDARD = LVCMOS33;
NET "FP_JTAG_ENA_N" LOC = AP32;
NET "FRAMCS_N" IOSTANDARD = LVCMOS33;
NET "FRAMCS_N" LOC = W34;
NET "FRAMMISO" IOSTANDARD = LVCMOS33;
NET "FRAMMISO" LOC = V33;
NET "FRAMMOSI" IOSTANDARD = LVCMOS33;
NET "FRAMMOSI" LOC = V32;
NET "FRAMSCLK" IOSTANDARD = LVCMOS33;
NET "FRAMSCLK" LOC = Y32;
NET "FRAMWPDIS" IOSTANDARD = LVCMOS33;
NET "FRAMWPDIS" LOC = W32;
NET "FRAMWP_N" IOSTANDARD = LVCMOS33;
NET "FRAMWP_N" LOC = V34;
NET "GAP_N" IOSTANDARD = LVCMOS33;
NET "GAP_N" LOC = C34;
NET "GA_N[0]" IOSTANDARD = LVCMOS33;
NET "GA_N[0]" LOC = C33;
NET "GA_N[1]" IOSTANDARD = LVCMOS33;
NET "GA_N[1]" LOC = B33;
NET "GA_N[2]" IOSTANDARD = LVCMOS33;
NET "GA_N[2]" LOC = B32;
NET "GA_N[3]" IOSTANDARD = LVCMOS33;
NET "GA_N[3]" LOC = C32;
NET "GA_N[4]" IOSTANDARD = LVCMOS33;
NET "GA_N[4]" LOC = D32;
NET "HWVERSION[0]" IOSTANDARD = LVCMOS33;
NET "HWVERSION[0]" LOC = AK7;
NET "HWVERSION[1]" IOSTANDARD = LVCMOS33;
NET "HWVERSION[1]" LOC = AJ7;
NET "HWVERSION[2]" IOSTANDARD = LVCMOS33;
NET "HWVERSION[2]" LOC = AH7;
NET "HWVERSION[3]" IOSTANDARD = LVCMOS33;
NET "HWVERSION[3]" LOC = AG7;
# NET "KEEPER" IOSTANDARD = LVCMOS33;
# NET "KEEPER" LOC = T6;
NET "LED_CLK_G" IOSTANDARD = LVCMOS33;
NET "LED_CLK_G" LOC = AJ31;
NET "LED_CLK_R" IOSTANDARD = LVCMOS33;
NET "LED_CLK_R" LOC = AK31;
NET "LED_SFP_SCL" IOSTANDARD = LVCMOS33;
NET "LED_SFP_SCL" LOC = AB33;
NET "LED_SFP_SDA" IOSTANDARD = LVCMOS33;
NET "LED_SFP_SDA" LOC = AC33;
# NET "LED_SPARE_G" IOSTANDARD = LVCMOS33;
# NET "LED_SPARE_G" LOC = AH30;
# NET "LED_SPARE_R" IOSTANDARD = LVCMOS33;
# NET "LED_SPARE_R" LOC = AJ30;
NET "POR" IOSTANDARD = LVCMOS33;
NET "POR" LOC = AG23;
# NET "POWERDOWN" IOSTANDARD = LVCMOS33;
# NET "POWERDOWN" LOC = E6;
NET "PP10_SCL" IOSTANDARD = LVCMOS33;
NET "PP10_SCL" LOC = L34;
NET "PP10_SDA" IOSTANDARD = LVCMOS33;
NET "PP10_SDA" LOC = T33;
NET "PP11_SCL" IOSTANDARD = LVCMOS33;
NET "PP11_SCL" LOC = R34;
NET "PP11_SDA" IOSTANDARD = LVCMOS33;
NET "PP11_SDA" LOC = R33;
NET "PP12_SCL" IOSTANDARD = LVCMOS33;
NET "PP12_SCL" LOC = R32;
NET "PP12_SDA" IOSTANDARD = LVCMOS33;
NET "PP12_SDA" LOC = T34;
# NET "PP1_SCL_I" IOSTANDARD = LVCMOS33;
# NET "PP1_SCL_I" LOC = J34;
# NET "PP1_SCL_O_N" IOSTANDARD = LVCMOS33;
# NET "PP1_SCL_O_N" LOC = H34;
NET "PP1_SDA_I" IOSTANDARD = LVCMOS33;
NET "PP1_SDA_I" LOC = H33;
# NET "PP1_SDA_O_N" IOSTANDARD = LVCMOS33;
# NET "PP1_SDA_O_N" LOC = J32;
NET "PP2_SCL" IOSTANDARD = LVCMOS33;
NET "PP2_SCL" LOC = H32;
NET "PP2_SDA" IOSTANDARD = LVCMOS33;
NET "PP2_SDA" LOC = K34;
NET "PP3_SCL" IOSTANDARD = LVCMOS33;
NET "PP3_SCL" LOC = G33;
NET "PP3_SDA" IOSTANDARD = LVCMOS33;
NET "PP3_SDA" LOC = G32;
NET "PP4_SCL" IOSTANDARD = LVCMOS33;
NET "PP4_SCL" LOC = K32;
NET "PP4_SDA" IOSTANDARD = LVCMOS33;
NET "PP4_SDA" LOC = K33;
NET "PP5_SCL" IOSTANDARD = LVCMOS33;
NET "PP5_SCL" LOC = F34;
NET "PP5_SDA" IOSTANDARD = LVCMOS33;
NET "PP5_SDA" LOC = F33;
NET "PP6_SCL" IOSTANDARD = LVCMOS33;
NET "PP6_SCL" LOC = N32;
NET "PP6_SDA" IOSTANDARD = LVCMOS33;
NET "PP6_SDA" LOC = P32;
NET "PP7_SCL" IOSTANDARD = LVCMOS33;
NET "PP7_SCL" LOC = N34;
NET "PP7_SDA" IOSTANDARD = LVCMOS33;
NET "PP7_SDA" LOC = P34;
NET "PP8_SCL" IOSTANDARD = LVCMOS33;
NET "PP8_SCL" LOC = M32;
NET "PP8_SDA" IOSTANDARD = LVCMOS33;
NET "PP8_SDA" LOC = L33;
NET "PP9_SCL" IOSTANDARD = LVCMOS33;
NET "PP9_SCL" LOC = M33;
NET "PP9_SDA" IOSTANDARD = LVCMOS33;
NET "PP9_SDA" LOC = N33;
# NET "Q_CS_N" IOSTANDARD = LVCMOS33;
# NET "Q_CS_N" LOC = AP14;
NET "Q_MISO" IOSTANDARD = LVCMOS33;
NET "Q_MISO" LOC = AN14;
# NET "Q_MOSI" IOSTANDARD = LVCMOS33;
# NET "Q_MOSI" LOC = AN12;
# NET "Q_SCLK" IOSTANDARD = LVCMOS33;
# NET "Q_SCLK" LOC = AP12;
#: NET "SEL_VXS" IOSTANDARD = LVCMOS33;
#: "SEL_VXS" LOC = AM11;
NET "SFP0_LOS" IOSTANDARD = LVCMOS33;
NET "SFP0_LOS" LOC = AM33;
NET "SFP0_PRSNT_N" IOSTANDARD = LVCMOS33;
NET "SFP0_PRSNT_N" LOC = AL33;
NET "SFP0_SCL" IOSTANDARD = LVCMOS33;
NET "SFP0_SCL" LOC = AL34;
NET "SFP0_SDA" IOSTANDARD = LVCMOS33;
NET "SFP0_SDA" LOC = AK32;
# NET "SFP0_TX_DIS" IOSTANDARD = LVCMOS33;
# NET "SFP0_TX_DIS" LOC = AK33;
NET "SFP1_LOS" IOSTANDARD = LVCMOS33;
NET "SFP1_LOS" LOC = AJ32;
NET "SFP1_PRSNT_N" IOSTANDARD = LVCMOS33;
NET "SFP1_PRSNT_N" LOC = AH32;
NET "SFP1_SCL" IOSTANDARD = LVCMOS33;
NET "SFP1_SCL" LOC = AG32;
NET "SFP1_SDA" IOSTANDARD = LVCMOS33;
NET "SFP1_SDA" LOC = AK34;
# NET "SFP1_TX_DIS" IOSTANDARD = LVCMOS33;
# NET "SFP1_TX_DIS" LOC = AH33;
NET "SFP2_LOS" IOSTANDARD = LVCMOS33;
NET "SFP2_LOS" LOC = AJ34;
NET "SFP2_PRSNT_N" IOSTANDARD = LVCMOS33;
NET "SFP2_PRSNT_N" LOC = AH34;
NET "SFP2_SCL" IOSTANDARD = LVCMOS33;
NET "SFP2_SCL" LOC = AE34;
NET "SFP2_SDA" IOSTANDARD = LVCMOS33;
NET "SFP2_SDA" LOC = AF34;
# NET "SFP2_TX_DIS" IOSTANDARD = LVCMOS33;
# NET "SFP2_TX_DIS" LOC = AE33;
NET "SFP3_LOS" IOSTANDARD = LVCMOS33;
NET "SFP3_LOS" LOC = AD34;
NET "SFP3_PRSNT_N" IOSTANDARD = LVCMOS33;
NET "SFP3_PRSNT_N" LOC = AC34;
NET "SFP3_SCL" IOSTANDARD = LVCMOS33;
NET "SFP3_SCL" LOC = Y34;
NET "SFP3_SDA" IOSTANDARD = LVCMOS33;
NET "SFP3_SDA" LOC = AA34;
NET "SFP3_TX_DIS" IOSTANDARD = LVCMOS33;
NET "SFP3_TX_DIS" LOC = AA33;
# NET "SW_RX_N" LOC = F28;
# NET "SW_RX_IBUFDS/SW_RX_P" LOC = E28;
# NET "SW_RX_P" LOC = E28;
# NET "SW_RX_N" IOSTANDARD = LVPECL_25;
# NET "SW_RX_P" IOSTANDARD = LVPECL_25;
NET "SW_SE1" IOSTANDARD = LVCMOS33;
NET "SW_SE1" LOC = E34;
NET "SW_SE2" IOSTANDARD = LVCMOS33;
NET "SW_SE2" LOC = E29;
NET "SW_SE3" IOSTANDARD = LVCMOS33;
NET "SW_SE3" LOC = F29;
NET "SW_SE4" IOSTANDARD = LVCMOS33;
NET "SW_SE4" LOC = F30;
NET "SW_SE5" IOSTANDARD = LVCMOS33;
NET "SW_SE5" LOC = D34;
NET "SW_SE6" IOSTANDARD = LVCMOS33;
NET "SW_SE6" LOC = E32;
NET "SW_SE7" IOSTANDARD = LVCMOS33;
NET "SW_SE7" LOC = E33;
NET "SW_SE8" IOSTANDARD = LVCMOS33;
NET "SW_SE8" LOC = G30;
# NET "SW_TX_N" IOSTANDARD = LVPECL_25;
# NET "SW_TX_N" LOC = G28;
# NET "SW_TX_P" LOC = H28;
# NET "SW_TX_P" IOSTANDARD = LVPECL_25;
NET "SYSRST_N" IOSTANDARD = LVCMOS33;
NET "SYSRST_N" LOC = A33;
####### test ports used for WR ############
####### old definitions
#used for 1-wire
#NET "TESTPORT[1]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[1]" LOC = Y7;
#used for UART RXD
#NET "TESTPORT[2]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[2]" LOC = AB5;
# unused
#NET "TESTPORT[3]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[3]" LOC = AA5;
# used for UART TXD
#NET "TESTPORT[4]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[4]" LOC = AB7;
# unused
#NET "TESTPORT[5]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[5]" LOC = AB6;
################# new definitions
# UART at TESTPORT[0]
NET "UART_RXD" IOSTANDARD = LVCMOS33;
NET "UART_RXD" LOC = AA6;
# 1-wire at TESTPORT[1]
NET "DQ_WR" IOSTANDARD = LVCMOS33;
NET "DQ_WR" LOC = Y7;
NET "DQ_WR" PULLUP;
# UART at TESTPORT[2]
NET "UART_TXD" IOSTANDARD = LVCMOS33;
NET "UART_TXD" LOC = AB5;
##########################################################
# NET "TESTPORT[10]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[10]" LOC = AD6;
# NET "TESTPORT[11]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[11]" LOC = AD5;
# NET "TESTPORT[12]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[12]" LOC = AD7;
# NET "TESTPORT[13]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[13]" LOC = AE6;
# NET "TESTPORT[14]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[14]" LOC = AF6;
# NET "TESTPORT[15]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[15]" LOC = AF5;
# NET "TESTPORT[6]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[6]" LOC = AC5;
# NET "TESTPORT[7]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[7]" LOC = AC4;
# NET "TESTPORT[8]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[8]" LOC = AD4;
# NET "TESTPORT[9]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[9]" LOC = AC7;
NET "XBAR_ADDR[0]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[0]" LOC = H8;
NET "XBAR_ADDR[1]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[1]" LOC = G10;
NET "XBAR_ADDR[2]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[2]" LOC = J10;
NET "XBAR_ADDR[3]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[3]" LOC = H10;
NET "XBAR_ADDR[4]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[4]" LOC = G12;
NET "XBAR_ADDR[5]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[5]" LOC = G8;
NET "XBAR_ADDR[6]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[6]" LOC = F10;
NET "XBAR_ADDR[7]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[7]" LOC = F8;
NET "XBAR_ADDR[8]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[8]" LOC = E8;
NET "XBAR_ADDR[9]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[9]" LOC = D10;
NET "XBAR_CS_N" IOSTANDARD = LVCMOS33;
NET "XBAR_CS_N" LOC = E12;
NET "XBAR_DATA[0]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[0]" LOC = K8;
NET "XBAR_DATA[1]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[1]" LOC = J9;
NET "XBAR_DATA[2]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[2]" LOC = H9;
NET "XBAR_DATA[3]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[3]" LOC = K9;
NET "XBAR_DATA[4]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[4]" LOC = E13;
NET "XBAR_DATA[5]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[5]" LOC = E11;
NET "XBAR_DATA[6]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[6]" LOC = D12;
NET "XBAR_DATA[7]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[7]" LOC = E9;
NET "XBAR_DIS_N" IOSTANDARD = LVCMOS33;
NET "XBAR_DIS_N" LOC = L10;
NET "XBAR_DS_N" IOSTANDARD = LVCMOS33;
NET "XBAR_DS_N" LOC = F9;
# NET "XBAR_ENRX_N[0]" IOSTANDARD = LVCMOS33;
# NET "XBAR_ENRX_N[0]" LOC = B12;
# NET "XBAR_ENRX_N[1]" IOSTANDARD = LVCMOS33;
# NET "XBAR_ENRX_N[1]" LOC = F11;
# NET "XBAR_ENTX_N[0]" IOSTANDARD = LVCMOS33;
# NET "XBAR_ENTX_N[0]" LOC = C12;
# NET "XBAR_ENTX_N[1]" IOSTANDARD = LVCMOS33;
# NET "XBAR_ENTX_N[1]" LOC = G11;
NET "XBAR_LOS" IOSTANDARD = LVCMOS33;
NET "XBAR_LOS" LOC = L11;
NET "XBAR_PERROR[0]" IOSTANDARD = LVCMOS33;
NET "XBAR_PERROR[0]" LOC = B13;
NET "XBAR_PERROR[1]" IOSTANDARD = LVCMOS33;
NET "XBAR_PERROR[1]" LOC = J11;
NET "XBAR_RD" IOSTANDARD = LVCMOS33;
NET "XBAR_RD" LOC = D11;
NET "XBAR_RSTRX_N[0]" IOSTANDARD = LVCMOS33;
NET "XBAR_RSTRX_N[0]" LOC = A13;
NET "XBAR_RSTRX_N[1]" IOSTANDARD = LVCMOS33;
NET "XBAR_RSTRX_N[1]" LOC = F13;
NET "XBAR_RST_N" IOSTANDARD = LVCMOS33;
NET "XBAR_RST_N" LOC = C13;
# NET "XBAR_SER" IOSTANDARD = LVCMOS33;
# NET "XBAR_SER" LOC = K11;
NET "XBAR_SET_N" IOSTANDARD = LVCMOS33;
NET "XBAR_SET_N" LOC = G13;
# Missing pull-up resistors in HW V1
NET "GAP_N" PULLUP;
NET "GA_N[0]" PULLUP;
NET "GA_N[1]" PULLUP;
NET "GA_N[2]" PULLUP;
NET "GA_N[3]" PULLUP;
NET "GA_N[4]" PULLUP;
# PlanAhead Generated physical constraints
NET "FPGA_IO_E1_N" LOC = AK11; # AL10
NET "FPGA_IO_E2_N" LOC = AL10; # AK11
NET "FPGA_IO_IN1" LOC = AG8; # AJ11
NET "FPGA_IO_IN2" LOC = AH9; # AJ10
NET "FPGA_IO_Z1" LOC = AJ9;
NET "FPGA_IO_Z2" LOC = AH8;
# PlanAhead Generated IO constraints
NET "FPGA_IO_E1_N" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_E2_N" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_IN1" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_IN2" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_Z1" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_Z2" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_E1_N" DRIVE = 12;
NET "FPGA_IO_E2_N" DRIVE = 12;
NET "FPGA_IO_IN1" DRIVE = 12;
NET "FPGA_IO_IN2" DRIVE = 12;
NET "FPGA_IO_Z1" DRIVE = 12;
NET "FPGA_IO_Z2" DRIVE = 12;
NET "FPGA_IO_E1_N" SLEW = SLOW;
NET "FPGA_IO_E2_N" SLEW = SLOW;
NET "FPGA_IO_IN1" SLEW = SLOW;
NET "FPGA_IO_IN2" SLEW = SLOW;
NET "FPGA_IO_Z1" SLEW = SLOW;
NET "FPGA_IO_Z2" SLEW = SLOW;
############################ WR stuff #################################
# DDMTD
NET "VCXO_MHZ20" TNM_NET = VCXO_MHZ20;
# ML-replaced
# TIMESPEC TS_VCXO_MHZ20 = PERIOD "VCXO_MHZ20" 21 MHz HIGH 50%;
TIMESPEC TS_VCXO_MHZ20 = PERIOD "VCXO_MHZ20" 50 ns HIGH 50%;
# main
NET "VCXO_MHZ125_N" TNM_NET = VCXO_MHZ125_N;
# ML-replaced
# TIMESPEC TS_VCXO_MHZ125_N = PERIOD "VCXO_MHZ125_N" 132 MHz HIGH 50%;
TIMESPEC TS_VCXO_MHZ125_N = PERIOD "VCXO_MHZ125_N" 8 ns HIGH 50%;
NET "VCXO_MHZ125_P" TNM_NET = VCXO_MHZ125_P;
# ML-replaced
# TIMESPEC TS_VCXO_MHZ125_P = PERIOD "VCXO_MHZ125_P" 132 MHz HIGH 50%;
TIMESPEC TS_VCXO_MHZ125_P = PERIOD "VCXO_MHZ125_P" 8 ns HIGH 50%;
# SFP:
NET "GTP118_CLK_N" TNM_NET = GTP118_CLK_N;
# ML-replaced
#TIMESPEC TS_GTP118_CLK_N = PERIOD "GTP118_CLK_N" 132 MHz HIGH 50%;
TIMESPEC TS_GTP118_CLK_N = PERIOD "GTP118_CLK_N" 8 ns HIGH 50%;
NET "GTP118_CLK_P" TNM_NET = GTP118_CLK_P;
# ML-replaced
#TIMESPEC TS_GTP118_CLK_P = PERIOD "GTP118_CLK_P" 132 MHz HIGH 50%;
TIMESPEC TS_GTP118_CLK_P = PERIOD "GTP118_CLK_P" 8 ns HIGH 50%;
NET "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad" TNM_NET = cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad;
TIMESPEC TS_cmp_xwrc_board_vxs_cmp_xwrc_platform_gen_phy_virtex5_cmp_gtp_ch1_rx_rec_clk_pad = PERIOD "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad" 8 ns HIGH 50%;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
###############################################################################
#Created by Constraints Editor (xc5vlx50t-ff1136-1) - 2015/04/09
# NET "FPGA_MHZ100_P" TNM_NET = FPGA_MHZ100_P;
# TIMESPEC TS_FPGA_MHZ100_P = PERIOD "FPGA_MHZ100_P" 105 MHz HIGH 50%;
# NET "GTP122_CLK_P" TNM_NET = GTP122_CLK_P;
# TIMESPEC TS_GTP122_CLK_P = PERIOD "GTP122_CLK_P" 105 MHz HIGH 50%;
# NET "RF_CLK_FPGA_P" TNM_NET = RF_CLK_FPGA_P;
# TIMESPEC TS_RF_CLK_FPGA_P = PERIOD "RF_CLK_FPGA_P" 105 MHz HIGH 50%;
#Created by Constraints Editor (xc5vlx50t-ff1136-1) - 2015/04/13
# NET "FPGA_MHZ100_N" TNM_NET = FPGA_MHZ100_N;
# TIMESPEC TS_FPGA_MHZ100_N = PERIOD "FPGA_MHZ100_N" 105 MHz HIGH 50%;
# NET "GTP122_CLK_N" TNM_NET = GTP122_CLK_N;
# TIMESPEC TS_GTP122_CLK_N = PERIOD "GTP122_CLK_N" 105 MHz HIGH 50%;
# NET "RF_CLK_FPGA_N" TNM_NET = RF_CLK_FPGA_N;
# TIMESPEC TS_RF_CLK_FPGA_N = PERIOD "RF_CLK_FPGA_N" 105 MHz HIGH 50%;
#NET "C456/REFCLKOUT_X0Y0" TNM_NET = C456/REFCLKOUT_X0Y0;
#TIMESPEC TS_C456_REFCLKOUT_X0Y0 = PERIOD "C456/REFCLKOUT_X0Y0" 132 MHz HIGH 50%;
-------------------------------------------------------------------------------
-- CERN
-- WR PTP Core
-- http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- vxs_wr_ref_top.vhd
-------------------------------------------------------------------------------
--
-- Description: Top-level file for the WRPC reference design on the VXS switch.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
use work.gn4124_core_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity vxs_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0
);
port ( -- port description taken from EDA-02299-V2-VXS-Switch project
---------------------------------------------------------------
-- WR-related IOs
---------------------------------------------------------------
VCXO_MHZ20 : in std_logic; -- clk_20m_vcxo_i
VCXO_MHZ125_N : in std_logic; -- clk_125m_pllref_p_i
VCXO_MHZ125_P : in std_logic; -- clk_125m_pllref_n_i
GTP118_CLK_N : in std_logic; -- clk_125m_gtp_n_i
GTP118_CLK_P : in std_logic; -- clk_125m_gtp_p_i
DAC_PLL_SCLK : out std_logic; -- plldac_sclk_o
DAC_PLL_DIN : out std_logic; -- plldac_din_o
DAC_PLL20_SYNC_N : out std_logic; -- pll20dac_cs_n_o
DAC_PLL125_SYNC_N : out std_logic; -- pll25dac_cs_n_o
DQ_WR : inout std_logic; -- 1-wire
UART_RXD : in std_logic; -- uart_rxd_i
UART_TXD : out std_logic; -- uart_txd_o
-- WR-dedicated SFP
SFP2FPGA_P : in std_logic; -- sfp_rxp_i
SFP2FPGA_N : in std_logic; -- sfp_rxn_i
FPGA2SFP_N : out std_logic;-- sfp_txn_o
FPGA2SFP_P : out std_logic;-- sfp_txp_o
SFP3_PRSNT_N : in std_logic;
SFP3_LOS : in std_logic;
SFP3_SCL : inout std_logic;
SFP3_TX_DIS : out std_logic;
SFP3_SDA : inout std_logic;
--- backup SFP routred via switch FPGA (unused)
FPGA2VXS2_N : out std_logic;
FPGA2VXS2_P : out std_logic;
VXS2FPGA2_N : in std_logic;
VXS2FPGA2_P : in std_logic;
SFP2_LOS : in std_logic;
--unused SFP2_TX_DIS : out std_logic;
SFP2_SCL : inout std_logic;
SFP2_SDA : inout std_logic;
SFP2_PRSNT_N : in std_logic;
-- IOs
FPGA_IO_Z1 : out std_logic;
FPGA_IO_Z2 : out std_logic;
FPGA_IO_E1_N : out std_logic;
FPGA_IO_E2_N : out std_logic;
FPGA_IO_OUT1 : out std_logic;
-- unused FPGA_IO_OUT2 : out std_logic;
FPGA_IO_IN1 : in std_logic;
FPGA_IO_IN2 : in std_logic;
-- control of SFP's leds
LED_SFP_SDA : inout std_logic;
LED_SFP_SCL : inout std_logic;
POR : in std_logic;
LED_CLK_R : out std_logic;
LED_CLK_G : out std_logic;
-- flash
FRAMMOSI : out std_logic;
FRAMSCLK : out std_logic;
FRAMWPDIS : in std_logic;
FRAMWP_N : out std_logic;
FRAMMISO : in std_logic;
FRAMCS_N : out std_logic;
---------------------------------------------------------------
-- other IOs - unused in the WR ref design
---------------------------------------------------------------
SYSRST_N : in std_logic;
PP3_SCL : in std_logic;
PP2_SDA : in std_logic;
ACE_TDO_I : in std_logic;
PP2_SCL : in std_logic;
Q_MISO : in std_logic;
FP_JTAG_ENA_N : out std_logic;
XBAR_DATA : inout std_logic_vector(7 downto 0 );
PP1_SDA_I : in std_logic;
PP12_SDA : in std_logic;
PP12_SCL : in std_logic;
GAP_N : in std_logic;
XBAR_SET_N : out std_logic;
PP11_SDA : in std_logic;
PP11_SCL : in std_logic;
PP10_SDA : in std_logic;
PP10_SCL : in std_logic;
HWVERSION : in std_logic_vector(3 downto 0 );
GA_N : in std_logic_vector(4 downto 0 );
XBAR_RSTRX_N : out std_logic_vector(1 downto 0 );
PP9_SDA : in std_logic;
XBAR_CS_N : out std_logic;
PP9_SCL : in std_logic;
XBAR_PERROR : in std_logic_vector(1 downto 0 );
PP8_SDA : in std_logic;
SFP1_LOS : in std_logic;
SFP1_PRSNT_N : in std_logic;
PP8_SCL : in std_logic;
PP7_SDA : in std_logic;
SFP0_LOS : in std_logic;
PP7_SCL : in std_logic;
PP6_SDA : in std_logic;
SFP1_SCL : inout std_logic;
XBAR_RST_N : out std_logic;
XBAR_LOS : in std_logic;
PP6_SCL : in std_logic;
XBAR_ADDR : out std_logic_vector(9 downto 0 );
SFP1_SDA : inout std_logic;
PP5_SDA : in std_logic;
SFP0_SCL : inout std_logic;
XBAR_DS_N : out std_logic;
XBAR_RD : out std_logic;
PP5_SCL : in std_logic;
SW_SE1 : in std_logic;
SW_SE2 : in std_logic;
SW_SE3 : in std_logic;
SW_SE4 : in std_logic;
SW_SE5 : in std_logic;
SW_SE6 : in std_logic;
SW_SE7 : in std_logic;
SW_SE8 : in std_logic;
SFP0_SDA : inout std_logic;
PP4_SDA : in std_logic;
XBAR_DIS_N : out std_logic;
PP4_SCL : in std_logic;
PP3_SDA : in std_logic;
DQ : inout std_logic;
SFP0_PRSNT_N : in std_logic
-- pins commeted out in constraints to prevent warnings/errors
-- FPGA2VXS0_N : out std_logic;
-- FPGA2VXS0_P : out std_logic;
-- VXS2FPGA0_N : in std_logic;
-- VXS2FPGA0_P : in std_logic;
-- FPGA_MHZ100_N : in std_logic;
-- FPGA_MHZ100_P : in std_logic;
-- VXS2FPGA1_N : in std_logic;
-- VXS2FPGA1_P : in std_logic;
-- FPGA2VXS1_N : out std_logic;
-- FPGA2VXS1_P : out std_logic;
-- GTP122_CLK_N : in std_logic;
-- GTP122_CLK_P : in std_logic;
-- RF_CLK_FPGA_N : in std_logic;
-- RF_CLK_FPGA_P : in std_logic;
-- TAG_FPGA_N : in std_logic;
-- TAG_FPGA_P : in std_logic;
-- FPGA_MHZ200_N : in std_logic;
-- FPGA_MHZ200_P : in std_logic;
-- FPGA_MHZ50_N : in std_logic;
-- FPGA_MHZ50_P : in std_logic;
-- SW_RX_N : in std_logic;
-- SW_RX_P : in std_logic;
-- SW_TX_N : out std_logic;
-- SW_TX_P : out std_logic;
-- LED_SPARE_R : out std_logic;
-- LED_SPARE_G : out std_logic;
-- TESTPORT : out std_logic_vector(15 downto 4 );
-- PP1_SDA_O_N : out std_logic;
-- XBAR_SER : out std_logic;
-- PP1_SCL_I : in std_logic;
-- ACE_TDI_O : out std_logic;
-- Q_CS_N : out std_logic;
-- ACE_TMS_O : out std_logic;
-- KEEPER : out std_logic;
-- POWERDOWN : out std_logic;
-- XBAR_ENRX_N : out std_logic_vector(1 downto 0 );
-- ACE_TCK_O : out std_logic;
-- SFP0_TX_DIS : out std_logic;
-- Q_SCLK : out std_logic;
-- SFP1_TX_DIS : out std_logic;
-- PP1_SCL_O_N : out std_logic;
-- Q_MOSI : out std_logic;
-- XBAR_ENTX_N : out std_logic_vector(1 downto 0 );
-- SEL_VXS : out std_logic
);
end entity vxs_wr_ref_top;
architecture top of vxs_wr_ref_top is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- clock and reset
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ext_10m : std_logic;
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
signal wrc_pps_out : std_logic;
signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
-- DIO Mezzanine
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
-- ChipScope for histogram readout/debugging
-- component chipscope_virtex5_icon
-- port (
-- CONTROL0: inout std_logic_vector(35 downto 0));
-- end component;
--
-- component chipscope_virtex5_ila
-- port (
-- CONTROL: inout std_logic_vector(35 downto 0);
-- CLK: in std_logic;
-- TRIG0: in std_logic_vector(31 downto 0);
-- TRIG1: in std_logic_vector(31 downto 0);
-- TRIG2: in std_logic_vector(31 downto 0);
-- TRIG3: in std_logic_vector(31 downto 0));
-- end component;
--
-- signal CONTROL0, CONTROL1, CONTROL2, CONTROL3 : std_logic_vector(35 downto 0);
-- signal TRIG0, TRIG1, TRIG2, TRIG3 : std_logic_vector(31 downto 0);
signal led_link : std_logic;
signal led_ack : std_logic;
signal SFP3_TX_DIS_out, SFP3_LOS_in : std_logic;
begin -- architecture top
-----------------------------------------------------------------------------
-- The WR PTP core board package
-----------------------------------------------------------------------------
cmp_xwrc_board_vxs : xwrc_board_vxs
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => FALSE,
g_dpram_initf => g_dpram_initf)
port map (
areset_n_i => std_logic(not POR), -- Power
areset_edge_n_i => '1', -- not use
clk_20m_vcxo_i => VCXO_MHZ20,
clk_125m_pllref_p_i => VCXO_MHZ125_P,
clk_125m_pllref_n_i => VCXO_MHZ125_N,
clk_125m_gtp_n_i => GTP118_CLK_N,
clk_125m_gtp_p_i => GTP118_CLK_P,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
plldac_sclk_o => DAC_PLL_SCLK,
plldac_din_o => DAC_PLL_DIN,
pll25dac_cs_n_o => DAC_PLL125_SYNC_N,
pll20dac_cs_n_o => DAC_PLL20_SYNC_N,
sfp_txp_o => FPGA2SFP_P,
sfp_txn_o => FPGA2SFP_N,
sfp_rxp_i => SFP2FPGA_P,
sfp_rxn_i => SFP2FPGA_N,
sfp_det_i => SFP3_PRSNT_N,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => open, -- connect later
sfp_tx_fault_i => open,
sfp_tx_disable_o => SFP3_TX_DIS_out,
sfp_los_i => SFP3_LOS_in,
eeprom_sda_i => '1',
eeprom_sda_o => open,
eeprom_scl_i => '1',
eeprom_scl_o => open,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
-- Uart
uart_rxd_i => UART_RXD,
uart_txd_o => UART_TXD,
-- SPI Flash
flash_sclk_o => FRAMSCLK,
flash_ncs_o => FRAMCS_N,
flash_mosi_o => FRAMMOSI,
flash_miso_i => FRAMMISO,
pps_p_o => wrc_pps_out,
pps_led_o => wrc_pps_led,
led_link_o => led_link,
led_act_o => led_ack
);
LED_CLK_G <= led_link;
LED_CLK_R <= led_ack;
-- Tristates for SFP EEPROM
SFP3_SCL <= '0' when sfp_scl_out = '0' else 'Z';
SFP3_SDA <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= SFP3_SCL;
sfp_sda_in <= SFP3_SDA;
SFP3_LOS_in <= SFP3_LOS;
SFP3_TX_DIS <= SFP3_TX_DIS_out;
-- tri-state onewire access
DQ_WR <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= DQ_WR;
-- enable JTAG
FP_JTAG_ENA_N <= '0';
-- make sure that switch-bar (M21141G-24) is disabled
XBAR_SET_N <= '1';
XBAR_RST_N <= '0';
XBAR_CS_N <= '1';
XBAR_ADDR <= (others => '0');
XBAR_DS_N <= '1';
XBAR_RD <= '1';
XBAR_RSTRX_N <= "00";
XBAR_DIS_N <= '0';
-- outputs
FPGA_IO_E1_N <= '0'; -- enable output buffer of IO1 (active low)
FPGA_IO_E2_N <= '1'; -- enable output buffer of IO2 (active low)
FPGA_IO_Z1 <= '0'; -- disable terminatin 50 ohm termination (active high)
FPGA_IO_Z2 <= '0'; -- disable terminatin 50 ohm termination (active high)
FPGA_IO_OUT1 <= wrc_pps_out;
-- FPGA_IO_OUT2 <= clk_ref_125m; -- not sure output fast-enough
-- FLASH
FRAMWP_N <= '1'; -- not write protected
--
-- CS_ICON : chipscope_virtex5_icon
-- port map (
-- CONTROL0 => CONTROL0);
-- CS_ILA : chipscope_virtex5_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_sys_62m5,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--
-- trig0(2) <= onewire_data;
-- trig0(3) <= led_link;
-- trig0(4) <= led_ack;
-- trig0(5) <= SFP3_PRSNT_N;
-- trig0(6) <= SFP3_LOS;
-- trig0(7) <= SFP3_TX_DIS_out;
-- trig0(8) <= wrc_pps_out;
-- trig0(9) <= wrc_pps_led;
end architecture top;
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