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White Rabbit core collection
Commit 6417d9c0 authored by Cesar Prados's avatar Cesar Prados
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wr_endpoint: cleanup unused and unsaved signals 

the signal link_kill_i is not used anymore, either the signal
ep_ctrl_i and link_ctrl_i which are steered byt link_kill_i.

Remove also processes that use these signal... besides,
according to the author of the commit this code covers
dubious situations like: "in theory, this should not happen"
parent f9a533b6
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Showing with 3 additions and 54 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 6417d9c0
......@@ -267,7 +267,6 @@ package endpoint_pkg is
rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
led_link_o : out std_logic;
led_act_o : out std_logic;
link_kill_i : in std_logic := '0';
link_up_o : out std_logic;
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
......@@ -394,7 +393,6 @@ package endpoint_pkg is
rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
led_link_o : out std_logic;
led_act_o : out std_logic;
link_kill_i : in std_logic := '0';
link_up_o : out std_logic;
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 6417d9c0
......@@ -135,7 +135,6 @@ package endpoint_private_pkg is
txpcs_dreq_o : out std_logic;
txpcs_timestamp_trigger_p_a_o : out std_logic;
link_ok_o : out std_logic;
link_ctr_i : in std_logic := '1';
serdes_rst_o : out std_logic;
serdes_loopen_o : out std_logic;
serdes_loopen_vec_o : out std_logic_vector(2 downto 0);
......@@ -382,7 +381,6 @@ package endpoint_private_pkg is
txtsu_ack_i : in std_logic;
txts_timestamp_i : in std_logic_vector(31 downto 0);
txts_timestamp_valid_i : in std_logic;
ep_ctrl_i : in std_logic;
regs_i : in t_ep_out_registers);
end component;
......@@ -728,7 +726,6 @@ package endpoint_private_pkg is
inject_ready_o : out std_logic;
inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
ep_ctrl_i : in std_logic := '1';
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers;
dbg_o : out std_logic_vector(33 downto 0));
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ 6417d9c0
......@@ -116,7 +116,6 @@ entity ep_1000basex_pcs is
txpcs_timestamp_trigger_p_a_o : out std_logic;
link_ok_o : out std_logic;
link_ctr_i : in std_logic;
-----------------------------------------------------------------------------
-- GTP/GTX/TBI Serdes interface
---------------------------------------------------------------------------
......@@ -419,8 +418,7 @@ begin -- rtl
txpcs_busy_o <= txpcs_busy_int;
-- to enable killing of link (by ML)
mdio_mcr_pdown <= mdio_mcr_pdown_cpu or (not link_ctr_i);
mdio_mcr_pdown <= mdio_mcr_pdown_cpu;
-- keep PHY reset also when SFP reports LOS (DL)
serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown or serdes_sfp_los_i;
......
modules/wr_endpoint/ep_tx_framer.vhd
View file @ 6417d9c0
......@@ -112,8 +112,6 @@ entity ep_tx_framer is
-------------------------------------------------------------------------------
-- Control registers
-------------------------------------------------------------------------------
ep_ctrl_i : in std_logic;
regs_i : in t_ep_out_registers
);
......@@ -741,7 +739,7 @@ begin -- behavioral
end if;
end process;
tx_en <= regs_i.ecr_tx_en_o and ep_ctrl_i;
tx_en <= regs_i.ecr_tx_en_o;
stall_int <= (not (pcs_dreq_i and tx_ready) and tx_en) or (snk_i.cyc xor snk_cyc_d0); -- /dev/null if disabled
......
modules/wr_endpoint/ep_tx_header_processor.vhd
View file @ 6417d9c0
......@@ -125,7 +125,6 @@ entity ep_tx_header_processor is
-------------------------------------------------------------------------------
-- Control registers
-------------------------------------------------------------------------------
ep_ctrl_i : in std_logic;
regs_i : in t_ep_out_registers
);
......@@ -168,7 +167,6 @@ architecture behavioral of ep_tx_header_processor is
signal abort_now : std_logic;
signal stall_int : std_logic;
signal tx_en : std_logic;
signal ep_ctrl : std_logic;
signal bitsel_d : std_logic;
signal needs_padding : std_logic;
signal to_be_untagged : std_logic;
......@@ -649,7 +647,7 @@ begin -- behavioral
end if;
end process;
tx_en <= regs_i.ecr_tx_en_o and ep_ctrl and ep_ctrl_i;
tx_en <= regs_i.ecr_tx_en_o;
--p_gen_stall : process(src_dreq_i, state, regs_i, wb_snk_i, snk_cyc_d0, tx_en)
p_gen_stall : process(src_dreq_i, state, tx_en, wb_snk_i, eof_p1)
......@@ -699,24 +697,6 @@ begin -- behavioral
end if;
end process;
-- in theory, this should not happen: we don't send frames to ports which are DOWN, but..
-- we make sure that we don't start sending frames on the PHY in the middle of the frame...
-- the TX is enabled only when we don't receive any frames from SWcore
p_ctrl: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
ep_ctrl <= '1';
else
if(ep_ctrl_i = '0') then
ep_ctrl <= '0';
elsif(ep_ctrl_i = '1' and wb_snk_i.cyc = '0') then
ep_ctrl <= '1';
end if; --ep_ctr
end if;-- rst
end if; -- clk
end process;
wb_snk_o <= wb_out;
end behavioral;
......
modules/wr_endpoint/ep_tx_path.vhd
View file @ 6417d9c0
......@@ -134,7 +134,6 @@ entity ep_tx_path is
-------------------------------------------------------------------------------
-- Control registers
-------------------------------------------------------------------------------
ep_ctrl_i : in std_logic :='1';
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers;
dbg_o : out std_logic_vector(33 downto 0)
......@@ -197,7 +196,6 @@ begin -- rtl
txtsu_ack_i => txtsu_ack_i,
txts_timestamp_i => txts_timestamp_i,
txts_timestamp_valid_i => txts_timestamp_valid_i,
ep_ctrl_i => ep_ctrl_i,
regs_i => regs_i);
txtsu_stb_o <= txtsu_stb;
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 6417d9c0
......@@ -289,9 +289,6 @@ entity wr_endpoint is
led_link_o : out std_logic;
led_act_o : out std_logic;
-- HI physically kills the link (turn of laser)
link_kill_i : in std_logic := '0';
-- HI indicates that link is up (so cable connected), LOW indicates that link is faulty
-- (e.g.: cable disconnected)
link_up_o : out std_logic;
......@@ -421,7 +418,6 @@ architecture syn of wr_endpoint is
-------------------------------------------------------------------------------
-- TRU stuff
-------------------------------------------------------------------------------
signal ep_ctrl : std_logic;
signal pfilter_pclass : std_logic_vector(7 downto 0);
signal pfilter_drop : std_logic;
signal pfilter_done : std_logic;
......@@ -492,7 +488,6 @@ begin
txpcs_timestamp_trigger_p_a_o => txpcs_timestamp_trigger_p_a,
link_ok_o => link_ok,
link_ctr_i => ep_ctrl,
serdes_rst_o => phy_rst_o,
serdes_loopen_o => phy_loopen_o,
......@@ -556,7 +551,6 @@ begin
fc_pause_ready_o => txfra_pause_ready,
fc_pause_delay_i => txfra_pause_delay,
fc_flow_enable_i => txfra_flow_enable,
ep_ctrl_i => ep_ctrl,
regs_i => regs_fromwb,
regs_o => regs_towb_tpath,
......@@ -900,18 +894,6 @@ begin
fc_tx_pause_ready_o <= txfra_pause_ready;
txfra_pause_delay <= fc_tx_pause_delay_i;
-- TRU needs to be able to share the control of ouput path, i.e. turn off the laser
p_ep_ctrl : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' then
ep_ctrl <= '1';
else
ep_ctrl <= not link_kill_i;
end if;
end if;
end process;
GEN_STOP: if(g_with_stop_traffic) generate
rxpath_fab.sof <= rxpcs_fab.sof when(stop_traffic_i='0') else '0';
rxpath_fab.dvalid <= rxpcs_fab.dvalid when(stop_traffic_i='0') else '0';
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 6417d9c0
......@@ -263,7 +263,6 @@ entity xwr_endpoint is
led_link_o : out std_logic;
led_act_o : out std_logic;
link_kill_i : in std_logic := '0';
link_up_o : out std_logic;
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
......@@ -406,7 +405,6 @@ begin
led_link_o => led_link_o,
led_act_o => led_act_o,
link_up_o => link_up_o,
link_kill_i => link_kill_i,
pfilter_pclass_o => pfilter_pclass_o,
pfilter_drop_o => pfilter_drop_o,
pfilter_done_o => pfilter_done_o,
......
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