wr_endpoint: add to the oob pkt length field

5efc3de3 · Cesar Prados · 3c2a6c72 · 5efc3de3 · 5efc3de3
Commit 5efc3de3 authored Aug 09, 2017 by Cesar Prados
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Showing with 44 additions and 14 deletions

ep_rx_buffer.vhd modules/wr_endpoint/ep_rx_buffer.vhd +8 -4

ep_rx_oob_insert.vhd modules/wr_endpoint/ep_rx_oob_insert.vhd +36 -10

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--- a/modules/wr_endpoint/ep_rx_buffer.vhd
+++ b/modules/wr_endpoint/ep_rx_buffer.vhd
@@ -90,10 +90,14 @@ architecture behavioral of ep_rx_buffer is
      -- tag = 11
      dout(17)          <= '1';
      dout(16)          <= '1';
-      dout(15)          <= fab.sof;
-      dout(14)          <= fab.eof;
-      dout(13)          <= fab.error;
-      dout(12 downto 0) <= (others => '0');
+      if(fab.dvalid = '1') then
+        dout(15 downto 0) <= fab.data;
+      else
+        dout(15)          <= fab.sof;
+        dout(14)          <= fab.eof;
+        dout(13)          <= fab.error;
+        dout(12 downto 0) <= (others => '0');
+      end if;
      valid_tmp         := '1';
 --      dout_valid        <= '1';
    elsif(fab.dvalid = '1') then

--- a/modules/wr_endpoint/ep_rx_oob_insert.vhd
+++ b/modules/wr_endpoint/ep_rx_oob_insert.vhd
@@ -29,8 +29,9 @@ architecture behavioral of ep_rx_oob_insert is

  type t_state is (WAIT_OOB, OOB);
  signal state : t_state;
+  signal src_fab_addr : std_logic_vector(1 downto 0);

-  signal src_dreq_d0 : std_logic;
+  signal byte_cntr   : unsigned(15 downto 0);

  component chipscope_ila
    port (
@@ -83,6 +84,25 @@ begin
  src_fab_o.eof     <= snk_fab_i.eof;
  src_fab_o.error   <= snk_fab_i.error;
  src_fab_o.bytesel <= snk_fab_i.bytesel;
+  src_fab_o.addr    <= src_fab_addr;
+
+  p_count_bytes : process (clk_sys_i, rst_n_i)
+    begin  -- process
+        if rising_edge(clk_sys_i) then
+            if rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' or 
+                snk_fab_i.sof = '1' then
+                byte_cntr <= (others => '0');
+            else
+                if(snk_fab_i.dvalid = '1' and src_fab_addr = c_WRF_DATA) then
+                    if(snk_fab_i.bytesel = '1') then
+                        byte_cntr <= byte_cntr + 1;
+                    else
+                        byte_cntr <= byte_cntr + 2;
+                    end if;
+                end if;
+            end if;
+        end if;
+  end process;

  p_comb_src : process (state, snk_fab_i, src_dreq_i, regs_i)
  begin
@@ -90,15 +110,22 @@ begin
    if(snk_fab_i.has_rx_timestamp = '1')then
      src_fab_o.data   <= c_WRF_OOB_TYPE_RX & (not snk_fab_i.rx_timestamp_valid) & "000000" & regs_i.ecr_portid_o;
      src_fab_o.dvalid <= '1';
-      src_fab_o.addr   <= c_WRF_OOB;
+      src_fab_addr   <= c_WRF_OOB;
    else
      if(state = WAIT_OOB) then
-        src_fab_o.addr <= c_WRF_DATA;
-      else
-        src_fab_o.addr <= c_WRF_OOB;
+        src_fab_addr   <= c_WRF_DATA;
+        src_fab_o.data   <= snk_fab_i.data;
+        src_fab_o.dvalid <= snk_fab_i.dvalid;
+      elsif (state = OOB) then
+        src_fab_addr   <= c_WRF_OOB;
+        if (snk_fab_i.eof = '1') then
+          src_fab_o.data   <= std_logic_vector(byte_cntr);
+          src_fab_o.dvalid <= '1';
+        else
+          src_fab_o.data   <= snk_fab_i.data;
+          src_fab_o.dvalid <= snk_fab_i.dvalid;
+        end if;
      end if;
-      src_fab_o.data   <= snk_fab_i.data;
-      src_fab_o.dvalid <= snk_fab_i.dvalid;
    end if;
  end process;

@@ -109,6 +136,8 @@ begin
        state <= WAIT_OOB;
      else

+        --src_fab_o.eof <= snk_fab_i.eof;
+
        if(snk_fab_i.error = '1' or snk_fab_i.sof = '1') then
          state <= WAIT_OOB;
        else
@@ -123,14 +152,11 @@ begin
              if(snk_fab_i.eof = '1') then
                state <= WAIT_OOB;
              end if;
-              
          end case;
        end if;
      end if;
    end if;
  end process;
-
-
 end behavioral;