re-done manifests to distinguish between Altera and Xilinx synthesis targets

5d852cc7 · Tomasz Wlostowski · da5a9d35 · 5d852cc7 · 5d852cc7 · 5d852cc7
Commit 5d852cc7 authored Feb 10, 2012 by Tomasz Wlostowski
5 changed files
--- a/Manifest.py
+++ b/Manifest.py
 fetchto = "ip_cores"

 modules =  {"local" : 
-											[ "platform/xilinx/wr_gtp_phy",
+											[ "platform",
 												"modules/fabric",
 												"modules/wr_tbi_phy",
 												"modules/timing",

--- a/platform/Manifest.py
+++ b/platform/Manifest.py
+if target=="altera":
+	modules = {"local" : "altera"}
+elif target=="xilinx":
+	modules = {"local" : "xilinx"}
\ No newline at end of file
--- a/platform/altera/Manifest.py
+++ b/platform/altera/Manifest.py
+modules = {"local":"wr_gxb_phy_arria2"}
\ No newline at end of file
--- a/platform/altera/wr_gxb_phy_arria2/Manifest.py
+++ b/platform/altera/wr_gxb_phy_arria2/Manifest.py
+files = ["altgx_reconf.vhd",
+				 "arria_phy.vhd",
+				 "wr_gxb_phy_arriaii.vhd" ];
+				 
+
+if (action == "simulation"):
+	modules = { "local" : "sim" };
\ No newline at end of file
--- a/platform/xilinx/Manifest.py
+++ b/platform/xilinx/Manifest.py
+modules = {"local" : ["wr_gtp_phy", "chipscope"]}
\ No newline at end of file