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White Rabbit core collection
Commit 5999b631 authored by Antonin Broquet's avatar Antonin Broquet
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add clock output from wr pll for FLASH interface (xil_multiboot module).

parent 69cc4cc3
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Showing with 17 additions and 2 deletions
board/spec/xwrc_board_spec.vhd
View file @ 5999b631
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-07-04
-- Last update: 2022-04-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -104,6 +104,8 @@ entity xwrc_board_spec is
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- 10MHz FLASH clock output
clk_flash_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
......@@ -316,7 +318,7 @@ begin -- architecture struct
I => clk_125m_pllref_p_i,
IB => clk_125m_pllref_n_i);
cmp_xwrc_platform : xwrc_platform_xilinx
cmp_xwrc_platform : entity work.xwrc_platform_xilinx
generic map (
g_fpga_family => "spartan6",
g_with_external_clock_input => g_with_external_clock_input,
......@@ -337,6 +339,7 @@ begin -- architecture struct
sfp_los_i => sfp_los_i,
sfp_tx_disable_o => sfp_tx_disable_o,
clk_62m5_sys_o => clk_pll_62m5,
clk_flash_o => clk_flash_o,
clk_125m_ref_o => clk_pll_125m,
clk_62m5_dmtd_o => clk_pll_dmtd,
pll_locked_o => pll_locked,
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ 5999b631
......@@ -122,6 +122,7 @@ entity xwrc_platform_xilinx is
---------------------------------------------------------------------------
-- PLL outputs
clk_62m5_sys_o : out std_logic;
clk_flash_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_ref_locked_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
......@@ -191,6 +192,7 @@ begin -- architecture rtl
signal clk_sys : std_logic;
signal clk_sys_out : std_logic;
signal clk_sys_fb : std_logic;
signal clk_flash : std_logic;
signal pll_sys_locked : std_logic;
signal clk_dmtd : std_logic;
signal clk_dmtd_fb : std_logic;
......@@ -211,11 +213,15 @@ begin -- architecture rtl
CLKOUT0_DIVIDE => 16,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 100,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => clk_sys_fb,
CLKOUT0 => clk_sys,
CLKOUT1 => clk_flash,
LOCKED => pll_sys_locked,
RST => pll_arst,
CLKFBIN => clk_sys_fb,
......@@ -233,6 +239,12 @@ begin -- architecture rtl
O => clk_sys_out,
I => clk_sys);
-- System PLL output clock buffer
cmp_clk_flash_buf_o : BUFG
port map (
O => clk_flash_o,
I => clk_flash);
clk_62m5_sys_o <= clk_sys_out;
clk_125m_ref_o <= clk_125m_pllref_buf;
pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
......
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