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White Rabbit core collection
Commit 581e8d02 authored by Qiang Du's avatar Qiang Du
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Add 9th wb client(g_aux1_sdb) to WB_SECONDARY_CON(xwb_sdb_crossbar) in modules/wrc_core/wr_core.vhd 

Connect xil_multiboot to g_aux1_sdb at top/cute_wr/wr_core_demo/cute_top.vhd

Fix g_aux_sdb to c_etherbone_sdb.

BusPath        VendorID         Product   BaseAddress(Hex)  Description
1              000000000000ce42:66cfeb52                 0  WB4-BlockRAM
2              0000000000000651:eef0b198             20000  WB4-Bridge-GSI
2.1            000000000000ce42:ab28633a             20000  WR-Mini-NIC
2.2            000000000000ce42:650c2d4f             20100  WR-Endpoint
2.3            000000000000ce42:65158dc0             20200  WR-Soft-PLL
2.4            000000000000ce42:de0d8ced             20300  WR-PPS-Generator
2.5            000000000000ce42:ff07fc47             20400  WR-Periph-Syscon
2.6            000000000000ce42:e2d13d04             20500  WR-Periph-UART
2.7            000000000000ce42:779c5443             20600  WR-Periph-1Wire
2.8            0000000000000651:68202b22             20700  Etherbone-Config
2.9            000000000000ce42:deadbeaf             20800  SPI-flash+Multiboot
parent 634ae5bf
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Showing with 98 additions and 17 deletions
modules/wrc_core/wr_core.vhd
View file @ 581e8d02
......@@ -63,6 +63,7 @@
-- +0x500: UART
-- +0x600: OneWire
-- +0x700: Auxillary space (Etherbone config, etc)
-- +0x900: Auxillary1 space (SPI FLASH + Multiboot, etc)
library ieee;
use ieee.std_logic_1164.all;
......@@ -79,7 +80,7 @@ use work.softpll_pkg.all;
entity wr_core is
generic(
--if set to 1, then blocks in PCS use smaller calibration counter to speed
--if set to 1, then blocks in PCS use smaller calibration counter to speed
--up simulation
g_simulation : integer := 0;
g_with_external_clock_input : boolean := false;
......@@ -93,6 +94,7 @@ entity wr_core is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_aux1_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024
......@@ -206,6 +208,19 @@ entity wr_core is
aux_ack_i : in std_logic := '1';
aux_stall_i : in std_logic := '0';
-----------------------------------------
-- Auxillary1 WB master
-----------------------------------------
aux1_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux1_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux1_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
aux1_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux1_we_o : out std_logic;
aux1_cyc_o : out std_logic;
aux1_stb_o : out std_logic;
aux1_ack_i : in std_logic := '1';
aux1_stall_i : in std_logic := '0';
-----------------------------------------
-- External Fabric I/F
-----------------------------------------
......@@ -350,7 +365,8 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--WB Secondary Crossbar
-----------------------------------------------------------------------------
constant c_secbar_layout : t_sdb_record_array(7 downto 0) :=
constant c_nr_slaves_secbar : natural := 9;
constant c_secbar_layout : t_sdb_record_array(c_nr_slaves_secbar-1 downto 0) :=
(0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
......@@ -358,15 +374,16 @@ architecture struct of wr_core is
4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"), -- Syscon
5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"), -- UART
6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"), -- 1-Wire
7 => f_sdb_embed_device(g_aux_sdb, x"00000700") -- aux WB bus
7 => f_sdb_embed_device(g_aux_sdb, x"00000700"), -- aux WB bus
8 => f_sdb_embed_device(g_aux1_sdb, x"00000800") -- aux1 WB bus
);
constant c_secbar_sdb_address : t_wishbone_address := x"00000800";
constant c_secbar_sdb_address : t_wishbone_address := x"00001000";
constant c_secbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
signal secbar_master_i : t_wishbone_master_in_array(7 downto 0);
signal secbar_master_o : t_wishbone_master_out_array(7 downto 0);
signal secbar_master_i : t_wishbone_master_in_array(c_nr_slaves_secbar-1 downto 0);
signal secbar_master_o : t_wishbone_master_out_array(c_nr_slaves_secbar-1 downto 0);
-----------------------------------------------------------------------------
--WB intercon
......@@ -859,7 +876,7 @@ begin
WB_SECONDARY_CON : xwb_sdb_crossbar
generic map(
g_num_masters => 1,
g_num_slaves => 8,
g_num_slaves => c_nr_slaves_secbar,
g_registered => true,
g_wraparound => true,
g_layout => c_secbar_layout,
......@@ -906,6 +923,18 @@ begin
secbar_master_i(7).err <= '0';
secbar_master_i(7).rty <= '0';
aux1_adr_o <= secbar_master_o(8).adr;
aux1_dat_o <= secbar_master_o(8).dat;
aux1_sel_o <= secbar_master_o(8).sel;
aux1_cyc_o <= secbar_master_o(8).cyc;
aux1_stb_o <= secbar_master_o(8).stb;
aux1_we_o <= secbar_master_o(8).we;
secbar_master_i(8).dat <= aux1_dat_i;
secbar_master_i(8).ack <= aux1_ack_i;
secbar_master_i(8).stall <= aux1_stall_i;
secbar_master_i(8).err <= '0';
secbar_master_i(8).rty <= '0';
--secbar_master_i(6).err <= '0';
--secbar_master_i(5).err <= '0';
--secbar_master_i(4).err <= '0';
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 581e8d02
......@@ -296,6 +296,7 @@ package wrcore_pkg is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_aux1_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024
......@@ -354,6 +355,9 @@ package wrcore_pkg is
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_unused_master_in;
aux1_master_o : out t_wishbone_master_out;
aux1_master_i : in t_wishbone_master_in := cc_unused_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
......@@ -396,6 +400,7 @@ package wrcore_pkg is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_aux1_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024
......@@ -509,6 +514,19 @@ package wrcore_pkg is
aux_ack_i : in std_logic := '1';
aux_stall_i : in std_logic := '0';
-----------------------------------------
-- Auxillary1 WB master
-----------------------------------------
aux1_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux1_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux1_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux1_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux1_we_o : out std_logic;
aux1_cyc_o : out std_logic;
aux1_stb_o : out std_logic;
aux1_ack_i : in std_logic := '1';
aux1_stall_i : in std_logic := '0';
-----------------------------------------
-- External Fabric I/F
-----------------------------------------
......
modules/wrc_core/xwr_core.vhd
View file @ 581e8d02
......@@ -78,6 +78,7 @@ entity xwr_core is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_aux1_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024
......@@ -172,6 +173,8 @@ entity xwr_core is
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
aux1_master_o : out t_wishbone_master_out;
aux1_master_i : in t_wishbone_master_in := cc_dummy_master_in;
-----------------------------------------
-- External Fabric I/F
-----------------------------------------
......@@ -229,6 +232,7 @@ begin
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_aux_sdb => g_aux_sdb,
g_aux1_sdb => g_aux1_sdb,
g_softpll_channels_config => g_softpll_channels_config,
g_softpll_enable_debugger => g_softpll_enable_debugger,
g_vuart_fifo_size => g_vuart_fifo_size)
......@@ -301,6 +305,16 @@ begin
aux_ack_i => aux_master_i.ack,
aux_dat_i => aux_master_i.dat,
aux1_adr_o => aux1_master_o.adr,
aux1_dat_o => aux1_master_o.dat,
aux1_sel_o => aux1_master_o.sel,
aux1_cyc_o => aux1_master_o.cyc,
aux1_stb_o => aux1_master_o.stb,
aux1_we_o => aux1_master_o.we,
aux1_stall_i => aux1_master_i.stall,
aux1_ack_i => aux1_master_i.ack,
aux1_dat_i => aux1_master_i.dat,
ext_snk_adr_i => wrf_snk_i.adr,
ext_snk_dat_i => wrf_snk_i.dat,
ext_snk_sel_i => wrf_snk_i.sel,
......
top/cute_wr/wr_core_demo/cute_top.vhd
View file @ 581e8d02
......@@ -157,7 +157,23 @@ architecture rtl of cute_top is
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 2;
constant c_nr_slaves : natural := 1;
constant c_wrc_multiboot_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"deadbeaf",
version => x"00000001",
date => x"20141115",
name => "SPI-flash+Multiboot")));
-----------------------------------------
-- Memory map
......@@ -174,24 +190,20 @@ architecture rtl of cute_top is
-- base address definitions
constant c_addr_wrc_slave : t_wishbone_address := x"00000000";
constant c_addr_multiboot : t_wishbone_address := x"00000300";
-- address mask definitions
constant c_mask_wrc_slave : t_wishbone_address := x"00000F00";
constant c_mask_multiboot : t_wishbone_address := x"00000F00";
constant c_mask_wrc_slave : t_wishbone_address := x"00000000";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_wrc_slave => c_addr_wrc_slave,
c_slv_multiboot => c_addr_multiboot
c_slv_wrc_slave => c_addr_wrc_slave
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_wrc_slave => c_mask_wrc_slave,
c_slv_multiboot => c_addr_multiboot
c_slv_wrc_slave => c_mask_wrc_slave
);
------------------------------------------------------------------------------
-- Signals declaration
......@@ -288,6 +300,8 @@ architecture rtl of cute_top is
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
signal multiboot_in : t_wishbone_slave_in;
signal multiboot_out : t_wishbone_slave_out;
begin
......@@ -429,6 +443,7 @@ begin
thermo_id <= '0' when owr_en(0) = '1' else 'Z';
owr_i(0) <= thermo_id;
owr_i(1) <= '0';
pps_o <= pps;
sfp_tx_disable_o <= '0';
......@@ -443,6 +458,8 @@ begin
g_ep_rxbuf_size => 1024,
g_dpram_initf => "",
g_dpram_size => 94208/4,
g_aux_sdb => c_etherbone_sdb,
g_aux1_sdb => c_wrc_multiboot_sdb,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
......@@ -499,6 +516,9 @@ begin
aux_master_o => etherbone_cfg_in,
aux_master_i => etherbone_cfg_out,
aux1_master_o => multiboot_in,
aux1_master_i => multiboot_out,
wrf_src_o => etherbone_snk_in,
wrf_src_i => etherbone_snk_out,
wrf_snk_o => etherbone_src_in,
......@@ -628,8 +648,8 @@ begin
(
slave_clk_i => clk_sys,
slave_rst_n_i => local_reset_n,
slave_i => xbar_master_out(c_slv_multiboot),
slave_o => xbar_master_in(c_slv_multiboot),
slave_i => multiboot_in,
slave_o => multiboot_out,
master_clk_i => clk_20m_vcxo_buf,
master_rst_n_i => local_reset_n,
......
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