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Commit 52d64e77 authored by Maciej Lipinski's avatar Maciej Lipinski
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wr_streamers: cleanup only 

- added comments
- removed white spaces and unnecessary lines
- aligned text

NO FUNCTIONAL CHANGES
parent ce621186
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Showing with 200 additions and 181 deletions
modules/wr_streamers/fifo_showahead_adapter.vhd
View file @ 52d64e77
......@@ -76,7 +76,6 @@ begin
elsif rd_i = '1' then
valid_int <= not fifo_empty_i;
end if;
end if;
end if;
end process;
......
modules/wr_streamers/fixed_latency_delay.vhd
View file @ 52d64e77
......@@ -9,7 +9,7 @@
-- description:
--
-- This module delays incoming data until the configured fixed
-- latency
-- latency. The delayed data is stored in a dropping FIFO.
--
--
--------------------------------------------------------------------------------
......@@ -109,7 +109,6 @@ architecture rtl of fixed_latency_delay is
signal fifo_rd : std_logic;
signal dbuf_d : std_logic_vector(c_datapath_width-1 downto 0);
signal dbuf_q : std_logic_vector(c_datapath_width-1 downto 0);
signal fifo_q : std_logic_vector(c_datapath_width-1 downto 0);
......@@ -137,7 +136,6 @@ architecture rtl of fixed_latency_delay is
begin
U_SyncReset_to_RefClk : gc_sync_ffs
port map (
clk_i => clk_ref_i,
......@@ -145,9 +143,11 @@ begin
data_i => rst_n_i,
synced_o => rst_n_ref);
-- choose which clock to use as clk_data
clk_data <= clk_sys_i when g_use_ref_clock_for_data = 0 else clk_ref_i;
rst_n_data <= rst_n_i when g_use_ref_clock_for_data = 0 else rst_n_ref;
-- Pack input data to the FIFO in clk_sys_i clock domain
dbuf_d(g_data_width-1 downto 0) <= d_data_i;
dbuf_d(g_data_width) <= d_last_i;
dbuf_d(g_data_width+1) <= d_sync_i;
......@@ -156,7 +156,6 @@ begin
dbuf_d(g_data_width+3+28+39 downto g_data_width+3+28) <= d_target_ts_tai_i;
dbuf_d(g_data_width+3+28+40) <= d_target_ts_error_i;
U_DropBuffer : entity work.dropping_buffer
generic map (
g_size => g_buffer_size,
......@@ -193,6 +192,8 @@ begin
rd_i => fifo_rd,
rd_empty_o => fifo_empty);
-- FSM that controls the readout from the FIFO and the delaying of
-- exposing the data to the user.
p_fsm_seq: process(clk_data)
begin
if rising_edge(clk_data) then
......@@ -207,15 +208,14 @@ begin
fifo_valid <= '0';
end if;
case state is
-- wait for data to come
when IDLE =>
if fifo_empty = '0' then
state <= TS_SETUP_MATCH;
end if;
-- decide whether to delay the release of data or not, based on config
when TS_SETUP_MATCH =>
if fifo_valid = '1' then
if fifo_target_ts_en = '1' and fifo_target_ts_error = '0' then
......@@ -225,7 +225,7 @@ begin
end if;
end if;
-- wait for the correct time (fixed-delay per config)
when TS_WAIT_MATCH =>
if delay_miss_p = '1' or delay_match_p = '1' or delay_timeout_p = '1' then
if fifo_last = '1' and fifo_empty = '0' then
......@@ -236,22 +236,24 @@ begin
end if;
-- provide the data to the user
when SEND =>
if fifo_last = '1' and fifo_valid = '1' then
if fifo_empty = '1' then
state <= IDLE;
state <= IDLE; -- nothing in the FIFO
else
state <= TS_SETUP_MATCH;
state <= TS_SETUP_MATCH; -- new frame
end if;
elsif fifo_empty = '1' then
state <= IDLE;
state <= IDLE; -- nothing in the FIFO
end if;
end case;
end if;
end if;
end process;
-- the module that is used when fixed-delay is requested. In notifies
-- the FSM when the configured fixed-latency has expired.
U_Compare: entity work.fixed_latency_ts_match
generic map (
g_clk_ref_rate => g_clk_ref_rate,
......@@ -263,18 +265,27 @@ begin
clk_data_i => clk_data,
rst_ref_n_i => rst_n_ref,
rst_data_n_i => rst_n_data,
-- in clk_data (clk_sys_i or clk_ref_i) domain
arm_p_i => delay_arm_p,
ts_tai_i => fifo_target_ts_tai,
ts_cycles_i => fifo_target_ts_cycles,
-- in clk_sys_i domain
ts_latency_i => rx_streamer_cfg_i.fixed_latency,
ts_timeout_i => rx_streamer_cfg_i.fixed_latency_timeout,
-- in clk_ref_i domain
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
-- in clk_data (clk_sys_i or clk_ref_i) domain
timeout_p_o => delay_timeout_p,
match_p_o => delay_match_p,
late_p_o => delay_miss_p);
-- combinatorial part of the above FSM
p_fsm_comb: process(state, rx_dreq_i, fifo_empty, delay_miss_p, fifo_last, delay_match_p, delay_timeout_p, fifo_target_ts_en, fifo_valid)
begin
case state is
......@@ -286,7 +297,7 @@ begin
rx_timeout_o <= '0';
when TS_SETUP_MATCH =>
delay_arm_p <= fifo_valid and fifo_target_ts_en;
delay_arm_p <= fifo_valid and fifo_target_ts_en; --ML need to add "not fifo_target_ts_error"?
fifo_rd <= '0';
rx_valid <= '0';
rx_late_o <= '0';
......@@ -309,7 +320,9 @@ begin
end case;
end process;
-----------------------------------------------------------------------------
-- synchronize signals for stats counters that are in clk_sys_i domain
-----------------------------------------------------------------------------
U_Sync_RXMatch_Pulse : gc_pulse_synchronizer2
port map (
clk_in_i => clk_data,
......@@ -337,6 +350,7 @@ begin
d_p_i => delay_timeout_p,
q_p_o => stat_timeout_p1_o);
-- decode the data from FIFO in clk_data_i (clk_ref_i or clk_sys_i) domain
fifo_data <= fifo_q(g_data_width-1 downto 0);
fifo_last <= fifo_q(g_data_width);
fifo_sync <= fifo_q(g_data_width+1);
......@@ -345,13 +359,10 @@ begin
fifo_target_ts_tai <= fifo_q(g_data_width+3+28+39 downto g_data_width+3+28);
fifo_target_ts_error <= fifo_q(g_data_width+3+28+40);
-- signals that are outputs to the user
rx_data_o <= fifo_data;
rx_valid_o <= rx_valid;
rx_first_p1_o <= fifo_sync and rx_valid;
rx_last_p1_o <= fifo_last and rx_valid;
end rtl;
modules/wr_streamers/fixed_latency_ts_match.vhd
View file @ 52d64e77
......@@ -52,26 +52,26 @@ entity fixed_latency_ts_match is
port
(
clk_ref_i : in std_logic;
clk_data_i : in std_logic;
clk_data_i : in std_logic; -- either clk_sys_i or clk_ref_i
rst_ref_n_i : in std_logic;
rst_data_n_i : in std_logic;
-- in clk_data (clk_sys_i or clk_ref_i) domain
arm_p_i : in std_logic;
ts_tai_i : in std_logic_vector(39 downto 0);
ts_cycles_i : in std_logic_vector(27 downto 0);
-- in clk_sys_i domain
ts_latency_i : in std_logic_vector(27 downto 0);
ts_timeout_i : in std_logic_vector(27 downto 0);
-- Time valid flag
-- in clk_ref_i domain
tm_time_valid_i : in std_logic := '0';
-- TAI seconds
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
-- Fractional part of the second (in clk_ref_i cycles)
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
-- in clk_data (clk_sys_i or clk_ref_i) domain
match_p_o : out std_logic;
late_p_o : out std_logic;
timeout_p_o : out std_logic
......@@ -91,7 +91,6 @@ architecture rtl of fixed_latency_ts_match is
else
return g_sim_cycle_counter_range;
end if;
else
return 125000000;
end if;
......@@ -118,7 +117,6 @@ architecture rtl of fixed_latency_ts_match is
signal state : t_state;
signal trig : std_logic;
signal arm_synced_p, arm_synced_p_d : std_logic;
signal wait_cnt : unsigned(23 downto 0);
......@@ -132,7 +130,10 @@ begin
end if;
end process;
-- clk_ref_i domain: tm_cycles_i
-- sys_clk domain: ts_latency_i & ts_timeout_i
-- scale the cycle counts depending what clack is used as ref_clk.
-- The software input assumes 125MHz clock (8ns cycle).
process(tm_cycles_i, ts_latency_i, ts_timeout_i)
begin
if g_clk_ref_rate = 62500000 then
......@@ -148,7 +149,7 @@ begin
end if;
end process;
--ML: this seems unsed
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
......@@ -173,9 +174,16 @@ begin
end if;
end process;
------------------------------------------------------------------------------
-- FSM that always works in clk_ref_i domain because it compares the current
-- WR TAI/cycles value with the expected value whent the fixed-latency is
-- reached. It also handles the cases when
-- 1) it's already too late, in such case it notifies with late_o
-- 2) the latency was not achieved in a configured timeout amount of time,
-- in such case it notifies with timeout_p_o
-- If all goes well and the delayed TAI/cycles were reached, it notifes with
-- match_p_o
------------------------------------------------------------------------------
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
......@@ -192,6 +200,8 @@ begin
late <= '0';
timeout <= '0';
-- save the configuration when starting to receive frame to be
-- fixed-latency delayed
if arm_synced_p_d = '1' then
ts_adjusted_tai <= ts_adjusted_tai_latched;
ts_adjusted_cycles <= ts_adjusted_cycles_latched;
......@@ -201,13 +211,13 @@ begin
end if;
when WRAP_ADJ_TS =>
-- adjust TAI seconds if the delayed latency timestamp is in the next TAI second
if ts_adjusted_cycles >= f_cycles_counter_range then
ts_adjusted_cycles <= ts_adjusted_cycles - f_cycles_counter_range;
ts_adjusted_tai <= ts_adjusted_tai + 1;
end if;
-- adjust TAI seconds if the delayed timeout timestamp is in the next TAI second
if ts_timeout_cycles >= f_cycles_counter_range then
ts_timeout_cycles <= ts_timeout_cycles - f_cycles_counter_range;
ts_timeout_tai <= ts_timeout_tai + 1;
......@@ -215,14 +225,15 @@ begin
state <= CHECK_LATE;
when CHECK_LATE =>
when CHECK_LATE => -- handle all the late cases
-- if the time is temporarily incorrect, we assume we are late, send the info out
if tm_time_valid_i = '0' then
late <= '1';
state <= IDLE;
end if;
-- if we are in the future relateive to the delayed timestamp, we are definitely late
if ts_adjusted_tai < tm_tai_d then
late <= '1';
State <= IDLE;
......@@ -233,7 +244,7 @@ begin
State <= WAIT_TRIG;
end if;
when WAIT_TRIG =>
when WAIT_TRIG => -- wait for the correct timestamp for exposing the data, or timeout
if tm_tai_d > ts_timeout_tai or
(ts_timeout_tai = tm_tai_d and tm_cycles_scaled_d > ts_timeout_cycles) then
......@@ -241,7 +252,6 @@ begin
State <= IDLE;
end if;
if ts_adjusted_cycles = tm_cycles_scaled_d and ts_adjusted_tai = tm_tai_d then
match <= '1';
State <= IDLE;
......@@ -252,20 +262,20 @@ begin
end if;
end process;
------------------------------------------------------------------------------
-- clk_data_i == clk_ref_i | data is in the ref_clk domain
------------------------------------------------------------------------------
gen_data_synchronous_to_wr : if g_use_ref_clock_for_data /= 0 generate
match_p_o <= match;
late_p_o <= late;
timeout_p_o <= timeout;
arm_synced_p <= arm_p_i;
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
arm_synced_p_d <= arm_synced_p;
if arm_synced_p = '1' then
ts_adjusted_cycles_latched <= resize(unsigned(ts_cycles_i) + unsigned(ts_latency_scaled), 29);
ts_adjusted_tai_latched <= resize(unsigned(ts_tai_i), 40);
......@@ -277,6 +287,9 @@ begin
end generate;
------------------------------------------------------------------------------
-- clk_data_i != clk_ref_i | data is in the sys_clk domain
------------------------------------------------------------------------------
gen_data_asynchronous_to_wr : if g_use_ref_clock_for_data = 0 generate
U_Sync1: entity work.gc_pulse_synchronizer2
......@@ -330,9 +343,6 @@ begin
end if;
end if;
end process;
end generate;
end generate;
end rtl;
modules/wr_streamers/ts_restore_tai.vhd
View file @ 52d64e77
......@@ -123,7 +123,6 @@ begin
tm_tai_ref <= tm_tai_ref_d;
tm_valid_ref <= tm_valid_ref_d;
if tm_sample_cnt = g_tm_sample_period-1 then
tm_sample_p_ref <= '1';
tm_cycles_ref_d <= tm_cycles_i;
......@@ -189,10 +188,4 @@ begin
end if;
end process;
end rtl;
modules/wr_streamers/xrtx_streamers_stats.vhd
View file @ 52d64e77
......@@ -130,19 +130,14 @@ architecture rtl of xrtx_streamers_stats is
signal reset_time_tai : std_logic_vector(39 downto 0);
signal reset_time_cycles : std_logic_vector(27 downto 0);
-- signal sent_frame_cnt : unsigned(g_cnt_width-1 downto 0);
-- signal rcvd_frame_cnt : unsigned(g_cnt_width-1 downto 0);
-- signal lost_frame_cnt : unsigned(g_cnt_width-1 downto 0);
-- signal lost_block_cnt : unsigned(g_cnt_width-1 downto 0);
signal rx_stat_match_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal rx_stat_timeout_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal rx_stat_late_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
-- signal latency_cnt : unsigned(g_cnt_width-1 downto 0);
signal latency_max : std_logic_vector(27 downto 0);
signal latency_min : std_logic_vector(27 downto 0);
signal latency_acc : unsigned(g_acc_width-1+1 downto 0);
signal latency_acc_overflow: std_logic;
signal latency_acc_overflow : std_logic;
signal sent_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal rcvd_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
......
modules/wr_streamers/xrx_streamer.vhd
View file @ 52d64e77
......@@ -78,10 +78,17 @@ entity xrx_streamer is
-- in the future, more frequences might be supported..
g_clk_ref_rate : integer := 125000000;
-- indicate that we are simulating so that some processes can be made to take less
-- time, e.g. below
g_simulation : integer := 0;
-- shorten the duration of second to see TAI seconds for simulation only (i.e.
-- only if g_simulation = 1)
g_sim_cycle_counter_range : integer := 125000000;
-- when non-zero, the datapath (tx_/rx_ ports) are in the clk_ref_i clock
-- domain instead of clk_sys_i. This is a must for fixed latency mode if
-- clk_sys_i is asynchronous (i.e. not locked) to the WR timing.
g_use_ref_clock_for_data : integer := 0
);
......@@ -100,7 +107,6 @@ entity xrx_streamer is
-- Caution: uses clk_ref_i clock domain!
---------------------------------------------------------------------------
-- Time valid flag
tm_time_valid_i : in std_logic := '0';
......
modules/wr_streamers/xwr_streamers.vhd
View file @ 52d64e77
......@@ -99,7 +99,12 @@ entity xwr_streamers is
-----------------------------------------------------------------------------------------
g_slave_mode : t_wishbone_interface_mode := CLASSIC;
g_slave_granularity : t_wishbone_address_granularity := BYTE;
-- indicate that we are simulating so that some processes can be made to take less time
g_simulation : integer := 0;
-- shorten the duration of second to see TAI seconds for simulation only (i.e.
-- only if g_simulation = 1)
g_sim_cycle_counter_range : integer := 125000
);
......
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