Commit 52d64e77 authored by Maciej Lipinski's avatar Maciej Lipinski

wr_streamers: cleanup only

- added comments
- removed white spaces and unnecessary lines
- aligned text

NO FUNCTIONAL CHANGES
parent ce621186
...@@ -76,18 +76,17 @@ begin ...@@ -76,18 +76,17 @@ begin
elsif rd_i = '1' then elsif rd_i = '1' then
valid_int <= not fifo_empty_i; valid_int <= not fifo_empty_i;
end if; end if;
end if; end if;
end if; end if;
end process; end process;
rd <= not fifo_empty_i when valid_int = '0' else rd_i and not fifo_empty_i; rd <= not fifo_empty_i when valid_int = '0' else rd_i and not fifo_empty_i;
q_o <= fifo_q_i; q_o <= fifo_q_i;
fifo_rd_o <= rd; fifo_rd_o <= rd;
valid_o <= valid_int; valid_o <= valid_int;
end rtl; end rtl;
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
-- description: -- description:
-- --
-- This module delays incoming data until the configured fixed -- This module delays incoming data until the configured fixed
-- latency -- latency. The delayed data is stored in a dropping FIFO.
-- --
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -109,7 +109,6 @@ architecture rtl of fixed_latency_delay is ...@@ -109,7 +109,6 @@ architecture rtl of fixed_latency_delay is
signal fifo_rd : std_logic; signal fifo_rd : std_logic;
signal dbuf_d : std_logic_vector(c_datapath_width-1 downto 0); signal dbuf_d : std_logic_vector(c_datapath_width-1 downto 0);
signal dbuf_q : std_logic_vector(c_datapath_width-1 downto 0); signal dbuf_q : std_logic_vector(c_datapath_width-1 downto 0);
signal fifo_q : std_logic_vector(c_datapath_width-1 downto 0); signal fifo_q : std_logic_vector(c_datapath_width-1 downto 0);
...@@ -134,9 +133,8 @@ architecture rtl of fixed_latency_delay is ...@@ -134,9 +133,8 @@ architecture rtl of fixed_latency_delay is
signal clk_data : std_logic; signal clk_data : std_logic;
signal rst_n_data : std_logic; signal rst_n_data : std_logic;
begin
begin
U_SyncReset_to_RefClk : gc_sync_ffs U_SyncReset_to_RefClk : gc_sync_ffs
port map ( port map (
...@@ -145,18 +143,19 @@ begin ...@@ -145,18 +143,19 @@ begin
data_i => rst_n_i, data_i => rst_n_i,
synced_o => rst_n_ref); synced_o => rst_n_ref);
-- choose which clock to use as clk_data
clk_data <= clk_sys_i when g_use_ref_clock_for_data = 0 else clk_ref_i; clk_data <= clk_sys_i when g_use_ref_clock_for_data = 0 else clk_ref_i;
rst_n_data <= rst_n_i when g_use_ref_clock_for_data = 0 else rst_n_ref; rst_n_data <= rst_n_i when g_use_ref_clock_for_data = 0 else rst_n_ref;
dbuf_d(g_data_width-1 downto 0) <= d_data_i; -- Pack input data to the FIFO in clk_sys_i clock domain
dbuf_d(g_data_width) <= d_last_i; dbuf_d(g_data_width-1 downto 0) <= d_data_i;
dbuf_d(g_data_width+1) <= d_sync_i; dbuf_d(g_data_width) <= d_last_i;
dbuf_d(g_data_width+2) <= d_target_ts_en_i; dbuf_d(g_data_width+1) <= d_sync_i;
dbuf_d(g_data_width+2) <= d_target_ts_en_i;
dbuf_d(g_data_width+3+27 downto g_data_width+3) <= d_target_ts_cycles_i; dbuf_d(g_data_width+3+27 downto g_data_width+3) <= d_target_ts_cycles_i;
dbuf_d(g_data_width+3+28+39 downto g_data_width+3+28) <= d_target_ts_tai_i; dbuf_d(g_data_width+3+28+39 downto g_data_width+3+28) <= d_target_ts_tai_i;
dbuf_d(g_data_width+3+28+40) <= d_target_ts_error_i; dbuf_d(g_data_width+3+28+40) <= d_target_ts_error_i;
U_DropBuffer : entity work.dropping_buffer U_DropBuffer : entity work.dropping_buffer
generic map ( generic map (
g_size => g_buffer_size, g_size => g_buffer_size,
...@@ -175,7 +174,7 @@ begin ...@@ -175,7 +174,7 @@ begin
d_req_i => dbuf_req); d_req_i => dbuf_req);
dbuf_req <= not wr_full; dbuf_req <= not wr_full;
fifo_we <= dbuf_q_valid and not wr_full; fifo_we <= dbuf_q_valid and not wr_full;
U_ClockSyncFifo : generic_async_fifo U_ClockSyncFifo : generic_async_fifo
generic map ( generic map (
...@@ -193,6 +192,8 @@ begin ...@@ -193,6 +192,8 @@ begin
rd_i => fifo_rd, rd_i => fifo_rd,
rd_empty_o => fifo_empty); rd_empty_o => fifo_empty);
-- FSM that controls the readout from the FIFO and the delaying of
-- exposing the data to the user.
p_fsm_seq: process(clk_data) p_fsm_seq: process(clk_data)
begin begin
if rising_edge(clk_data) then if rising_edge(clk_data) then
...@@ -207,15 +208,14 @@ begin ...@@ -207,15 +208,14 @@ begin
fifo_valid <= '0'; fifo_valid <= '0';
end if; end if;
case state is case state is
-- wait for data to come
when IDLE => when IDLE =>
if fifo_empty = '0' then if fifo_empty = '0' then
state <= TS_SETUP_MATCH; state <= TS_SETUP_MATCH;
end if; end if;
-- decide whether to delay the release of data or not, based on config
when TS_SETUP_MATCH => when TS_SETUP_MATCH =>
if fifo_valid = '1' then if fifo_valid = '1' then
if fifo_target_ts_en = '1' and fifo_target_ts_error = '0' then if fifo_target_ts_en = '1' and fifo_target_ts_error = '0' then
...@@ -225,7 +225,7 @@ begin ...@@ -225,7 +225,7 @@ begin
end if; end if;
end if; end if;
-- wait for the correct time (fixed-delay per config)
when TS_WAIT_MATCH => when TS_WAIT_MATCH =>
if delay_miss_p = '1' or delay_match_p = '1' or delay_timeout_p = '1' then if delay_miss_p = '1' or delay_match_p = '1' or delay_timeout_p = '1' then
if fifo_last = '1' and fifo_empty = '0' then if fifo_last = '1' and fifo_empty = '0' then
...@@ -236,80 +236,93 @@ begin ...@@ -236,80 +236,93 @@ begin
end if; end if;
-- provide the data to the user
when SEND => when SEND =>
if fifo_last = '1' and fifo_valid = '1' then if fifo_last = '1' and fifo_valid = '1' then
if fifo_empty = '1' then if fifo_empty = '1' then
state <= IDLE; state <= IDLE; -- nothing in the FIFO
else else
state <= TS_SETUP_MATCH; state <= TS_SETUP_MATCH; -- new frame
end if; end if;
elsif fifo_empty = '1' then elsif fifo_empty = '1' then
state <= IDLE; state <= IDLE; -- nothing in the FIFO
end if; end if;
end case; end case;
end if; end if;
end if; end if;
end process; end process;
-- the module that is used when fixed-delay is requested. In notifies
-- the FSM when the configured fixed-latency has expired.
U_Compare: entity work.fixed_latency_ts_match U_Compare: entity work.fixed_latency_ts_match
generic map ( generic map (
g_clk_ref_rate => g_clk_ref_rate, g_clk_ref_rate => g_clk_ref_rate,
g_sim_cycle_counter_range => g_sim_cycle_counter_range, g_sim_cycle_counter_range => g_sim_cycle_counter_range,
g_simulation => g_simulation, g_simulation => g_simulation,
g_use_ref_clock_for_data => g_use_ref_clock_for_data) g_use_ref_clock_for_data => g_use_ref_clock_for_data)
port map ( port map (
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
clk_data_i => clk_data, clk_data_i => clk_data,
rst_ref_n_i => rst_n_ref, rst_ref_n_i => rst_n_ref,
rst_data_n_i => rst_n_data, rst_data_n_i => rst_n_data,
arm_p_i => delay_arm_p,
-- in clk_data (clk_sys_i or clk_ref_i) domain
arm_p_i => delay_arm_p,
ts_tai_i => fifo_target_ts_tai, ts_tai_i => fifo_target_ts_tai,
ts_cycles_i => fifo_target_ts_cycles, ts_cycles_i => fifo_target_ts_cycles,
-- in clk_sys_i domain
ts_latency_i => rx_streamer_cfg_i.fixed_latency, ts_latency_i => rx_streamer_cfg_i.fixed_latency,
ts_timeout_i => rx_streamer_cfg_i.fixed_latency_timeout, ts_timeout_i => rx_streamer_cfg_i.fixed_latency_timeout,
-- in clk_ref_i domain
tm_time_valid_i => tm_time_valid_i, tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i, tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i, tm_cycles_i => tm_cycles_i,
timeout_p_o => delay_timeout_p,
match_p_o => delay_match_p,
late_p_o => delay_miss_p);
-- in clk_data (clk_sys_i or clk_ref_i) domain
timeout_p_o => delay_timeout_p,
match_p_o => delay_match_p,
late_p_o => delay_miss_p);
-- combinatorial part of the above FSM
p_fsm_comb: process(state, rx_dreq_i, fifo_empty, delay_miss_p, fifo_last, delay_match_p, delay_timeout_p, fifo_target_ts_en, fifo_valid) p_fsm_comb: process(state, rx_dreq_i, fifo_empty, delay_miss_p, fifo_last, delay_match_p, delay_timeout_p, fifo_target_ts_en, fifo_valid)
begin begin
case state is case state is
when IDLE => when IDLE =>
delay_arm_p <= '0'; delay_arm_p <= '0';
fifo_rd <= not fifo_empty; fifo_rd <= not fifo_empty;
rx_valid <= '0'; rx_valid <= '0';
rx_late_o <= '0'; rx_late_o <= '0';
rx_timeout_o <= '0'; rx_timeout_o <= '0';
when TS_SETUP_MATCH => when TS_SETUP_MATCH =>
delay_arm_p <= fifo_valid and fifo_target_ts_en; delay_arm_p <= fifo_valid and fifo_target_ts_en; --ML need to add "not fifo_target_ts_error"?
fifo_rd <= '0'; fifo_rd <= '0';
rx_valid <= '0'; rx_valid <= '0';
rx_late_o <= '0'; rx_late_o <= '0';
rx_timeout_o <= '0'; rx_timeout_o <= '0';
when TS_WAIT_MATCH => when TS_WAIT_MATCH =>
delay_arm_p <= '0'; delay_arm_p <= '0';
fifo_rd <= (delay_match_p or delay_miss_p or delay_timeout_p) and not fifo_empty; fifo_rd <= (delay_match_p or delay_miss_p or delay_timeout_p) and not fifo_empty;
rx_valid <= delay_match_p or delay_miss_p; rx_valid <= delay_match_p or delay_miss_p;
rx_late_o <= delay_miss_p; rx_late_o <= delay_miss_p;
rx_timeout_o <= delay_timeout_p; rx_timeout_o <= delay_timeout_p;
when SEND => when SEND =>
delay_arm_p <= '0'; delay_arm_p <= '0';
fifo_rd <= (rx_dreq_i or (fifo_last and fifo_valid)) and not fifo_empty; fifo_rd <= (rx_dreq_i or (fifo_last and fifo_valid)) and not fifo_empty;
rx_valid <= fifo_valid; rx_valid <= fifo_valid;
rx_late_o <= '0'; rx_late_o <= '0';
rx_timeout_o <= '0'; rx_timeout_o <= '0';
end case; end case;
end process; end process;
-----------------------------------------------------------------------------
-- synchronize signals for stats counters that are in clk_sys_i domain
-----------------------------------------------------------------------------
U_Sync_RXMatch_Pulse : gc_pulse_synchronizer2 U_Sync_RXMatch_Pulse : gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_data, clk_in_i => clk_data,
...@@ -327,7 +340,7 @@ begin ...@@ -327,7 +340,7 @@ begin
rst_out_n_i => rst_n_i, rst_out_n_i => rst_n_i,
d_p_i => delay_miss_p, d_p_i => delay_miss_p,
q_p_o => stat_late_p1_o); q_p_o => stat_late_p1_o);
U_Sync_RXTimeout_Pulse : gc_pulse_synchronizer2 U_Sync_RXTimeout_Pulse : gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_data, clk_in_i => clk_data,
...@@ -337,21 +350,19 @@ begin ...@@ -337,21 +350,19 @@ begin
d_p_i => delay_timeout_p, d_p_i => delay_timeout_p,
q_p_o => stat_timeout_p1_o); q_p_o => stat_timeout_p1_o);
fifo_data <= fifo_q(g_data_width-1 downto 0); -- decode the data from FIFO in clk_data_i (clk_ref_i or clk_sys_i) domain
fifo_last <= fifo_q(g_data_width); fifo_data <= fifo_q(g_data_width-1 downto 0);
fifo_sync <= fifo_q(g_data_width+1); fifo_last <= fifo_q(g_data_width);
fifo_target_ts_en <= fifo_q(g_data_width+2); fifo_sync <= fifo_q(g_data_width+1);
fifo_target_ts_en <= fifo_q(g_data_width+2);
fifo_target_ts_cycles <= fifo_q(g_data_width+3+27 downto g_data_width+3); fifo_target_ts_cycles <= fifo_q(g_data_width+3+27 downto g_data_width+3);
fifo_target_ts_tai <= fifo_q(g_data_width+3+28+39 downto g_data_width+3+28); fifo_target_ts_tai <= fifo_q(g_data_width+3+28+39 downto g_data_width+3+28);
fifo_target_ts_error <= fifo_q(g_data_width+3+28+40); fifo_target_ts_error <= fifo_q(g_data_width+3+28+40);
-- signals that are outputs to the user
rx_data_o <= fifo_data; rx_data_o <= fifo_data;
rx_valid_o <= rx_valid; rx_valid_o <= rx_valid;
rx_first_p1_o <= fifo_sync and rx_valid; rx_first_p1_o <= fifo_sync and rx_valid;
rx_last_p1_o <= fifo_last and rx_valid; rx_last_p1_o <= fifo_last and rx_valid;
end rtl; end rtl;
...@@ -123,7 +123,6 @@ begin ...@@ -123,7 +123,6 @@ begin
tm_tai_ref <= tm_tai_ref_d; tm_tai_ref <= tm_tai_ref_d;
tm_valid_ref <= tm_valid_ref_d; tm_valid_ref <= tm_valid_ref_d;
if tm_sample_cnt = g_tm_sample_period-1 then if tm_sample_cnt = g_tm_sample_period-1 then
tm_sample_p_ref <= '1'; tm_sample_p_ref <= '1';
tm_cycles_ref_d <= tm_cycles_i; tm_cycles_ref_d <= tm_cycles_i;
...@@ -189,10 +188,4 @@ begin ...@@ -189,10 +188,4 @@ begin
end if; end if;
end process; end process;
end rtl; end rtl;
...@@ -127,22 +127,17 @@ end xrtx_streamers_stats; ...@@ -127,22 +127,17 @@ end xrtx_streamers_stats;
architecture rtl of xrtx_streamers_stats is architecture rtl of xrtx_streamers_stats is
signal reset_time_tai : std_logic_vector(39 downto 0); signal reset_time_tai : std_logic_vector(39 downto 0);
signal reset_time_cycles : std_logic_vector(27 downto 0); signal reset_time_cycles : std_logic_vector(27 downto 0);
-- signal sent_frame_cnt : unsigned(g_cnt_width-1 downto 0); signal rx_stat_match_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
-- signal rcvd_frame_cnt : unsigned(g_cnt_width-1 downto 0); signal rx_stat_timeout_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
-- signal lost_frame_cnt : unsigned(g_cnt_width-1 downto 0); signal rx_stat_late_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
-- signal lost_block_cnt : unsigned(g_cnt_width-1 downto 0);
signal rx_stat_match_cnt_out : std_logic_vector(g_cnt_width-1 downto 0); signal latency_max : std_logic_vector(27 downto 0);
signal rx_stat_timeout_cnt_out : std_logic_vector(g_cnt_width-1 downto 0); signal latency_min : std_logic_vector(27 downto 0);
signal rx_stat_late_cnt_out : std_logic_vector(g_cnt_width-1 downto 0); signal latency_acc : unsigned(g_acc_width-1+1 downto 0);
-- signal latency_cnt : unsigned(g_cnt_width-1 downto 0); signal latency_acc_overflow : std_logic;
signal latency_max : std_logic_vector(27 downto 0);
signal latency_min : std_logic_vector(27 downto 0);
signal latency_acc : unsigned(g_acc_width-1+1 downto 0);
signal latency_acc_overflow: std_logic;
signal sent_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0); signal sent_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal rcvd_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0); signal rcvd_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
...@@ -167,7 +162,7 @@ architecture rtl of xrtx_streamers_stats is ...@@ -167,7 +162,7 @@ architecture rtl of xrtx_streamers_stats is
signal snapshot_remote_ena : std_logic; signal snapshot_remote_ena : std_logic;
signal snapshot_ena : std_logic; signal snapshot_ena : std_logic;
signal snapshot_ena_d1 : std_logic; signal snapshot_ena_d1 : std_logic;
-- for code cleanness -- for code cleanness
constant c_cw : integer := g_cnt_width; constant c_cw : integer := g_cnt_width;
constant c_aw : integer := g_acc_width; constant c_aw : integer := g_acc_width;
......
...@@ -78,10 +78,17 @@ entity xrx_streamer is ...@@ -78,10 +78,17 @@ entity xrx_streamer is
-- in the future, more frequences might be supported.. -- in the future, more frequences might be supported..
g_clk_ref_rate : integer := 125000000; g_clk_ref_rate : integer := 125000000;
-- indicate that we are simulating so that some processes can be made to take less
-- time, e.g. below
g_simulation : integer := 0; g_simulation : integer := 0;
-- shorten the duration of second to see TAI seconds for simulation only (i.e.
-- only if g_simulation = 1)
g_sim_cycle_counter_range : integer := 125000000; g_sim_cycle_counter_range : integer := 125000000;
-- when non-zero, the datapath (tx_/rx_ ports) are in the clk_ref_i clock
-- domain instead of clk_sys_i. This is a must for fixed latency mode if
-- clk_sys_i is asynchronous (i.e. not locked) to the WR timing.
g_use_ref_clock_for_data : integer := 0 g_use_ref_clock_for_data : integer := 0
); );
...@@ -100,7 +107,6 @@ entity xrx_streamer is ...@@ -100,7 +107,6 @@ entity xrx_streamer is
-- Caution: uses clk_ref_i clock domain! -- Caution: uses clk_ref_i clock domain!
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Time valid flag -- Time valid flag
tm_time_valid_i : in std_logic := '0'; tm_time_valid_i : in std_logic := '0';
......
...@@ -47,7 +47,7 @@ use work.wrcore_pkg.all; -- needed for t_generic_word_array ...@@ -47,7 +47,7 @@ use work.wrcore_pkg.all; -- needed for t_generic_word_array
-- use work.wr_transmission_wbgen2_pkg.all; -- use work.wr_transmission_wbgen2_pkg.all;
entity xtx_streamers_stats is entity xtx_streamers_stats is
generic ( generic (
-- Width of frame counters -- Width of frame counters
g_cnt_width : integer := 32 -- minimum 15 bits, max 32 g_cnt_width : integer := 32 -- minimum 15 bits, max 32
...@@ -68,7 +68,7 @@ entity xtx_streamers_stats is ...@@ -68,7 +68,7 @@ entity xtx_streamers_stats is
); );
end xtx_streamers_stats; end xtx_streamers_stats;
architecture rtl of xtx_streamers_stats is architecture rtl of xtx_streamers_stats is
signal sent_frame_cnt : unsigned(g_cnt_width-1 downto 0); signal sent_frame_cnt : unsigned(g_cnt_width-1 downto 0);
......
...@@ -80,7 +80,7 @@ entity xwr_streamers is ...@@ -80,7 +80,7 @@ entity xwr_streamers is
-- domain instead of clk_sys_i. This is a must for fixed latency mode if -- domain instead of clk_sys_i. This is a must for fixed latency mode if
-- clk_sys_i is asynchronous (i.e. not locked) to the WR timing. -- clk_sys_i is asynchronous (i.e. not locked) to the WR timing.
g_use_ref_clock_for_data : integer := 0; g_use_ref_clock_for_data : integer := 0;
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
-- Transmission/reception parameters -- Transmission/reception parameters
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
...@@ -99,8 +99,13 @@ entity xwr_streamers is ...@@ -99,8 +99,13 @@ entity xwr_streamers is
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
g_slave_mode : t_wishbone_interface_mode := CLASSIC; g_slave_mode : t_wishbone_interface_mode := CLASSIC;
g_slave_granularity : t_wishbone_address_granularity := BYTE; g_slave_granularity : t_wishbone_address_granularity := BYTE;
-- indicate that we are simulating so that some processes can be made to take less time
g_simulation : integer := 0; g_simulation : integer := 0;
g_sim_cycle_counter_range : integer := 125000
-- shorten the duration of second to see TAI seconds for simulation only (i.e.
-- only if g_simulation = 1)
g_sim_cycle_counter_range : integer := 125000
); );
port ( port (
......
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