[cute/top] added synchronizer bringing pll_aux_locked to clk_pll_125m clock domain

It seems that pll_aux_locked is in clk_sys clock domain. When synthesising cute for BTrain I had timing errors in the 10MHz generation process. This commit fixes the timing issues.

[cute/top] added synchronizer bringing pll_aux_locked to clk_pll_125m clock domain
It seems that pll_aux_locked is in clk_sys clock domain. When synthesising cute for BTrain I had timing errors in the 10MHz generation process. This commit fixes the timing issues.
5186a12f · Maciej Lipinski · fdc5cff4 · 5186a12f
Commit 5186a12f authored Apr 02, 2020 by Maciej Lipinski
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Showing with 14 additions and 3 deletions

xwrc_board_cute.vhd board/cute/xwrc_board_cute.vhd +14 -3

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--- a/board/cute/xwrc_board_cute.vhd
+++ b/board/cute/xwrc_board_cute.vhd
@@ -414,7 +414,9 @@ architecture struct of xwrc_board_cute is

  signal multiboot_wb_out  : t_wishbone_master_out;
  signal multiboot_wb_in   : t_wishbone_master_in;
-  
+
+  signal clk_pll_aux_locked : std_logic;
+
 begin  -- architecture struct

  -----------------------------------------------------------------------------
@@ -759,10 +761,19 @@ end generate;
  rst_oserdes   <= not pll_aux_locked;
  clk_10m_ext_o <= sd_out(0);

+  cmp_pll_aux_locked: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_pll_125m,
+      rst_n_i  => rstlogic_rst_out(1),
+      data_i   => pll_aux_locked,
+      synced_o => clk_pll_aux_locked);
+
  process(clk_pll_125m)
  begin
    if rising_edge(clk_pll_125m) then
-      if(rstlogic_rst_out(1) = '0' or pll_aux_locked = '0') then
+      if(rstlogic_rst_out(1) = '0' or clk_pll_aux_locked = '0') then
        tm_time_valid_d1 <= '0';
      elsif(pps_csync = '1') then
        tm_time_valid_d1 <= tm_time_valid;
@@ -776,7 +787,7 @@ end generate;
    variable v_bit : std_logic;
  begin
    if rising_edge(clk_pll_125m) then
-      if (rstlogic_rst_out(1)='0' or pll_aux_locked='0' or clk_realign='1') then
+      if (rstlogic_rst_out(1)='0' or clk_pll_aux_locked='0' or clk_realign='1') then
          rest := to_integer(aux_half_high - aux_shift);
          v_bit := '1';
      else