Commit 4e5e3dfc authored by Miguel Jimenez Lopez's avatar Miguel Jimenez Lopez

wr_nic_wrapper: Fix indentation.

parent f0519a1f
......@@ -50,46 +50,46 @@ entity wr_nic_wrapper is
g_num_irqs : integer := 3;
-- Number of ports for the TxTSU module
g_num_ports : integer := 1
);
);
port(
---------------------------------------------------------------------------
-- Global ports (Clocks & Resets)
---------------------------------------------------------------------------
-- System clock
clk_sys_i : in std_logic;
clk_sys_i : in std_logic;
-- Global reset (active low)
resetn_i : in std_logic;
resetn_i : in std_logic;
---------------------------------------------------------------------------
-- External WB slave interface
---------------------------------------------------------------------------
ext_slave_i : in t_wishbone_slave_in;
ext_slave_o : out t_wishbone_slave_out;
ext_slave_i : in t_wishbone_slave_in;
ext_slave_o : out t_wishbone_slave_out;
---------------------------------------------------------------------------
-- NIC fabric data buses
---------------------------------------------------------------------------
nic_snk_i : in t_wrf_sink_in;
nic_snk_o : out t_wrf_sink_out;
nic_src_i : in t_wrf_source_in;
nic_src_o : out t_wrf_source_out;
nic_snk_i : in t_wrf_sink_in;
nic_snk_o : out t_wrf_sink_out;
nic_src_i : in t_wrf_source_in;
nic_src_o : out t_wrf_source_out;
-- PPS-related signal for NIC core
pps_p_i : in std_logic := '0';
pps_valid_i : in std_logic := '0';
pps_p_i : in std_logic := '0';
pps_valid_i : in std_logic := '0';
---------------------------------------------------------------------------
-- VIC ports (peripheral interrupts lines and global interrupt output)
---------------------------------------------------------------------------
vic_irqs_i : in std_logic_vector(g_num_irqs-1 downto 0);
vic_int_o : out std_logic;
vic_irqs_i : in std_logic_vector(g_num_irqs-1 downto 0);
vic_int_o : out std_logic;
---------------------------------------------------------------------------
-- TxTSU ports (Timestamp trigger and acknowlegdement signal)
---------------------------------------------------------------------------
txtsu_timestamps_i : in t_txtsu_timestamp_array(g_num_ports-1 downto 0);
txtsu_timestamps_ack_o : out std_logic_vector(g_num_ports -1 downto 0)
);
);
end entity wr_nic_wrapper;
architecture struct of wr_nic_wrapper is
......@@ -98,24 +98,24 @@ architecture struct of wr_nic_wrapper is
-----------------------------------------------------------------------------
-- NIC constants
constant c_NIC_INTERFACE_MODE : t_wishbone_interface_mode := PIPELINED;
constant c_NIC_INTERFACE_MODE : t_wishbone_interface_mode := PIPELINED;
constant c_NIC_ADDRESS_GRANULARITY : t_wishbone_address_granularity := BYTE;
constant c_NIC_SRC_CYC_ON_STALL : boolean := true;
constant c_NIC_PORT_MASK_BITS : integer := g_num_ports+1;
constant c_NIC_RMON_EVENTS_PP : integer := 1;
constant c_NIC_SRC_CYC_ON_STALL : boolean := true;
constant c_NIC_PORT_MASK_BITS : integer := g_num_ports+1;
constant c_NIC_RMON_EVENTS_PP : integer := 1;
-- VIC constants
constant c_VIC_INTERFACE_MODE : t_wishbone_interface_mode := PIPELINED;
constant c_VIC_INTERFACE_MODE : t_wishbone_interface_mode := PIPELINED;
constant c_VIC_ADDRESS_GRANULARITY : t_wishbone_address_granularity := BYTE;
constant c_VIC_EXTRA_IRQS : integer := 3;
constant c_VIC_NUM_IRQS : integer := g_num_irqs+c_VIC_EXTRA_IRQS;
constant c_VIC_IRQ_TXTSU : integer := 0;
constant c_VIC_IRQ_NIC : integer := 1;
constant c_VIC_IRQ_PPS : integer := 2;
constant c_VIC_EXTRA_IRQS : integer := 3;
constant c_VIC_NUM_IRQS : integer := g_num_irqs+c_VIC_EXTRA_IRQS;
constant c_VIC_IRQ_TXTSU : integer := 0;
constant c_VIC_IRQ_NIC : integer := 1;
constant c_VIC_IRQ_PPS : integer := 2;
-- TxTSU constants
constant c_TXTSU_NUM_PORTS : integer := g_num_ports;
constant c_TXTSU_INTERFACE_MODE : t_wishbone_interface_mode := PIPELINED;
constant c_TXTSU_NUM_PORTS : integer := g_num_ports;
constant c_TXTSU_INTERFACE_MODE : t_wishbone_interface_mode := PIPELINED;
constant c_TXTSU_ADDRESS_GRANULARITY : t_wishbone_address_granularity := BYTE;
-----------------------------------------------------------------------------
......@@ -147,12 +147,12 @@ begin -- architecture struct
g_layout => c_nic_wrapper_xbar_layout,
g_sdb_addr => c_nic_wrapper_xbar_sdb_address)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => resetn_i,
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
master_i => cbar_master_i,
master_o => cbar_master_o);
clk_sys_i => clk_sys_i,
rst_n_i => resetn_i,
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
master_i => cbar_master_i,
master_o => cbar_master_o);
-- Assign slave interface of the WB crossbar to external port
cbar_slave_i(c_NIC_WRAPPER_XBAR_MASTER_EXT) <= ext_slave_i;
......@@ -163,15 +163,15 @@ begin -- architecture struct
-----------------------------------------------------------------------------
cmp_nic : xwr_nic
generic map(
g_interface_mode => c_NIC_INTERFACE_MODE,
g_address_granularity => c_NIC_ADDRESS_GRANULARITY,
g_src_cyc_on_stall => c_NIC_SRC_CYC_ON_STALL,
g_port_mask_bits => c_NIC_PORT_MASK_BITS,
g_rmon_events_pp => c_NIC_RMON_EVENTS_PP)
g_interface_mode => c_NIC_INTERFACE_MODE,
g_address_granularity => c_NIC_ADDRESS_GRANULARITY,
g_src_cyc_on_stall => c_NIC_SRC_CYC_ON_STALL,
g_port_mask_bits => c_NIC_PORT_MASK_BITS,
g_rmon_events_pp => c_NIC_RMON_EVENTS_PP)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => resetn_i,
pps_p_i => pps_p_i,
pps_p_i => pps_p_i,
pps_valid_i => pps_valid_i,
snk_i => nic_snk_i,
snk_o => nic_snk_o,
......@@ -203,9 +203,9 @@ begin -- architecture struct
irqs_i => vic_vec_int_i,
irq_master_o => vic_int_o);
vic_vec_int_i(c_VIC_IRQ_TXTSU) <= txtsu_int;
vic_vec_int_i(c_VIC_IRQ_NIC) <= nic_int;
vic_vec_int_i(c_VIC_IRQ_PPS) <= pps_p_i;
vic_vec_int_i(c_VIC_IRQ_TXTSU) <= txtsu_int;
vic_vec_int_i(c_VIC_IRQ_NIC) <= nic_int;
vic_vec_int_i(c_VIC_IRQ_PPS) <= pps_p_i;
vic_vec_int_i(c_VIC_NUM_IRQS-1 downto c_VIC_EXTRA_IRQS) <= vic_irqs_i;
-----------------------------------------------------------------------------
......@@ -217,12 +217,12 @@ begin -- architecture struct
g_interface_mode => c_TXTSU_INTERFACE_MODE,
g_address_granularity => c_TXTSU_ADDRESS_GRANULARITY)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => resetn_i,
timestamps_i => txtsu_timestamps_i,
timestamps_ack_o => txtsu_timestamps_ack_o,
wb_i => cbar_master_o(c_NIC_WRAPPER_XBAR_SLAVE_TXTSU),
wb_o => cbar_master_i(c_NIC_WRAPPER_XBAR_SLAVE_TXTSU),
int_o => txtsu_int);
clk_sys_i => clk_sys_i,
rst_n_i => resetn_i,
timestamps_i => txtsu_timestamps_i,
timestamps_ack_o => txtsu_timestamps_ack_o,
wb_i => cbar_master_o(c_NIC_WRAPPER_XBAR_SLAVE_TXTSU),
wb_o => cbar_master_i(c_NIC_WRAPPER_XBAR_SLAVE_TXTSU),
int_o => txtsu_int);
end architecture struct;
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