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White Rabbit core collection
Commit 48f04c06 authored by A. Hahn's avatar A. Hahn
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ftm4: added phy stuff

parent fc654127
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platform/altera/wr_altera_pkg.vhd
View file @ 48f04c06
......@@ -434,6 +434,90 @@ package wr_altera_pkg is
);
end component wr_arria10_scu4_phy;
component wr_arria10_ftm4_det_phy is
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
reconfig_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
rx_cdr_refclk0 : in std_logic := 'X'; -- clk
rx_clkout : out std_logic_vector(0 downto 0); -- clk
rx_coreclkin : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
rx_datak : out std_logic; -- rx_datak
rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
rx_disperr : out std_logic; -- rx_disperr
rx_errdetect : out std_logic; -- rx_errdetect
rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(7 downto 0); -- rx_parallel_data
rx_patterndetect : out std_logic; -- rx_patterndetect
rx_runningdisp : out std_logic; -- rx_runningdisp
rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
rx_std_bitslipboundarysel : out std_logic_vector(4 downto 0); -- rx_std_bitslipboundarysel
rx_std_wa_patternalign : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_std_wa_patternalign
rx_syncstatus : out std_logic; -- rx_syncstatus
tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
tx_clkout : out std_logic_vector(0 downto 0); -- clk
tx_coreclkin : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
tx_datak : in std_logic := 'X'; -- tx_datak
tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
tx_parallel_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- tx_parallel_data
tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
unused_rx_parallel_data : out std_logic_vector(113 downto 0); -- unused_rx_parallel_data
unused_tx_parallel_data : in std_logic_vector(118 downto 0) := (others => 'X'); -- unused_tx_parallel_data
rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => 'X') -- rx_seriallpbken
);
end component wr_arria10_ftm4_det_phy;
component wr_arria10_ftm4_transceiver is
generic (
g_use_atx_pll : boolean := TRUE);
port (
clk_ref_i : in std_logic := '0';
tx_clk_o : out std_logic;
tx_data_i : in std_logic_vector(7 downto 0):= (others => '0');
rx_clk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0'
);
end component wr_arria10_ftm4_transceiver;
component wr_arria10_ftm4_phy is
port (
rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X');
rx_cal_busy : out std_logic_vector(0 downto 0);
rx_cdr_refclk0 : in std_logic := 'X';
rx_clkout : out std_logic_vector(0 downto 0);
rx_coreclkin : in std_logic_vector(0 downto 0) := (others => 'X');
rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X');
rx_is_lockedtodata : out std_logic_vector(0 downto 0);
rx_is_lockedtoref : out std_logic_vector(0 downto 0);
rx_parallel_data : out std_logic_vector(7 downto 0);
rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X');
tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X');
tx_cal_busy : out std_logic_vector(0 downto 0);
tx_clkout : out std_logic_vector(0 downto 0);
tx_coreclkin : in std_logic_vector(0 downto 0) := (others => 'X');
tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X');
tx_parallel_data : in std_logic_vector(7 downto 0) := (others => 'X');
tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => 'X');
tx_serial_data : out std_logic_vector(0 downto 0);
--rx_set_locktodata : in std_logic_vector(0 downto 0) := (others => 'X');
--rx_set_locktoref : in std_logic_vector(0 downto 0) := (others => 'X');
unused_tx_parallel_data : in std_logic_vector(119 downto 0) := (others => 'X');
unused_rx_parallel_data : out std_logic_vector(119 downto 0)
);
end component wr_arria10_ftm4_phy;
component wr_arria10_pex10_det_phy is
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
......@@ -652,6 +736,26 @@ package wr_altera_pkg is
);
end component wr_arria10_scu4_cmu_pll;
component wr_arria10_ftm4_atx_pll is
port (
pll_refclk0 : in std_logic := 'X';
pll_powerdown : in std_logic := 'X';
pll_locked : out std_logic;
tx_serial_clk : out std_logic;
pll_cal_busy : out std_logic
);
end component wr_arria10_ftm4_atx_pll;
component wr_arria10_ftm4_cmu_pll is
port (
pll_powerdown : in std_logic := 'X';
pll_refclk0 : in std_logic := 'X';
tx_serial_clk : out std_logic;
pll_locked : out std_logic;
pll_cal_busy : out std_logic
);
end component wr_arria10_ftm4_cmu_pll;
component wr_arria10_pex10_atx_pll is
port (
pll_refclk0 : in std_logic := 'X';
......@@ -771,6 +875,25 @@ package wr_altera_pkg is
);
end component wr_arria10_scu4_rst_ctl;
component wr_arria10_ftm4_rst_ctl is
port (
clock : in std_logic := 'X';
reset : in std_logic := 'X';
pll_powerdown : out std_logic_vector(0 downto 0);
tx_analogreset : out std_logic_vector(0 downto 0);
tx_digitalreset : out std_logic_vector(0 downto 0);
tx_ready : out std_logic_vector(0 downto 0);
pll_locked : in std_logic_vector(0 downto 0) := (others => 'X');
pll_select : in std_logic_vector(0 downto 0) := (others => 'X');
tx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X');
rx_analogreset : out std_logic_vector(0 downto 0);
rx_digitalreset : out std_logic_vector(0 downto 0);
rx_ready : out std_logic_vector(0 downto 0);
rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X');
rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X')
);
end component wr_arria10_ftm4_rst_ctl;
component wr_arria10_pex10_rst_ctl is
port (
clock : in std_logic := 'X';
......
platform/altera/wr_arria10_phy/Manifest.py
View file @ 48f04c06
......@@ -2,6 +2,7 @@ def __helper():
dirs = []
if syn_device[:4] == "10as": dirs.extend(["wr_arria10_phy"])
if syn_device[:7] == "10ax027": dirs.extend(["wr_arria10_scu4_phy"])
if syn_device[:7] == "10ax048": dirs.extend(["wr_arria10_ftm4_phy"])
if syn_device[:7] == "10ax115": dirs.extend(["wr_arria10_e3p1_phy"])
if syn_device[:9] == "10ax027h2": dirs.extend(["wr_arria10_pex10_phy"])
if syn_device[:9] == "10ax066h2": dirs.extend(["wr_arria10_ftm10_phy"])
......
platform/altera/wr_arria10_phy/wr_arria10_ftm4_phy/Manifest.py 0 → 100644
View file @ 48f04c06
files = [
"wr_arria10_ftm4_atx_pll/wr_arria10_ftm4_atx_pll.qsys",
"wr_arria10_ftm4_cmu_pll/wr_arria10_ftm4_cmu_pll.qsys",
"wr_arria10_ftm4_det_phy/wr_arria10_ftm4_det_phy.qsys",
"wr_arria10_ftm4_phy/wr_arria10_ftm4_phy.qsys",
"wr_arria10_ftm4_rst_ctl/wr_arria10_ftm4_rst_ctl.qsys"
]
platform/altera/wr_arria10_phy/wr_arria10_ftm4_phy/wr_arria10_ftm4_atx_pll/wr_arria10_ftm4_atx_pll.qsys 0 → 100644
View file @ 48f04c06
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element xcvr_atx_pll_a10_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX048E3F29E2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="pll_cal_busy"
internal="xcvr_atx_pll_a10_0.pll_cal_busy"
type="conduit"
dir="end">
<port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<interface
name="pll_locked"
internal="xcvr_atx_pll_a10_0.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
internal="xcvr_atx_pll_a10_0.pll_powerdown"
type="conduit"
dir="end">
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
name="pll_refclk0"
internal="xcvr_atx_pll_a10_0.pll_refclk0"
type="clock"
dir="end">
<port name="pll_refclk0" internal="pll_refclk0" />
</interface>
<interface
name="tx_serial_clk"
internal="xcvr_atx_pll_a10_0.tx_serial_clk"
type="hssi_serial_clock"
dir="start">
<port name="tx_serial_clk" internal="tx_serial_clk" />
</interface>
<module
name="xcvr_atx_pll_a10_0"
kind="altera_xcvr_atx_pll_a10"
version="18.1"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY2" />
<parameter name="bw_sel" value="medium" />
<parameter name="device" value="10AX027E3F29E2SG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="1" />
<parameter name="enable_analog_resets" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
<parameter name="enable_ext_lockdetect_ports" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="enable_hfreq_clk" value="0" />
<parameter name="enable_hip_cal_done_port" value="0" />
<parameter name="enable_manual_configuration" value="1" />
<parameter name="enable_mcgb" value="0" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
<parameter name="generate_add_hdl_instance_example" value="0" />
<parameter name="generate_docs" value="0" />
<parameter name="mcgb_aux_clkin_cnt" value="0" />
<parameter name="mcgb_div" value="1" />
<parameter name="message_level" value="error" />
<parameter name="pma_width" value="64" />
<parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="prot_mode" value="Basic" />
<parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_enable_avmm_busy_port" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
<parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
<parameter name="rcfg_profile_data0" value="" />
<parameter name="rcfg_profile_data1" value="" />
<parameter name="rcfg_profile_data2" value="" />
<parameter name="rcfg_profile_data3" value="" />
<parameter name="rcfg_profile_data4" value="" />
<parameter name="rcfg_profile_data5" value="" />
<parameter name="rcfg_profile_data6" value="" />
<parameter name="rcfg_profile_data7" value="" />
<parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_reduced_files_enable" value="0" />
<parameter name="rcfg_separate_avmm_busy" value="0" />
<parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="125.0" />
<parameter name="set_capability_reg_enable" value="0" />
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_fref_clock_frequency" value="156.25" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="2000000000" />
<parameter name="set_l_cascade_counter" value="15" />
<parameter name="set_l_cascade_predivider" value="1" />
<parameter name="set_l_counter" value="16" />
<parameter name="set_m_counter" value="24" />
<parameter name="set_manual_reference_clock_frequency" value="200.0" />
<parameter name="set_output_clock_frequency" value="625.0" />
<parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_ref_clk_div" value="1" />
<parameter name="set_user_identifier" value="0" />
<parameter name="silicon_rev" value="false" />
<parameter name="support_mode" value="user_mode" />
<parameter name="test_mode" value="0" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
platform/altera/wr_arria10_phy/wr_arria10_ftm4_phy/wr_arria10_ftm4_cmu_pll/wr_arria10_ftm4_cmu_pll.qsys 0 → 100644
View file @ 48f04c06
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element xcvr_cdr_pll_a10_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX048E3F29E2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="pll_cal_busy"
internal="xcvr_cdr_pll_a10_0.pll_cal_busy"
type="conduit"
dir="end">
<port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<interface
name="pll_locked"
internal="xcvr_cdr_pll_a10_0.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
internal="xcvr_cdr_pll_a10_0.pll_powerdown"
type="conduit"
dir="end">
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
name="pll_refclk0"
internal="xcvr_cdr_pll_a10_0.pll_refclk0"
type="clock"
dir="end">
<port name="pll_refclk0" internal="pll_refclk0" />
</interface>
<interface
name="tx_serial_clk"
internal="xcvr_cdr_pll_a10_0.tx_serial_clk"
type="hssi_serial_clock"
dir="start">
<port name="tx_serial_clk" internal="tx_serial_clk" />
</interface>
<module
name="xcvr_cdr_pll_a10_0"
kind="altera_xcvr_cdr_pll_a10"
version="18.1"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY2" />
<parameter name="bw_sel" value="Medium" />
<parameter name="cdr_pll_cgb_div" value="1" />
<parameter name="cdr_pll_initial_settings" value="true" />
<parameter name="cdr_pll_is_cascaded_pll" value="false" />
<parameter name="cdr_pll_optimal" value="false" />
<parameter name="device" value="10AX027E3F29E2SG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_analog_resets" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
<parameter name="generate_add_hdl_instance_example" value="0" />
<parameter name="generate_docs" value="0" />
<parameter name="gui_tx_pll_prot_mode" value="Basic" />
<parameter name="manual_counters" value="" />
<parameter name="message_level" value="error" />
<parameter name="output_clock_frequency" value="2500" />
<parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_enable_avmm_busy_port" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_cdr_pll_a10</parameter>
<parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_separate_avmm_busy" value="0" />
<parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
<parameter name="refclk_select_mux_powerdown_mode" value="powerup" />
<parameter name="reference_clock_frequency" value="125.0" />
<parameter name="select_manual_config" value="false" />
<parameter name="set_altera_xcvr_cdr_pll_a10_calibration_en" value="1" />
<parameter name="set_capability_reg_enable" value="0" />
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="support_mode" value="user_mode" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
platform/altera/wr_arria10_phy/wr_arria10_ftm4_phy/wr_arria10_ftm4_phy.tcl 0 → 100644
View file @ 48f04c06
qsys-generate wr_arria10_ftm4_phy
qsys-generate wr_arria10_ftm4_atx_pll
qsys-generate wr_arria10_ftm4_rst_ctl
qsys-generate wr_arria10_ftm4_det_phy
qsys-generate wr_arria10_ftm4_cmu_pll
platform/altera/wr_arria10_phy/wr_arria10_ftm4_phy/wr_arria10_ftm4_rst_ctl/wr_arria10_ftm4_rst_ctl.qsys 0 → 100644
View file @ 48f04c06
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element xcvr_reset_control_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX048E3F29E2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="clock"
internal="xcvr_reset_control_0.clock"
type="clock"
dir="end">
<port name="clock" internal="clock" />
</interface>
<interface
name="pll_locked"
internal="xcvr_reset_control_0.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
internal="xcvr_reset_control_0.pll_powerdown"
type="conduit"
dir="end">
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
name="pll_select"
internal="xcvr_reset_control_0.pll_select"
type="conduit"
dir="end">
<port name="pll_select" internal="pll_select" />
</interface>
<interface
name="reset"
internal="xcvr_reset_control_0.reset"
type="reset"
dir="end">
<port name="reset" internal="reset" />
</interface>
<interface
name="rx_analogreset"
internal="xcvr_reset_control_0.rx_analogreset"
type="conduit"
dir="end">
<port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
name="rx_cal_busy"
internal="xcvr_reset_control_0.rx_cal_busy"
type="conduit"
dir="end">
<port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
name="rx_digitalreset"
internal="xcvr_reset_control_0.rx_digitalreset"
type="conduit"
dir="end">
<port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
name="rx_is_lockedtodata"
internal="xcvr_reset_control_0.rx_is_lockedtodata"
type="conduit"
dir="end">
<port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
name="rx_ready"
internal="xcvr_reset_control_0.rx_ready"
type="conduit"
dir="end">
<port name="rx_ready" internal="rx_ready" />
</interface>
<interface
name="tx_analogreset"
internal="xcvr_reset_control_0.tx_analogreset"
type="conduit"
dir="end">
<port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
name="tx_cal_busy"
internal="xcvr_reset_control_0.tx_cal_busy"
type="conduit"
dir="end">
<port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
name="tx_digitalreset"
internal="xcvr_reset_control_0.tx_digitalreset"
type="conduit"
dir="end">
<port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
name="tx_ready"
internal="xcvr_reset_control_0.tx_ready"
type="conduit"
dir="end">
<port name="tx_ready" internal="tx_ready" />
</interface>
<module
name="xcvr_reset_control_0"
kind="altera_xcvr_reset_control"
version="18.1"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="1" />
<parameter name="PLLS" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" />
<parameter name="RX_ENABLE" value="1" />
<parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
<parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="SYS_CLK_IN_MHZ" value="125" />
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" />
<parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
<parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="70000" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
<parameter name="T_TX_ANALOGRESET" value="70000" />
<parameter name="T_TX_DIGITALRESET" value="70000" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_pll_cal_busy" value="0" />
<parameter name="gui_rx_auto_reset" value="0" />
<parameter name="gui_split_interfaces" value="0" />
<parameter name="gui_tx_auto_reset" value="0" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
platform/altera/wr_arria10_phy/wr_arria10_phy.vhd
View file @ 48f04c06
......@@ -46,7 +46,7 @@ use work.altera_networks_pkg.all;
entity wr_arria10_transceiver is
generic (
g_family : string; -- Family/device, possible options are: "Arria 10 GX SCU4" or "Arria 10 GX E3P1"
g_family : string; -- Family/device, possible options are: "Arria 10 GX " or "Arria 10 GX E3P1"
g_use_atx_pll : boolean := true; -- Use ATX PLL?
g_use_cmu_pll : boolean := false; -- Use CMU PLL?
g_use_simple_wa : boolean := false; -- Use simple word aligner (following altera/intel documentation)?
......@@ -254,6 +254,49 @@ begin
);
end generate scu4_phy;
ftm4_phy: if (g_family = "Arria 10 GX FTM4") generate
inst_phy : wr_arria10_ftm4_det_phy
port map (
tx_analogreset(0) => s_rst_ctl_tx_analogreset(0),
tx_digitalreset(0) => s_rst_ctl_tx_digitalreset(0),
rx_analogreset(0) => s_rst_ctl_rx_analogreset(0),
rx_digitalreset(0) => s_rst_ctl_rx_digitalreset(0),
tx_cal_busy(0) => s_phy_tx_cal_busy(0),
rx_cal_busy(0) => s_phy_rx_cal_busy(0),
tx_serial_clk0(0) => s_tx_pll_serial_clk,
rx_cdr_refclk0 => clk_phy_i,
tx_serial_data(0) => pad_txp_o,
rx_serial_data(0) => pad_rxp_i,
rx_is_lockedtoref => s_phy_rx_is_lockedtoref,
rx_is_lockedtodata => s_phy_rx_is_lockedtodata,
tx_coreclkin(0) => clk_ref_i,
rx_coreclkin(0) => clk_ref_i,
tx_clkout(0) => s_tx_clk,
rx_clkout(0) => s_rx_clk,
tx_parallel_data => s_tx_data,
rx_parallel_data => s_rx_data,
rx_datak => s_rx_data_k,
rx_disperr => s_phy_rx_disperr(0),
rx_errdetect => s_phy_rx_errdetect(0),
rx_patterndetect => s_patterndetect,
rx_runningdisp => s_rx_runningdisp,
rx_syncstatus => s_syncstatus,
tx_datak => s_tx_data_k,
rx_std_wa_patternalign(0) => s_rx_std_wa_patternalign,
reconfig_clk(0) => clk_phy_i,
reconfig_reset(0) => s_rst_ctl_rst,
reconfig_write => s_reconfig_write,
reconfig_read => s_reconfig_read,
reconfig_address => s_reconfig_address,
reconfig_writedata => s_reconfig_writedata,
reconfig_readdata => s_reconfig_readdata,
reconfig_waitrequest => s_reconfig_waitrequest,
rx_std_bitslipboundarysel(3 downto 0) => rx_bitslide_o(3 downto 0),
rx_std_bitslipboundarysel(4) => s_rx_bs_dump,
rx_seriallpbken(0) => s_loop_en
);
end generate ftm4_phy;
pex10_phy: if (g_family = "Arria 10 GX PEX10") generate
inst_phy : wr_arria10_pex10_det_phy
port map (
......@@ -525,6 +568,48 @@ begin
end generate cmu_pll;
end generate scu4_pll_and_reset;
ftm4_pll_and_reset: if (g_family = "Arria 10 GX ftm4") generate
inst_rst_ctl : wr_arria10_ftm4_rst_ctl
port map (
clock => clk_ref_i,
reset => s_rst_ctl_rst,
pll_powerdown(0) => s_rst_ctl_powerdown(0), -- Missing at Intel documentation -> Connection Guidelines for a CPRI PHY Design
tx_analogreset(0) => s_rst_ctl_tx_analogreset(0),
tx_digitalreset(0) => s_rst_ctl_tx_digitalreset(0),
tx_ready(0) => s_rst_ctl_tx_ready(0),
pll_locked(0) => s_tx_pll_locked(0),
pll_select(0) => s_pll_select(0),
tx_cal_busy(0) => s_cal_busy(0),
rx_analogreset(0) => s_rst_ctl_rx_analogreset(0),
rx_digitalreset(0) => s_rst_ctl_rx_digitalreset(0),
rx_ready(0) => s_rst_ctl_rx_ready(0),
rx_is_lockedtodata(0) => s_phy_rx_is_lockedtodata(0),
rx_cal_busy(0) => s_phy_rx_cal_busy(0)
);
atx_pll : if g_use_atx_pll generate
inst_atx_pll : wr_arria10_ftm4_atx_pll
port map (
pll_refclk0 => clk_phy_i,
pll_powerdown => s_rst_ctl_powerdown(0), -- Missing at Intel documentation -> Connection Guidelines for a CPRI PHY Design
pll_locked => s_tx_pll_locked(0),
tx_serial_clk => s_tx_pll_serial_clk,
pll_cal_busy => s_tx_pll_cal_busy
);
end generate atx_pll;
cmu_pll : if g_use_cmu_pll generate
inst_cmu_pll : wr_arria10_ftm4_cmu_pll
port map (
pll_refclk0 => clk_phy_i,
pll_powerdown => s_rst_ctl_powerdown(0), -- Missing at Intel documentation -> Connection Guidelines for a CPRI PHY Design
pll_locked => s_tx_pll_locked(0),
tx_serial_clk => s_tx_pll_serial_clk,
pll_cal_busy => s_tx_pll_cal_busy
);
end generate cmu_pll;
end generate ftm4_pll_and_reset;
pex10_pll_and_reset: if (g_family = "Arria 10 GX pex10") generate
inst_rst_ctl : wr_arria10_pex10_rst_ctl
port map (
......
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