Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
479c1ff2
Commit
479c1ff2
authored
Feb 01, 2017
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
top/vfchd: Introduce VFC-HD reference design
parent
7eaac3d8
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
10 changed files
with
2790 additions
and
0 deletions
+2790
-0
Manifest.py
syn/vfchd_ref_design/Manifest.py
+25
-0
quartus_preflow.tcl
syn/vfchd_ref_design/quartus_preflow.tcl
+225
-0
vfchd_wr_ref.sdc
syn/vfchd_ref_design/vfchd_wr_ref.sdc
+29
-0
Manifest.py
top/vfchd_ref_design/Manifest.py
+21
-0
I2cMuxAndExpMaster.v
top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpMaster.v
+388
-0
I2cMuxAndExpReqArbiter.v
top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpReqArbiter.v
+1162
-0
README
top/vfchd_ref_design/vfchd_i2cmux/README
+5
-0
SfpIdReader.v
top/vfchd_ref_design/vfchd_i2cmux/SfpIdReader.v
+72
-0
vfchd_i2cmux_pkg.vhd
top/vfchd_ref_design/vfchd_i2cmux/vfchd_i2cmux_pkg.vhd
+166
-0
vfchd_wr_ref_top.vhd
top/vfchd_ref_design/vfchd_wr_ref_top.vhd
+697
-0
No files found.
syn/vfchd_ref_design/Manifest.py
0 → 100644
View file @
479c1ff2
target
=
"altera"
action
=
"synthesis"
syn_family
=
"Arria V"
syn_device
=
"5agxmb1g4f"
syn_grade
=
"c4"
syn_package
=
"40"
syn_top
=
"vfchd_wr_ref_top"
syn_project
=
"vfchd_wr_ref"
syn_tool
=
"quartus"
quartus_preflow
=
"quartus_preflow.tcl"
files
=
[
"vfchd_wr_ref.sdc"
,
"quartus_preflow.tcl"
,
]
modules
=
{
"local"
:
[
"../../top/vfchd_ref_design/"
,
]
}
syn/vfchd_ref_design/quartus_preflow.tcl
0 → 100644
View file @
479c1ff2
# Quartus II: Tcl Preflow File for VFC-HD WR PTP core reference design
# Load Quartus II Tcl Project package
package
require ::quartus::project
# Borrowed and adjusted from GSI bel-projects
proc
qmegawiz
{
files
}
{
set dir
[
file
dirname
[
info
script
]]
post_message
"Testing for megawizard regeneration in
$dir:$files
"
set device
[
get_global_assignment -name DEVICE
]
set family
[
get_global_assignment -name FAMILY
]
foreach i
$files
{
if
{
!
[
file
exists
"
$dir
/
$i.qip
"
]
||
[
file
mtime
"
$dir
/
$i.txt
"
]
>
[
file
mtime
"
$dir
/
$i.qip
"
]}
{
post_message -type info
"Regenerating
$i
using qmegawiz"
file delete
"
$dir
/
$i.qip
"
file copy -force
"
$dir
/
$i.txt
"
"
$dir
/
$i.vhd
"
set sf
[
open
"| qmegawiz -silent
\"
-defaultfamily:
$family
\"
\"
-defaultdevice:
$device
\"
\"
$dir
/
$i.vhd
\"
"
"r"
]
while
{[
gets
$sf
line
]
>= 0
}
{
post_message -type info
"
$line
"
}
if
{[
catch
{
close
$sf
}
err
]}
{
post_message -type error
"Executing qmegawiz:
$err
"
exit 1
}
if
{
!
[
file
exists
"
$dir
/
$i.qip
"
]}
{
post_message -type error
"Executing qmegawiz: did not create
$dir
/
$i.qip
!"
exit 1
}
file mtime
"
$dir
/
$i.qip
"
[
file
mtime
"
$dir
/
$i.vhd
"
]
}
set_global_assignment -name QIP_FILE
"
$dir
/
$i.qip
"
}
}
# procedure to delete an existing global assignment
proc
del_global_assignment
{
name value
}
{
set_global_assignment -name
$name
-remove
$value
}
# procedure to check if signal is input
proc
is_input
{
signal
}
{
return
[
regexp
-nocase
{
.+_i
(
\[
[
0123456789
]
+
\]
)
?$
}
$signal
]
}
# simple procedure to take care of location assignments
proc
loc
{
pin signal
{
iostandard
"default"
}
{
pullup
"off"
}}
{
set_location_assignment
"PIN_
${pin}
"
-to
$signal
if
{
!
[
string
equal
$iostandard
"default"
]}
{
set_instance_assignment -name IO_STANDARD
$iostandard
-to
$signal
}
else
{
set_instance_assignment -name IO_STANDARD
"2.5 V"
-to
$signal
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to
$signal
if
{
!
[
is_input
$signal
]}
{
set_instance_assignment -name SLEW_RATE 1 -to
$signal
}
}
if
{
!
[
string
equal
$pullup
"off"
]}
{
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to
$signal
}
}
# SCRIPT EXECUTION STARTS HERE
post_message
"Executing WR VFC-HD reference design pre-flow script"
set
project_name
"vfchd_wr_ref"
set
make_assignments 0
# Make sure that the right project is open
if
{[
is_project_open
]}
{
if
{[
string
compare
$quartus
(
project
)
$project
_name
]}
{
project_close
project_open
$project
_name
}
}
else
{
project_open
$project
_name
}
# Remove unused megafunctions to reduce number of warnings
del_global_assignment QIP_FILE
"../../ip_cores/general-cores/platform/altera/networks/arria5_networks.qip"
del_global_assignment QIP_FILE
"../../ip_cores/general-cores/platform/altera/wb_pcie/arria5_pcie.qip"
# Regenerate required megafunctions if necessary
source
../../platform/altera/wr_arria5_phy/wr_arria5_phy.tcl
source
../../platform/altera/wr_arria5_pll_default/wr_arria5_pll_default.tcl
# Global assignments
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
"PACK ALL IO REGISTERS"
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION
"FORCED IF ASYNCHRONOUS"
# I/O configuration
loc AW25 areset_n_i
loc AF8 clk_board_125m_i
"LVDS"
loc AD20 clk_board_20m_i
loc AF25 dac_dmtd_sync_n_o
loc AC24 dac_ref_sync_n_o
loc AH26 dac_sclk_o
loc AG26 dac_din_o
loc AE1 sfp_rx_i
"1.5-V PCML"
loc AD3 sfp_tx_o
"1.5-V PCML"
loc AN25 i2c_mux_sda_b
loc AM25 i2c_mux_scl_b
loc AT26 io_exp_irq_bsteth_n_i
"default"
"on"
loc AK25 io_exp_irq_los_n_i
"default"
"on"
loc AD26 eeprom_sda_b
loc AH25 eeprom_scl_b
loc AV27 onewire_b
loc AW28 vme_write_n_i
loc AW30 vme_lword_n_b
loc AK21 vme_iackout_n_o
loc AM21 vme_iackin_n_i
loc AN21 vme_iack_n_i
loc AL22 vme_dtack_oe_o
loc AP22 vme_ds_n_i
[
0
]
loc AN22 vme_ds_n_i
[
1
]
loc AW20 vme_data_oe_n_o
loc AW19 vme_data_dir_o
loc AE29 vme_as_n_i
loc AK27 vme_addr_oe_n_o
loc AJ27 vme_addr_dir_o
loc AK22 vme_irq_n_o
[
1
]
loc AT21 vme_irq_n_o
[
2
]
loc AR21 vme_irq_n_o
[
3
]
loc AH22 vme_irq_n_o
[
4
]
loc AG22 vme_irq_n_o
[
5
]
loc AU20 vme_irq_n_o
[
6
]
loc AT20 vme_irq_n_o
[
7
]
loc AD24 vme_data_b
[
0
]
loc AD23 vme_data_b
[
1
]
loc AU24 vme_data_b
[
2
]
loc AT24 vme_data_b
[
3
]
loc AL24 vme_data_b
[
4
]
loc AK24 vme_data_b
[
5
]
loc AF24 vme_data_b
[
6
]
loc AE24 vme_data_b
[
7
]
loc AH24 vme_data_b
[
8
]
loc AG24 vme_data_b
[
9
]
loc AW24 vme_data_b
[
10
]
loc AW23 vme_data_b
[
11
]
loc AP24 vme_data_b
[
12
]
loc AN24 vme_data_b
[
13
]
loc AU23 vme_data_b
[
14
]
loc AT23 vme_data_b
[
15
]
loc AP23 vme_data_b
[
16
]
loc AN23 vme_data_b
[
17
]
loc AE23 vme_data_b
[
18
]
loc AD22 vme_data_b
[
19
]
loc AL23 vme_data_b
[
20
]
loc AK23 vme_data_b
[
21
]
loc AU22 vme_data_b
[
22
]
loc AT22 vme_data_b
[
23
]
loc AW22 vme_data_b
[
24
]
loc AV22 vme_data_b
[
25
]
loc AW21 vme_data_b
[
26
]
loc AV21 vme_data_b
[
27
]
loc AH23 vme_data_b
[
28
]
loc AG23 vme_data_b
[
29
]
loc AF22 vme_data_b
[
30
]
loc AE22 vme_data_b
[
31
]
loc AD29 vme_am_i
[
0
]
loc AH30 vme_am_i
[
1
]
loc AG30 vme_am_i
[
2
]
loc AV31 vme_am_i
[
3
]
loc AU31 vme_am_i
[
4
]
loc AW31 vme_am_i
[
5
]
loc AL30 vme_addr_b
[
1
]
loc AK30 vme_addr_b
[
2
]
loc AT30 vme_addr_b
[
3
]
loc AR30 vme_addr_b
[
4
]
loc AV30 vme_addr_b
[
5
]
loc AU30 vme_addr_b
[
6
]
loc AU29 vme_addr_b
[
7
]
loc AT29 vme_addr_b
[
8
]
loc AP30 vme_addr_b
[
9
]
loc AN30 vme_addr_b
[
10
]
loc AP29 vme_addr_b
[
11
]
loc AN29 vme_addr_b
[
12
]
loc AC29 vme_addr_b
[
13
]
loc AB29 vme_addr_b
[
14
]
loc AG28 vme_addr_b
[
15
]
loc AF28 vme_addr_b
[
16
]
loc AL29 vme_addr_b
[
17
]
loc AK29 vme_addr_b
[
18
]
loc AJ28 vme_addr_b
[
19
]
loc AH28 vme_addr_b
[
20
]
loc AE28 vme_addr_b
[
21
]
loc AD28 vme_addr_b
[
22
]
loc AB28 vme_addr_b
[
23
]
loc AB27 vme_addr_b
[
24
]
loc AM28 vme_addr_b
[
25
]
loc AD27 vme_addr_b
[
26
]
loc AC27 vme_addr_b
[
27
]
loc AR28 vme_addr_b
[
28
]
loc AP28 vme_addr_b
[
29
]
loc AV28 vme_addr_b
[
30
]
loc AU28 vme_addr_b
[
31
]
loc AM27 fmc_enable_n_o
loc C20 dio_led_term_o
loc D20 dio_led_out_o
loc M27 dio1_i
"LVDS"
loc AK34 dio5_clk_i
loc R26 dio1_oe_n_o
loc C28 dio5_oe_n_o
loc T27 dio1_term_en_o
loc C27 dio5_term_en_o
loc AL26 vfchd_gpio3_o
loc AV24 vfchd_gpio4_o
# Commit assignments
export_assignments
# SCRIPT EXECUTION ENDS HERE
post_message
"WR VFC-HD reference design pre-flow script execution complete"
syn/vfchd_ref_design/vfchd_wr_ref.sdc
0 → 100644
View file @
479c1ff2
# Clock inputs
create_clock -name clk_10m_ext -period 100.0 [get_ports dio5_clk_i]
create_clock -name clk_125m -period 8.0 [get_ports clk_board_125m_i]
create_clock -name clk_20m -period 50.0 [get_ports clk_board_20m_i]
# Derive the PLL Output clocks automatically
derive_pll_clocks
derive_clock_uncertainty
# splitting of PHY clocks based on pexarria5 project from GSI
set_clock_groups -asynchronous \
-group { clk_10m_ext \
cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_ext_ref_pll|* } \
-group { clk_125m \
cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_sys_clk_pll|*|general[0]* \
cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_sys_clk_pll|*|general[1]* } \
-group { clk_20m \
cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_dmtd_clk_pll|* } \
-group { cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*.cdr_refclk* \
cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*.cmu_pll.* \
cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|av_tx_pma|* \
cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|inst_av_pcs|*|tx* } \
-group { cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|clk90bdes \
cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|clk90b \
cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|rcvdclkpma }
# False paths from/to all otherwise unconstrained I/O
set_false_path -from [get_ports *]
set_false_path -to [get_ports *]
top/vfchd_ref_design/Manifest.py
0 → 100644
View file @
479c1ff2
fetchto
=
"../../ip_cores"
files
=
[
"vfchd_wr_ref_top.vhd"
,
"vfchd_i2cmux/vfchd_i2cmux_pkg.vhd"
,
"vfchd_i2cmux/I2cMuxAndExpReqArbiter.v"
,
"vfchd_i2cmux/I2cMuxAndExpMaster.v"
,
"vfchd_i2cmux/SfpIdReader.v"
,
]
modules
=
{
"local"
:
[
"../../"
,
"../../board/vfchd"
,
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git"
,
"git://ohwr.org/hdl-core-lib/vme64x-core.git"
,
"git://ohwr.org/hdl-core-lib/etherbone-core.git"
,
],
}
top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpMaster.v
0 → 100644
View file @
479c1ff2
This diff is collapsed.
Click to expand it.
top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpReqArbiter.v
0 → 100644
View file @
479c1ff2
This diff is collapsed.
Click to expand it.
top/vfchd_ref_design/vfchd_i2cmux/README
0 → 100644
View file @
479c1ff2
All files copied from VFC-HD_System repository of CERN BE-BI[*].
Commit used = fbd74d93f99b54e2ce0dd8d4ae7ff2769234e2d8
[*]: https://gitlab.cern.ch/bi/VFC-HD_System
top/vfchd_ref_design/vfchd_i2cmux/SfpIdReader.v
0 → 100644
View file @
479c1ff2
`timescale
1
ns
/
1
ns
module
SfpIdReader
#(
parameter
g_SfpWbBaseAddress
=
0
,
g_WbAddrWidth
=
32
)
(
input
Clk_ik
,
input
SfpPlugged_i
,
output
reg
SfpIdValid_o
,
output
reg
[
127
:
0
]
SfpPN_b128
,
output
reg
WbCyc_o
,
output
reg
WbStb_o
,
output
reg
[
g_WbAddrWidth
-
1
:
0
]
WbAddr_ob
,
input
[
7
:
0
]
WbData_ib8
,
input
WbAck_i
)
;
localparam
s_NoSfp
=
0
,
s_WbStart
=
1
,
s_WbClose
=
2
,
s_Done
=
3
;
reg
[
1
:
0
]
State_q
=
s_NoSfp
,
NextState_a
;
reg
[
3
:
0
]
ByteRead_c4
;
always
@
(
posedge
Clk_ik
)
State_q
<=
NextState_a
;
always
@*
if
(
!
SfpPlugged_i
)
NextState_a
=
s_NoSfp
;
else
begin
NextState_a
=
State_q
;
case
(
State_q
)
s_NoSfp:
if
(
SfpPlugged_i
)
NextState_a
=
s_WbStart
;
s_WbStart:
if
(
WbAck_i
)
NextState_a
=
s_WbClose
;
s_WbClose:
if
(
!
WbAck_i
)
NextState_a
=
&
ByteRead_c4
?
s_Done
:
s_WbStart
;
s_Done:
;
default:
NextState_a
=
s_NoSfp
;
endcase
end
always
@
(
posedge
Clk_ik
)
case
(
State_q
)
s_NoSfp:
begin
SfpIdValid_o
<=
1'b0
;
ByteRead_c4
<=
4'd0
;
WbCyc_o
<=
1'b0
;
WbStb_o
<=
1'b0
;
WbAddr_ob
<=
g_SfpWbBaseAddress
+
40
;
SfpPN_b128
<=
128'd0
;
end
s_WbStart:
begin
WbCyc_o
<=
1'b1
;
WbStb_o
<=
1'b1
;
if
(
NextState_a
==
s_WbClose
)
SfpPN_b128
<=
{
SfpPN_b128
[
119
:
0
]
,
WbData_ib8
};
end
s_WbClose:
begin
WbCyc_o
<=
1'b1
;
WbStb_o
<=
1'b0
;
if
(
NextState_a
==
s_WbStart
)
begin
WbAddr_ob
<=
WbAddr_ob
+
1'b1
;
ByteRead_c4
<=
ByteRead_c4
+
1'b1
;
end
end
s_Done:
begin
SfpIdValid_o
<=
1'b1
;
WbCyc_o
<=
1'b0
;
WbStb_o
<=
1'b0
;
end
endcase
endmodule
top/vfchd_ref_design/vfchd_i2cmux/vfchd_i2cmux_pkg.vhd
0 → 100644
View file @
479c1ff2
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
package
vfchd_i2cmux_pkg
is
component
SfpIdReader
is
generic
(
g_SfpWbBaseAddress
:
natural
:
=
0
;
g_WbAddrWidth
:
natural
:
=
32
);
port
(
Clk_ik
:
in
std_logic
;
SfpPlugged_i
:
in
std_logic
;
SfpIdValid_o
:
out
std_logic
;
SfpPN_b128
:
out
std_logic_vector
(
127
downto
0
);
WbCyc_o
:
out
std_logic
;
WbStb_o
:
out
std_logic
;
WbAddr_ob
:
out
std_logic_vector
(
g_WbAddrWidth
-1
downto
0
);
WbData_ib8
:
in
std_logic_vector
(
7
downto
0
);
WbAck_i
:
in
std_logic
);
end
component
SfpIdReader
;
component
I2cExpAndMuxMaster
is
generic
(
g_SclHalfPeriod
:
std_logic_vector
(
9
downto
0
)
:
=
"0100000000"
);
port
(
Clk_ik
:
in
std_logic
;
Rst_irq
:
in
std_logic
;
IoExpWrReq_i
:
in
std_logic
;
IoExpWrOn_oq
:
out
std_logic
;
IoExpRdReq_i
:
in
std_logic
;
IoExpRdOn_oq
:
out
std_logic
;
IoExpAddr_ib3
:
in
std_logic_vector
(
2
downto
0
);
IoExpRegAddr_ib2
:
in
std_logic_vector
(
1
downto
0
);
IoExpData_ib8
:
in
std_logic_vector
(
7
downto
0
);
I2cSlaveWrReq_i
:
in
std_logic
;
I2cSlaveWrOn_o
:
out
std_logic
;
I2cSlaveRdReq_i
:
in
std_logic
;
I2cSlaveRdOn_o
:
out
std_logic
;
I2cMuxAddress_i
:
in
std_logic
;
I2cMuxChannel_ib2
:
in
std_logic_vector
(
1
downto
0
);
I2cSlaveAddr_ib7
:
in
std_logic_vector
(
6
downto
0
);
I2cSlaveRegAddr_ib8
:
in
std_logic_vector
(
7
downto
0
);
I2cSlaveByte_ib8
:
in
std_logic_vector
(
7
downto
0
);
Busy_o
:
out
std_logic
;
NewByteRead_op
:
out
std_logic
;
ByteOut_ob8
:
out
std_logic_vector
(
7
downto
0
);
AckError_op
:
out
std_logic
;
Scl_ioz
:
inout
std_logic
;
Sda_ioz
:
inout
std_logic
);
end
component
I2cExpAndMuxMaster
;
component
I2cExpAndMuxReqArbiter
is
port
(
Clk_ik
:
in
std_logic
;
Rst_irq
:
in
std_logic
;
IoExpWrReq_oq
:
out
std_logic
;
IoExpWrOn_i
:
in
std_logic
;
IoExpRdReq_oq
:
out
std_logic
;
IoExpRdOn_i
:
in
std_logic
;
IoExpAddr_oqb3
:
out
std_logic_vector
(
2
downto
0
);
IoExpRegAddr_oqb2
:
out
std_logic_vector
(
1
downto
0
);
IoExpData_oqb8
:
out
std_logic_vector
(
7
downto
0
);
I2cSlaveWrReq_oq
:
out
std_logic
;
I2cSlaveWrOn_i
:
in
std_logic
;
I2cSlaveRdReq_oq
:
out
std_logic
;
I2cSlaveRdOn_i
:
in
std_logic
;
I2cMuxAddress_oq
:
out
std_logic
;
I2cMuxChannel_oqb2
:
out
std_logic_vector
(
1
downto
0
);
I2cSlaveAddr_oqb7
:
out
std_logic_vector
(
6
downto
0
);
I2cSlaveRegAddr_oqb8
:
out
std_logic_vector
(
7
downto
0
);
I2cSlaveByte_oqb8
:
out
std_logic_vector
(
7
downto
0
);
MasterBusy_i
:
in
std_logic
;
MasterNewByteRead_ip
:
in
std_logic
;
MasterByteOut_ib8
:
in
std_logic_vector
(
7
downto
0
);
MasterAckError_i
:
in
std_logic
;
IoExpApp12Int_ian
:
in
std_logic
;
IoExpApp34Int_ian
:
in
std_logic
;
IoExpBstEthInt_ian
:
in
std_logic
;
IoExpLosInt_ian
:
in
std_logic
;
IoExpBlmInInt_ian
:
in
std_logic
;
InitDone_oq
:
out
std_logic
;
VmeGa_onqb5
:
out
std_logic_vector
(
4
downto
0
);
VmeGaP_onq
:
out
std_logic
;
Led_ib8
:
in
std_logic_vector
(
7
downto
0
);
StatusLed_ob8
:
out
std_logic_vector
(
7
downto
0
);
GpIo1A2B_i
:
in
std_logic
;
EnGpIo1Term_i
:
in
std_logic
;
GpIo2A2B_i
:
in
std_logic
;
EnGpIo2Term_i
:
in
std_logic
;
GpIo34A2B_i
:
in
std_logic
;
EnGpIo3Term_i
:
in
std_logic
;
EnGpIo4Term_i
:
in
std_logic
;
StatusGpIo1A2B_oq
:
out
std_logic
;
StatusEnGpIo1Term_oq
:
out
std_logic
;
StatusGpIo2A2B_oq
:
out
std_logic
;
StatusEnGpIo2Term_oq
:
out
std_logic
;
StatusGpIo34A2B_oq
:
out
std_logic
;
StatusEnGpIo3Term_oq
:
out
std_logic
;
StatusEnGpIo4Term_oq
:
out
std_logic
;
BlmIn_oqb8
:
out
std_logic_vector
(
7
downto
0
);
AppSfp1Present_oq
:
out
std_logic
;
AppSfp1Id_oq16
:
out
std_logic_vector
(
15
downto
0
);
AppSfp1TxFault_oq
:
out
std_logic
;
AppSfp1Los_oq
:
out
std_logic
;
AppSfp1TxDisable_i
:
in
std_logic
;
AppSfp1RateSelect_i
:
in
std_logic
;
StatusAppSfp1TxDisable_oq
:
out
std_logic
;
StatusAppSfp1RateSelect_oq
:
out
std_logic
;
AppSfp2Present_oq
:
out
std_logic
;
AppSfp2Id_oq16
:
out
std_logic_vector
(
15
downto
0
);
AppSfp2TxFault_oq
:
out
std_logic
;
AppSfp2Los_oq
:
out
std_logic
;
AppSfp2TxDisable_i
:
in
std_logic
;
AppSfp2RateSelect_i
:
in
std_logic
;
StatusAppSfp2TxDisable_oq
:
out
std_logic
;
StatusAppSfp2RateSelect_oq
:
out
std_logic
;
AppSfp3Present_oq
:
out
std_logic
;
AppSfp3Id_oq16
:
out
std_logic_vector
(
15
downto
0
);
AppSfp3TxFault_oq
:
out
std_logic
;
AppSfp3Los_oq
:
out
std_logic
;
AppSfp3TxDisable_i
:
in
std_logic
;
AppSfp3RateSelect_i
:
in
std_logic
;
StatusAppSfp3TxDisable_oq
:
out
std_logic
;
StatusAppSfp3RateSelect_oq
:
out
std_logic
;
AppSfp4Present_oq
:
out
std_logic
;
AppSfp4Id_oq16
:
out
std_logic_vector
(
15
downto
0
);
AppSfp4TxFault_oq
:
out
std_logic
;
AppSfp4Los_oq
:
out
std_logic
;
AppSfp4TxDisable_i
:
in
std_logic
;
AppSfp4RateSelect_i
:
in
std_logic
;
StatusAppSfp4TxDisable_oq
:
out
std_logic
;
StatusAppSfp4RateSelect_oq
:
out
std_logic
;
BstSfpPresent_oq
:
out
std_logic
;
BstSfpId_oq16
:
out
std_logic_vector
(
15
downto
0
);
BstSfpTxFault_oq
:
out
std_logic
;
BstSfpLos_oq
:
out
std_logic
;
BstSfpTxDisable_i
:
in
std_logic
;
BstSfpRateSelect_i
:
in
std_logic
;
StatusBstSfpTxDisable_oq
:
out
std_logic
;
StatusBstSfpRateSelect_oq
:
out
std_logic
;
EthSfpPresent_oq
:
out
std_logic
;
EthSfpId_oq16
:
out
std_logic_vector
(
15
downto
0
);
EthSfpTxFault_oq
:
out
std_logic
;
EthSfpLos_oq
:
out
std_logic
;
EthSfpTxDisable_i
:
in
std_logic
;
EthSfpRateSelect_i
:
in
std_logic
;
StatusEthSfpTxDisable_oq
:
out
std_logic
;
StatusEthSfpRateSelect_oq
:
out
std_logic
;
CdrLos_oq
:
out
std_logic
;
CdrLol_oq
:
out
std_logic
;
I2cWbCyc_i
:
in
std_logic
;
I2cWbStb_i
:
in
std_logic
;
I2cWbWe_i
:
in
std_logic
;
I2cWbAdr_ib12
:
in
std_logic_vector
(
11
downto
0
);
I2cWbDat_ib8
:
in
std_logic_vector
(
7
downto
0
);
I2cWbDat_ob8
:
out
std_logic_vector
(
7
downto
0
);
I2cWbAck_o
:
out
std_logic
;
WbCyc_i
:
in
std_logic
;
WbStb_i
:
in
std_logic
;
WbWe_i
:
in
std_logic
;
WbDat_ib32
:
in
std_logic_vector
(
31
downto
0
);
WbDat_oqb32
:
out
std_logic_vector
(
31
downto
0
);
WbAck_oa
:
out
std_logic
);
end
component
I2cExpAndMuxReqArbiter
;
end
vfchd_i2cmux_pkg
;
top/vfchd_ref_design/vfchd_wr_ref_top.vhd
0 → 100644
View file @
479c1ff2
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment