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Commit 471bc177 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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modules/wr_endpoint: remove unused PHY signals enable and syncen

parent 1648bf24
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Showing with 31 additions and 46 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 471bc177
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-03
-- Last update: 2017-02-16
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -93,8 +93,6 @@ package endpoint_pkg is
type t_phy_8bits_from_wrc is record
rst : std_logic;
loopen : std_logic;
enable : std_logic;
syncen : std_logic;
tx_data : std_logic_vector(7 downto 0);
tx_k : std_logic_vector(0 downto 0);
loopen_vec : std_logic_vector(2 downto 0);
......@@ -103,10 +101,10 @@ package endpoint_pkg is
end record;
constant c_dummy_phy8_to_wrc : t_phy_8bits_to_wrc :=
('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0', (others=>'0'), '0',
'0', '0');
('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0',
(others=>'0'), '0', '0', '0');
constant c_dummy_phy8_from_wrc : t_phy_8bits_from_wrc :=
('0', '0', '0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
('0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
(others=>'0'), '0');
-- 16-bit Serdes
......@@ -126,8 +124,6 @@ package endpoint_pkg is
type t_phy_16bits_from_wrc is record
rst : std_logic;
loopen : std_logic;
enable : std_logic;
syncen : std_logic;
tx_data : std_logic_vector(15 downto 0);
tx_k : std_logic_vector(1 downto 0);
loopen_vec : std_logic_vector(2 downto 0);
......@@ -136,10 +132,10 @@ package endpoint_pkg is
end record;
constant c_dummy_phy16_to_wrc : t_phy_16bits_to_wrc :=
('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0', (others=>'0'), '0',
'0', '0');
('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0',
(others=>'0'), '0', '0', '0');
constant c_dummy_phy16_from_wrc : t_phy_16bits_from_wrc :=
('0', '0', '0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
('0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
(others=>'0'), '0');
......@@ -205,8 +201,6 @@ package endpoint_pkg is
phy_sfp_tx_fault_i : in std_logic := '0';
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_enable_o : out std_logic;
phy_syncen_o : out std_logic;
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......@@ -312,8 +306,6 @@ package endpoint_pkg is
phy_sfp_tx_fault_i : in std_logic := '0';
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_enable_o : out std_logic;
phy_syncen_o : out std_logic;
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 471bc177
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2017-02-03
-- Last update: 2017-02-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -135,14 +135,12 @@ package endpoint_private_pkg is
link_ok_o : out std_logic;
link_ctr_i : in std_logic := '1';
serdes_rst_o : out std_logic;
serdes_syncen_o : out std_logic;
serdes_loopen_o : out std_logic;
serdes_loopen_vec_o : out std_logic_vector(2 downto 0);
serdes_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
serdes_sfp_tx_fault_i : in std_logic;
serdes_sfp_los_i : in std_logic;
serdes_sfp_tx_disable_o : out std_logic;
serdes_enable_o : out std_logic;
serdes_rdy_i : in std_logic;
serdes_tx_clk_i : in std_logic;
serdes_tx_data_o : out std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ 471bc177
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2017-02-03
-- Last update: 2017-02-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -122,9 +122,6 @@ entity ep_1000basex_pcs is
-- 1: serdes is reset, 0: serdes is operating normally.
serdes_rst_o : out std_logic;
-- 1: serdes comma alignent is enabled.
serdes_syncen_o : out std_logic;
-- 1: serdes near-end PMA loopback is enabled.
serdes_loopen_o : out std_logic;
......@@ -143,13 +140,9 @@ entity ep_1000basex_pcs is
-- 1: Disables the transmitter
serdes_sfp_tx_disable_o : out std_logic;
-- 1: serdes TX/RX is enabled.
serdes_enable_o : out std_logic;
-- 1: serdes is locked and aligned
serdes_rdy_i : in std_logic;
---------------------------------------------------------------------------
-- Serdes TX path (all synchronous to serdes_tx_clk_i)
---------------------------------------------------------------------------
......@@ -603,7 +596,5 @@ begin -- rtl
rmon_o.tx_frame <= '0';
rmon_o.rx_frame <= '0';
rmon_o.rx_drop_at_rtu_full <= '0';
serdes_syncen_o <= '1';
serdes_enable_o <= '1';
end rtl;
modules/wr_endpoint/wr_endpoint.vhd
View file @ 471bc177
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-03
-- Last update: 2017-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -112,8 +112,6 @@ entity wr_endpoint is
phy_sfp_tx_fault_i : in std_logic;
phy_sfp_los_i : in std_logic;
phy_sfp_tx_disable_o : out std_logic;
phy_enable_o : out std_logic;
phy_syncen_o : out std_logic;
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic;
......@@ -516,8 +514,6 @@ begin
serdes_sfp_tx_fault_i => phy_sfp_tx_fault_i,
serdes_sfp_los_i => phy_sfp_los_i,
serdes_sfp_tx_disable_o => phy_sfp_tx_disable_o,
serdes_enable_o => phy_enable_o,
serdes_syncen_o => phy_syncen_o,
serdes_rdy_i => phy_rdy_i,
serdes_tx_clk_i => phy_ref_clk_i,
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 471bc177
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-02
-- Last update: 2017-02-16
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -103,8 +103,6 @@ entity xwr_endpoint is
phy_sfp_tx_fault_i : in std_logic;
phy_sfp_los_i : in std_logic;
phy_sfp_tx_disable_o : out std_logic;
phy_enable_o : out std_logic;
phy_syncen_o : out std_logic;
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic := '0';
......@@ -275,8 +273,6 @@ architecture syn of xwr_endpoint is
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_loopen_vec : std_logic_vector(2 downto 0);
signal phy_enable : std_logic;
signal phy_syncen : std_logic;
signal phy_tx_data : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_k : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_prbs_sel : std_logic_vector(2 downto 0);
......@@ -329,8 +325,6 @@ begin
phy_loopen_o => phy_loopen,
phy_loopen_vec_o => phy_loopen_vec,
phy_tx_prbs_sel_o => phy_tx_prbs_sel,
phy_enable_o => phy_enable,
phy_syncen_o => phy_syncen,
phy_rdy_i => phy_rdy,
phy_sfp_tx_fault_i => sfp_tx_fault,
......@@ -434,8 +428,6 @@ begin
phy16_o.rst <= phy_rst;
phy16_o.loopen <= phy_loopen;
phy16_o.loopen_vec <= phy_loopen_vec;
phy16_o.enable <= phy_enable;
phy16_o.syncen <= phy_syncen;
phy16_o.tx_data <= phy_tx_data;
phy16_o.tx_k <= phy_tx_k;
phy16_o.tx_prbs_sel <= phy_tx_prbs_sel;
......@@ -452,14 +444,22 @@ begin
phy_rdy <= phy16_i.rdy;
sfp_tx_fault <= phy16_i.sfp_tx_fault;
sfp_los <= phy16_i.sfp_los;
-- drive unused ports with dummy values
phy8_o <= c_dummy_phy8_from_wrc;
phy_rst_o <= '0';
phy_loopen_o <= '0';
phy_tx_data_o <= (others => '0');
phy_tx_k_o <= (others => '0');
phy_loopen_vec_o <= (others => '0');
phy_tx_prbs_sel_o <= (others => '0');
phy_sfp_tx_disable_o <= '0';
end generate;
GEN_8BIT_IF: if not g_pcs_16bit and g_records_for_phy generate
phy8_o.rst <= phy_rst;
phy8_o.loopen <= phy_loopen;
phy8_o.loopen_vec <= phy_loopen_vec;
phy8_o.enable <= phy_enable;
phy8_o.syncen <= phy_syncen;
phy8_o.tx_data <= phy_tx_data;
phy8_o.tx_k <= phy_tx_k;
phy8_o.tx_prbs_sel <= phy_tx_prbs_sel;
......@@ -476,6 +476,16 @@ begin
phy_rdy <= phy8_i.rdy;
sfp_tx_fault <= phy8_i.sfp_tx_fault;
sfp_los <= phy8_i.sfp_los;
-- drive unused ports with dummy values
phy16_o <= c_dummy_phy16_from_wrc;
phy_rst_o <= '0';
phy_loopen_o <= '0';
phy_tx_data_o <= (others => '0');
phy_tx_k_o <= (others => '0');
phy_loopen_vec_o <= (others => '0');
phy_tx_prbs_sel_o <= (others => '0');
phy_sfp_tx_disable_o <= '0';
end generate;
-- backwards compatibility
......@@ -483,8 +493,6 @@ begin
phy_rst_o <= phy_rst;
phy_loopen_o <= phy_loopen;
phy_loopen_vec_o <= phy_loopen_vec;
phy_enable_o <= phy_enable;
phy_syncen_o <= phy_syncen;
phy_tx_data_o <= phy_tx_data;
phy_tx_k_o <= phy_tx_k;
phy_tx_prbs_sel_o <= phy_tx_prbs_sel;
......
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