[softpll] Fix clk_ext_mul_i input when g_num_exts=0

When g_num_exts=0, the input of xwr_softpll_ng clk_ext_mul_i : in std_logic_vector(g_num_exts-1 downto 0); was of wrong range, i.e. std_logic_vector(-1 to 0). Function f_nonzero_vector() was added to generate std_logic_vector(0 to 0) in the case when g_num_exts=0.

[softpll] Fix clk_ext_mul_i input when g_num_exts=0
When g_num_exts=0, the input of xwr_softpll_ng clk_ext_mul_i : in std_logic_vector(g_num_exts-1 downto 0); was of wrong range, i.e. std_logic_vector(-1 to 0). Function f_nonzero_vector() was added to generate std_logic_vector(0 to 0) in the case when g_num_exts=0.
462beb7c · Maciej Lipinski · 8299d657 · 462beb7c · 462beb7c · 462beb7c
Commit 462beb7c authored Mar 11, 2020 by Maciej Lipinski
4 changed files
--- a/modules/wr_softpll_ng/softpll_pkg.vhd
+++ b/modules/wr_softpll_ng/softpll_pkg.vhd
@@ -23,9 +23,32 @@ package softpll_pkg is
  constant c_softpll_out_status_locked   : std_logic_vector(3 downto 0) := "0010";
  constant c_softpll_out_status_aligning : std_logic_vector(3 downto 0) := "0011";
  constant c_softpll_out_status_holdover : std_logic_vector(3 downto 0) := "0100";
-  
+
+  function f_nonzero_vector(vector_width : integer) return integer;
+
 end package;

 package body softpll_pkg is

+  -- Function f_nonzero_vector() is to be used in generating std_logic_vector
+  -- in which the number of bits can be specified to be zero, e.g.
+  -- (see xwr_softpll_ng)
+  --
+  --   clk_ext_mul_i        : in std_logic_vector(g_num_exts-1 downto 0);
+  --
+  -- There might not be any external clocks, i.e. g_num_exts. In such case,
+  -- the code would not compile because std_logic_vector(-1 to 0) is not valid.
+  -- This function is used to generate std_logic_vector(0 to 0) in the case
+  -- when g_num_exts=0.
+  --
+  function f_nonzero_vector(vector_width : integer)
+    return integer is
+  begin
+    if (vector_width > 0) then
+      return vector_width;
+    else
+      return 1;
+    end if;
+  end function;
+
 end softpll_pkg;
--- a/modules/wr_softpll_ng/wr_softpll_ng.vhd
+++ b/modules/wr_softpll_ng/wr_softpll_ng.vhd
@@ -115,7 +115,7 @@ entity wr_softpll_ng is
    clk_ext_i : in std_logic;

 -- External clock, multiplied to 125 MHz using the FPGA's PLL
-    clk_ext_mul_i        : in std_logic_vector(g_num_exts-1 downto 0);
+    clk_ext_mul_i        : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
    clk_ext_mul_locked_i : in std_logic := '1';
    clk_ext_stopped_i : in std_logic := '0';
    clk_ext_rst_o : out std_logic;

--- a/modules/wr_softpll_ng/xwr_softpll_ng.vhd
+++ b/modules/wr_softpll_ng/xwr_softpll_ng.vhd
@@ -105,7 +105,7 @@ entity xwr_softpll_ng is
    clk_ext_i : in std_logic;

 -- External clock, multiplied to 125 MHz using the FPGA's PLL
-    clk_ext_mul_i        : in std_logic_vector(g_num_exts-1 downto 0);
+    clk_ext_mul_i        : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
    clk_ext_mul_locked_i : in std_logic := '1';
    clk_ext_stopped_i    : in std_logic := '0';
    clk_ext_rst_o        : out std_logic;
@@ -166,7 +166,7 @@ architecture wrapper of xwr_softpll_ng is
      clk_fb_i        : in  std_logic_vector(g_num_outputs-1 downto 0);
      clk_dmtd_i      : in  std_logic;
      clk_ext_i       : in  std_logic;
-      clk_ext_mul_i   : in  std_logic_vector(g_num_exts-1 downto 0);
+      clk_ext_mul_i   : in  std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
      clk_ext_mul_locked_i : in  std_logic;
      clk_ext_stopped_i    : in  std_logic;
      clk_ext_rst_o        : out std_logic;

--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
@@ -332,7 +332,7 @@ package wrcore_pkg is
      clk_fb_i        : in  std_logic_vector(g_num_outputs-1 downto 0);
      clk_dmtd_i      : in  std_logic;
      clk_ext_i       : in  std_logic;
-      clk_ext_mul_i        : in std_logic_vector(g_num_exts-1 downto 0);
+      clk_ext_mul_i        : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
      clk_ext_mul_locked_i : in std_logic;
      clk_ext_stopped_i    : in std_logic;
      clk_ext_rst_o        : out std_logic;