Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
4482c478
Commit
4482c478
authored
Oct 18, 2019
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
board/svec7: initial version
parent
ad01cd09
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
900 additions
and
2 deletions
+900
-2
Manifest.py
board/Manifest.py
+1
-1
Manifest.py
board/svec7/Manifest.py
+11
-0
wr_svec7_pkg.vhd
board/svec7/wr_svec7_pkg.vhd
+320
-0
xwrc_board_svec7.vhd
board/svec7/xwrc_board_svec7.vhd
+563
-0
xwrc_platform_xilinx.vhd
platform/xilinx/xwrc_platform_xilinx.vhd
+5
-1
No files found.
board/Manifest.py
View file @
4482c478
try
:
if
board
in
[
"spec"
,
"svec"
,
"vfchd"
,
"common"
]:
if
board
in
[
"spec"
,
"svec"
,
"vfchd"
,
"common"
,
"svec7"
]:
modules
=
{
"local"
:
[
board
]
}
except
NameError
:
pass
board/svec7/Manifest.py
0 → 100644
View file @
4482c478
files
=
[
"wr_svec7_pkg.vhd"
,
"xwrc_board_svec7.vhd"
# "wrc_board_svec.vhd",
]
modules
=
{
"local"
:
[
"../common"
,
]
}
board/svec7/wr_svec7_pkg.vhd
0 → 100644
View file @
4482c478
This diff is collapsed.
Click to expand it.
board/svec7/xwrc_board_svec7.vhd
0 → 100644
View file @
4482c478
This diff is collapsed.
Click to expand it.
platform/xilinx/xwrc_platform_xilinx.vhd
View file @
4482c478
...
...
@@ -93,8 +93,11 @@ entity xwrc_platform_xilinx is
clk_20m_vcxo_i
:
in
std_logic
:
=
'0'
;
-- 125.000 MHz PLL reference
clk_125m_pllref_i
:
in
std_logic
:
=
'0'
;
clk_62m5_pllref_i
:
in
std_logic
:
=
'0'
;
-- 124.992 MHz DMTD reference (CLBv3 reference design)
clk_125m_dmtd_i
:
in
std_logic
:
=
'0'
;
clk_125m_dmtd_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Clock inputs from custom PLLs (g_use_default_plls = FALSE)
---------------------------------------------------------------------------
...
...
@@ -151,6 +154,7 @@ entity xwrc_platform_xilinx is
-- PLL outputs
clk_62m5_sys_o
:
out
std_logic
;
clk_125m_ref_o
:
out
std_logic
;
clk_62m5_ref_o
:
out
std_logic
;
clk_20m_o
:
out
std_logic
;
clk_ref_locked_o
:
out
std_logic
;
clk_62m5_dmtd_o
:
out
std_logic
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment