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White Rabbit core collection
Commit 43b3139d authored by Pascal Bos's avatar Pascal Bos Committed by Peter Jansweijer
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Added processing system to ref design. 

updated PCIe Memory map to fit WRPC-v5
parent fd1c3919
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Showing with 129 additions and 98 deletions
board/spec7/wr_spec7_pkg.vhd
View file @ 43b3139d
......@@ -210,7 +210,6 @@ package wr_spec7_pkg is
user_lnk_up_0 : out STD_LOGIC;
usr_irq_ack_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
usr_irq_req_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
gpio_rtl_0_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
......
platform/xilinx/wr_pcie/processing_system_pcie.tcl
View file @ 43b3139d
......@@ -123,10 +123,7 @@ set bCheckIPsPassed 1
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:axi_hwicap:3.0\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:smartconnect:1.0\
xilinx.com:ip:xdma:4.1\
"
......@@ -204,8 +201,6 @@ proc create_root_design { parentCell } {
CONFIG.PROTOCOL {AXI4} \
] $M00_AXI_0
set gpio_rtl_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_rtl_0 ]
set pcie_mgt_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_mgt_0 ]
......@@ -220,16 +215,6 @@ proc create_root_design { parentCell } {
set usr_irq_ack_0 [ create_bd_port -dir O -from 0 -to 0 usr_irq_ack_0 ]
set usr_irq_req_0 [ create_bd_port -dir I -from 0 -to 0 usr_irq_req_0 ]
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_GPIO_WIDTH {4} \
] $axi_gpio_0
# Create instance: axi_hwicap_0, and set properties
set axi_hwicap_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_hwicap:3.0 axi_hwicap_0 ]
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list \
......@@ -1044,20 +1029,11 @@ proc create_root_design { parentCell } {
CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
] $processing_system7_0
# Create instance: ps7_0_axi_periph, and set properties
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $ps7_0_axi_periph
# Create instance: rst_ps7_0_50M, and set properties
set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_CLKS {2} \
CONFIG.NUM_MI {3} \
CONFIG.NUM_MI {2} \
CONFIG.NUM_SI {1} \
] $smartconnect_0
......@@ -1069,11 +1045,12 @@ proc create_root_design { parentCell } {
CONFIG.PF3_DEVICE_ID_mqdma {9022} \
CONFIG.axil_master_64bit_en {true} \
CONFIG.axilite_master_en {true} \
CONFIG.axilite_master_scale {Gigabytes} \
CONFIG.axilite_master_scale {Megabytes} \
CONFIG.axilite_master_size {1} \
CONFIG.axisten_freq {125} \
CONFIG.cfg_mgmt_if {false} \
CONFIG.pcie_extended_tag {false} \
CONFIG.pciebar2axibar_axil_master {0x40000000} \
CONFIG.pf0_device_id {7022} \
CONFIG.pf0_link_status_slot_clock_config {true} \
CONFIG.pf0_msi_enabled {false} \
......@@ -1086,42 +1063,34 @@ proc create_root_design { parentCell } {
] $xdma_0
# Create interface connections
connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports gpio_rtl_0] [get_bd_intf_pins axi_gpio_0/GPIO]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_ports M00_AXI_0] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_hwicap_0/S_AXI_LITE] [get_bd_intf_pins smartconnect_0/M01_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins processing_system7_0/S_AXI_GP0] [get_bd_intf_pins smartconnect_0/M02_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins processing_system7_0/S_AXI_GP0] [get_bd_intf_pins smartconnect_0/M01_AXI]
connect_bd_intf_net -intf_net xdma_0_M_AXIS_H2C_0 [get_bd_intf_pins xdma_0/M_AXIS_H2C_0] [get_bd_intf_pins xdma_0/S_AXIS_C2H_0]
connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pcie_mgt_0] [get_bd_intf_pins xdma_0/pcie_mgt]
# Create port connections
connect_bd_net -net aclk1_0_1 [get_bd_ports aclk1_0] [get_bd_pins axi_hwicap_0/icap_clk] [get_bd_pins smartconnect_0/aclk1]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
connect_bd_net -net aclk1_0_1 [get_bd_ports aclk1_0] [get_bd_pins smartconnect_0/aclk1]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
connect_bd_net -net sys_clk_0_1 [get_bd_ports pcie_clk] [get_bd_pins xdma_0/sys_clk]
connect_bd_net -net sys_rst_n_0_1 [get_bd_ports pcie_rst_n] [get_bd_pins xdma_0/sys_rst_n]
connect_bd_net -net usr_irq_req_0_1 [get_bd_ports usr_irq_req_0] [get_bd_pins xdma_0/usr_irq_req]
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_hwicap_0/s_axi_aclk] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins smartconnect_0/aclk] [get_bd_pins xdma_0/axi_aclk]
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_hwicap_0/s_axi_aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins xdma_0/axi_aresetn]
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins smartconnect_0/aclk] [get_bd_pins xdma_0/axi_aclk]
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins smartconnect_0/aresetn] [get_bd_pins xdma_0/axi_aresetn]
connect_bd_net -net xdma_0_user_lnk_up [get_bd_ports user_lnk_up_0] [get_bd_pins xdma_0/user_lnk_up]
connect_bd_net -net xdma_0_usr_irq_ack [get_bd_ports usr_irq_ack_0] [get_bd_pins xdma_0/usr_irq_ack]
# Create address segments
assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_LITE] [get_bd_addr_segs M00_AXI_0/Reg] -force
assign_bd_address -offset 0x10000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_hwicap_0/S_AXI_LITE/Reg] -force
assign_bd_address -offset 0xE0000000 -range 0x00400000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_LITE] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_IOP] -force
assign_bd_address -offset 0x40000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_LITE] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0] -force
assign_bd_address -offset 0x40000000 -range 0x00080000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_LITE] [get_bd_addr_segs M00_AXI_0/Reg] -force
assign_bd_address -offset 0x40080000 -range 0x00080000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_LITE] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0] -force
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
......@@ -1134,5 +1103,3 @@ proc create_root_design { parentCell } {
create_root_design ""
common::send_msg_id "BD_TCL-1000" "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
top/spec7_ref_design/spec7_wr_ref_top.vhd
View file @ 43b3139d
......@@ -221,7 +221,32 @@ entity spec7_wr_ref_top is
rxn : in std_logic_vector(1 downto 0);
rxp : in std_logic_vector(1 downto 0);
txn : out std_logic_vector(1 downto 0);
txp : out std_logic_vector(1 downto 0)
txp : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- Processing System interface
---------------------------------------------------------------------------
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end entity spec7_wr_ref_top;
......@@ -296,6 +321,8 @@ architecture top of spec7_wr_ref_top is
--Axi4
signal m_axil_i : t_axi4_lite_master_in_32;
signal m_axil_o : t_axi4_lite_master_out_32;
signal araddr : std_logic_vector(31 downto 0);
signal awaddr : std_logic_vector(31 downto 0);
--Wishbone
signal wb_master_i : t_wishbone_master_in;
......@@ -320,53 +347,82 @@ begin -- architecture top
CEB => '0'
);
Pcie: Pcie_wrapper
port map (
M00_AXI_0_araddr => m_axil_o.araddr,
M00_AXI_0_arburst => open,
M00_AXI_0_arcache => open,
M00_AXI_0_arlen => open,
M00_AXI_0_arlock => open,
M00_AXI_0_arprot => open,
M00_AXI_0_arqos => open,
M00_AXI_0_arready => m_axil_i.arready,
M00_AXI_0_arsize => open,
M00_AXI_0_arvalid => m_axil_o.arvalid,
M00_AXI_0_awaddr => m_axil_o.awaddr,
M00_AXI_0_awburst => open,
M00_AXI_0_awcache => open,
M00_AXI_0_awlen => open,
M00_AXI_0_awlock => open,
M00_AXI_0_awprot => open,
M00_AXI_0_awqos => open,
M00_AXI_0_awready => m_axil_i.awready,
M00_AXI_0_awsize => open,
M00_AXI_0_awvalid => m_axil_o.awvalid,
M00_AXI_0_bready => m_axil_o.bready,
M00_AXI_0_bresp => m_axil_i.bresp,
M00_AXI_0_bvalid => m_axil_i.bvalid,
M00_AXI_0_rdata => m_axil_i.rdata,
M00_AXI_0_rlast => m_axil_i.rlast,
M00_AXI_0_rready => m_axil_o.rready,
M00_AXI_0_rresp => m_axil_i.rresp,
M00_AXI_0_rvalid => m_axil_i.rvalid,
M00_AXI_0_wdata => m_axil_o.wdata,
M00_AXI_0_wlast => m_axil_o.wlast,
M00_AXI_0_wready => m_axil_i.wready,
M00_AXI_0_wstrb => m_axil_o.wstrb,
M00_AXI_0_wvalid => m_axil_o.wvalid,
aclk1_0 => clk_sys_62m5,
pcie_mgt_0_rxn => rxn,
pcie_mgt_0_rxp => rxp,
pcie_mgt_0_txn => txn,
pcie_mgt_0_txp => txp,
pcie_clk => pci_clk,
pcie_rst_n => perst_n,
user_lnk_up_0 => open,
usr_irq_ack_0 => open,
usr_irq_req_0 => "0"
);
Pcie: processing_system_pcie_wrapper
port map (
DDR_addr =>DDR_addr ,
DDR_ba =>DDR_ba ,
DDR_cas_n =>DDR_cas_n ,
DDR_ck_n =>DDR_ck_n ,
DDR_ck_p =>DDR_ck_p ,
DDR_cke =>DDR_cke ,
DDR_cs_n =>DDR_cs_n ,
DDR_dm =>DDR_dm ,
DDR_dq =>DDR_dq ,
DDR_dqs_n =>DDR_dqs_n ,
DDR_dqs_p =>DDR_dqs_p ,
DDR_odt =>DDR_odt ,
DDR_ras_n =>DDR_ras_n ,
DDR_reset_n =>DDR_reset_n ,
DDR_we_n =>DDR_we_n ,
FIXED_IO_ddr_vrn =>FIXED_IO_ddr_vrn ,
FIXED_IO_ddr_vrp =>FIXED_IO_ddr_vrp ,
FIXED_IO_mio =>FIXED_IO_mio ,
FIXED_IO_ps_clk =>FIXED_IO_ps_clk ,
FIXED_IO_ps_porb =>FIXED_IO_ps_porb ,
FIXED_IO_ps_srstb =>FIXED_IO_ps_srstb,
M00_AXI_0_araddr => araddr,
M00_AXI_0_arburst => open,
M00_AXI_0_arcache => open,
M00_AXI_0_arlen => open,
M00_AXI_0_arlock => open,
M00_AXI_0_arprot => open,
M00_AXI_0_arqos => open,
M00_AXI_0_arready => m_axil_i.arready,
M00_AXI_0_arsize => open,
M00_AXI_0_arvalid => m_axil_o.arvalid,
M00_AXI_0_awaddr => awaddr,
M00_AXI_0_awburst => open,
M00_AXI_0_awcache => open,
M00_AXI_0_awlen => open,
M00_AXI_0_awlock => open,
M00_AXI_0_awprot => open,
M00_AXI_0_awqos => open,
M00_AXI_0_awready => m_axil_i.awready,
M00_AXI_0_awsize => open,
M00_AXI_0_awvalid => m_axil_o.awvalid,
M00_AXI_0_bready => m_axil_o.bready,
M00_AXI_0_bresp => m_axil_i.bresp,
M00_AXI_0_bvalid => m_axil_i.bvalid,
M00_AXI_0_rdata => m_axil_i.rdata,
M00_AXI_0_rlast => m_axil_i.rlast,
M00_AXI_0_rready => m_axil_o.rready,
M00_AXI_0_rresp => m_axil_i.rresp,
M00_AXI_0_rvalid => m_axil_i.rvalid,
M00_AXI_0_wdata => m_axil_o.wdata,
M00_AXI_0_wlast => m_axil_o.wlast,
M00_AXI_0_wready => m_axil_i.wready,
M00_AXI_0_wstrb => m_axil_o.wstrb,
M00_AXI_0_wvalid => m_axil_o.wvalid,
aclk1_0 => clk_sys_62m5,
pcie_clk => pci_clk,
pcie_mgt_0_rxn => rxn,
pcie_mgt_0_rxp => rxp,
pcie_mgt_0_txn => txn,
pcie_mgt_0_txp => txp,
pcie_rst_n => perst_n,
user_lnk_up_0 => open,
usr_irq_ack_0 => open,
usr_irq_req_0 => "0"
);
m_axil_o.araddr(31 downto 28) <= x"0";
m_axil_o.araddr(27 downto 0) <= araddr(27 downto 0); --compensates for the PCI 0x4XXXXXXX offset
m_axil_o.awaddr(31 downto 28) <= x"0"; --not my cleanest fix....
m_axil_o.awaddr(27 downto 0) <= awaddr(27 downto 0);
-----------------------------------------------------------------------------
-- Axi to Wishbone converter
-----------------------------------------------------------------------------
AXI2WB : xwb_axi4lite_bridge
port map(
clk_sys_i => clk_sys_62m5,
......
top/spec7_write_design/spec7_write_top.vhd
View file @ 43b3139d
......@@ -300,6 +300,8 @@ architecture top of spec7_write_top is
--Axi4
signal m_axil_i : t_axi4_lite_master_in_32;
signal m_axil_o : t_axi4_lite_master_out_32;
signal araddr : std_logic_vector(31 downto 0);
signal awaddr : std_logic_vector(31 downto 0);
--Wishbone
signal wb_master_i : t_wishbone_master_in;
......@@ -366,7 +368,7 @@ Pcie: processing_system_pcie_wrapper
FIXED_IO_ps_clk =>FIXED_IO_ps_clk ,
FIXED_IO_ps_porb =>FIXED_IO_ps_porb ,
FIXED_IO_ps_srstb =>FIXED_IO_ps_srstb,
M00_AXI_0_araddr => m_axil_o.araddr,
M00_AXI_0_araddr => araddr,
M00_AXI_0_arburst => open,
M00_AXI_0_arcache => open,
M00_AXI_0_arlen => open,
......@@ -376,7 +378,7 @@ Pcie: processing_system_pcie_wrapper
M00_AXI_0_arready => m_axil_i.arready,
M00_AXI_0_arsize => open,
M00_AXI_0_arvalid => m_axil_o.arvalid,
M00_AXI_0_awaddr => m_axil_o.awaddr,
M00_AXI_0_awaddr => awaddr,
M00_AXI_0_awburst => open,
M00_AXI_0_awcache => open,
M00_AXI_0_awlen => open,
......@@ -398,9 +400,8 @@ Pcie: processing_system_pcie_wrapper
M00_AXI_0_wlast => m_axil_o.wlast,
M00_AXI_0_wready => m_axil_i.wready,
M00_AXI_0_wstrb => m_axil_o.wstrb,
M00_AXI_0_wvalid => m_axil_o.wvalid,
M00_AXI_0_wvalid => m_axil_o.wvalid,
aclk1_0 => clk_sys_62m5,
gpio_rtl_0_tri_o => open,
pcie_clk => pci_clk,
pcie_mgt_0_rxn => rxn,
pcie_mgt_0_rxp => rxp,
......@@ -411,7 +412,15 @@ Pcie: processing_system_pcie_wrapper
usr_irq_ack_0 => open,
usr_irq_req_0 => "0"
);
m_axil_o.araddr(31 downto 28) <= x"0";
m_axil_o.araddr(27 downto 0) <= araddr(27 downto 0); --compensates for the PCI 0x4XXXXXXX offset
m_axil_o.awaddr(31 downto 28) <= x"0"; --not my cleanest fix....
m_axil_o.awaddr(27 downto 0) <= awaddr(27 downto 0);
-----------------------------------------------------------------------------
-- Axi to Wishbone converter
-----------------------------------------------------------------------------
AXI2WB : xwb_axi4lite_bridge
port map(
clk_sys_i => clk_sys_62m5,
......
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