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White Rabbit core collection
Commit 3b79ddb6 authored by Maciej Lipinski's avatar Maciej Lipinski
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wr_streamers: update WB registers: bump version, remove unnecessary register

parent 800592f9
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Showing with 20 additions and 48 deletions
modules/wr_streamers/wr_streamers_wb.vhd
View file @ 3b79ddb6
......@@ -3,8 +3,8 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wb.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed May 22 19:52:32 2019
-- Version : 0x00000001
-- Created : Thu May 23 16:11:14 2019
-- Version : 0x00000002
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
......@@ -99,7 +99,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
wr_streamers_ver_id_int <= "00000000000000000000000000000001";
wr_streamers_ver_id_int <= "00000000000000000000000000000010";
wr_streamers_sscr1_rst_stats_int <= '0';
wr_streamers_sscr1_rst_seq_id_int <= '0';
wr_streamers_sscr1_snapshot_stats_int <= '0';
......@@ -633,48 +633,42 @@ begin
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat14_rx_buf_overflow_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat15_rx_late_frames_cnt_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100101" =>
when "100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat16_rx_late_frames_cnt_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100110" =>
when "100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat17_rx_timeout_frames_cnt_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100111" =>
when "100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat18_rx_timeout_frames_cnt_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101000" =>
when "100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat19_rx_match_frames_cnt_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101001" =>
when "101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat20_rx_match_frames_cnt_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101010" =>
when "101001" =>
if (wb_we_i = '1') then
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int <= wrdata_reg(27 downto 0);
end if;
......@@ -817,7 +811,6 @@ begin
end process;
-- WR Streamer RX Buffer Overflow Count
-- WR Streamer RX Late Frames Count (LSB)
-- WR Streamer RX Late Frames Count (MSB)
-- WR Streamer RX Timed-out Frames Count (LSB)
......
modules/wr_streamers/wr_streamers_wb.wb
View file @ 3b79ddb6
......@@ -28,7 +28,7 @@ peripheral {
-----------------------------------------------------------------";
prefix = "wr_streamers";
hdl_entity = "wr_streamers_wb";
version= 1;
version= 2;
reg {
name = "Statistics status and ctrl register";
......@@ -645,21 +645,6 @@ peripheral {
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT14";
field {
name = "WR Streamer RX Buffer Overflow Count";
description = "Number of RX buffer overflow events";
prefix = "RX_BUF_OVERFLOW_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT15";
......
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @ 3b79ddb6
......@@ -3,8 +3,8 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed May 22 19:52:32 2019
-- Version : 0x00000001
-- Created : Thu May 23 16:11:14 2019
-- Version : 0x00000002
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
......@@ -41,7 +41,6 @@ package wr_streamers_wbgen2_pkg is
rx_stat13_rx_latency_acc_cnt_msb_i : std_logic_vector(31 downto 0);
dbg_data_i : std_logic_vector(31 downto 0);
dummy_dummy_i : std_logic_vector(31 downto 0);
rx_stat14_rx_buf_overflow_cnt_i : std_logic_vector(31 downto 0);
rx_stat15_rx_late_frames_cnt_lsb_i : std_logic_vector(31 downto 0);
rx_stat16_rx_late_frames_cnt_msb_i : std_logic_vector(31 downto 0);
rx_stat17_rx_timeout_frames_cnt_lsb_i : std_logic_vector(31 downto 0);
......@@ -71,7 +70,6 @@ package wr_streamers_wbgen2_pkg is
rx_stat13_rx_latency_acc_cnt_msb_i => (others => '0'),
dbg_data_i => (others => '0'),
dummy_dummy_i => (others => '0'),
rx_stat14_rx_buf_overflow_cnt_i => (others => '0'),
rx_stat15_rx_late_frames_cnt_lsb_i => (others => '0'),
rx_stat16_rx_late_frames_cnt_msb_i => (others => '0'),
rx_stat17_rx_timeout_frames_cnt_lsb_i => (others => '0'),
......@@ -224,7 +222,6 @@ tmp.rx_stat12_rx_latency_acc_cnt_lsb_i := f_x_to_zero(left.rx_stat12_rx_latency_
tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_acc_cnt_msb_i) or f_x_to_zero(right.rx_stat13_rx_latency_acc_cnt_msb_i);
tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
tmp.rx_stat14_rx_buf_overflow_cnt_i := f_x_to_zero(left.rx_stat14_rx_buf_overflow_cnt_i) or f_x_to_zero(right.rx_stat14_rx_buf_overflow_cnt_i);
tmp.rx_stat15_rx_late_frames_cnt_lsb_i := f_x_to_zero(left.rx_stat15_rx_late_frames_cnt_lsb_i) or f_x_to_zero(right.rx_stat15_rx_late_frames_cnt_lsb_i);
tmp.rx_stat16_rx_late_frames_cnt_msb_i := f_x_to_zero(left.rx_stat16_rx_late_frames_cnt_msb_i) or f_x_to_zero(right.rx_stat16_rx_late_frames_cnt_msb_i);
tmp.rx_stat17_rx_timeout_frames_cnt_lsb_i := f_x_to_zero(left.rx_stat17_rx_timeout_frames_cnt_lsb_i) or f_x_to_zero(right.rx_stat17_rx_timeout_frames_cnt_lsb_i);
......
sim/wr_streamers_wb.svh
View file @ 3b79ddb6
`define WBGEN2_WR_STREAMERS_VERSION 32'h00000001
`define WBGEN2_WR_STREAMERS_VERSION 32'h00000002
`define ADDR_WR_STREAMERS_VER 8'h0
`define WR_STREAMERS_VER_ID_OFFSET 0
`define WR_STREAMERS_VER_ID 32'hffffffff
......@@ -138,27 +138,24 @@
`define ADDR_WR_STREAMERS_RSTR 8'h88
`define WR_STREAMERS_RSTR_RST_SW_OFFSET 0
`define WR_STREAMERS_RSTR_RST_SW 32'h00000001
`define ADDR_WR_STREAMERS_RX_STAT14 8'h8c
`define WR_STREAMERS_RX_STAT14_RX_BUF_OVERFLOW_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT14_RX_BUF_OVERFLOW_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT15 8'h90
`define ADDR_WR_STREAMERS_RX_STAT15 8'h8c
`define WR_STREAMERS_RX_STAT15_RX_LATE_FRAMES_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT15_RX_LATE_FRAMES_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT16 8'h94
`define ADDR_WR_STREAMERS_RX_STAT16 8'h90
`define WR_STREAMERS_RX_STAT16_RX_LATE_FRAMES_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT16_RX_LATE_FRAMES_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT17 8'h98
`define ADDR_WR_STREAMERS_RX_STAT17 8'h94
`define WR_STREAMERS_RX_STAT17_RX_TIMEOUT_FRAMES_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT17_RX_TIMEOUT_FRAMES_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT18 8'h9c
`define ADDR_WR_STREAMERS_RX_STAT18 8'h98
`define WR_STREAMERS_RX_STAT18_RX_TIMEOUT_FRAMES_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT18_RX_TIMEOUT_FRAMES_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT19 8'ha0
`define ADDR_WR_STREAMERS_RX_STAT19 8'h9c
`define WR_STREAMERS_RX_STAT19_RX_MATCH_FRAMES_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT19_RX_MATCH_FRAMES_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT20 8'ha4
`define ADDR_WR_STREAMERS_RX_STAT20 8'ha0
`define WR_STREAMERS_RX_STAT20_RX_MATCH_FRAMES_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT20_RX_MATCH_FRAMES_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG6 8'ha8
`define ADDR_WR_STREAMERS_RX_CFG6 8'ha4
`define WR_STREAMERS_RX_CFG6_RX_FIXED_LATENCY_TIMEOUT_OFFSET 0
`define WR_STREAMERS_RX_CFG6_RX_FIXED_LATENCY_TIMEOUT 32'h0fffffff
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