Commit 3b347340 authored by Peter Jansweijer's avatar Peter Jansweijer

replace dio(1) with 62.5 MHz out clock

parent 054200a6
Pipeline #2033 failed with stage
in 0 seconds
......@@ -501,7 +501,7 @@ begin -- architecture top
wrc_pps_in <= dio_in(3);
dio_out(0) <= wrc_pps_out;
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(1) <= clk_ref_div2;
dio_out(2) <= wrc_abscal_txts_out;
-- LEDs
......
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