Commit 38623a1a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

update

parent 423d90cc
modules = {"local" :
[ "platform/xilinx/wr_gtp_phy",
"modules/timing",
"modules/wr_mini_nic",
"modules/wr_softpll",
"modules/wrc_lm32",
"modules/wrc_core",
"modules/wrsw_endpoint",
"modules/wrsw_pps_gen" ]}
\ No newline at end of file
files = ["dmtd_phase_meas.vhd",
"dmtd_with_deglitcher.vhd",
"multi_dmtd_with_deglitcher.vhd" ]
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd" ]
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-04-18
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -45,7 +45,7 @@ use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.common_components.all;
use work.gencores_pkg.all;
entity dmtd_phase_meas is
generic (
......@@ -83,19 +83,17 @@ architecture syn of dmtd_phase_meas is
generic (
g_counter_bits : natural);
port (
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
clk_in_i : in std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p_o : out std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_thr_lo_i : in std_logic_vector(11 downto 0);
deglitch_thr_hi_i : in std_logic_vector(11 downto 0);
deglitch_thr_glitch_i : in std_logic_vector(7 downto 0);
dbg_dmtdout_o : out std_logic);
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_in_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_threshold_i : in std_logic_vector(15 downto 0);
dbg_dmtdout_o : out std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p1_o : out std_logic);
end component;
type t_pd_state is (PD_WAIT_TAG, PD_WAIT_A, PD_WAIT_B);
......@@ -128,7 +126,7 @@ begin -- syn
rst_n_sysclk <= rst_n_i;
-- reset sync for DMTD sampling clock
sync_reset_dmtdclk : sync_ffs
sync_reset_dmtdclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -149,12 +147,10 @@ begin -- syn
clk_sys_i => clk_sys_i,
clk_in_i => clk_a_i,
tag_o => tag_a,
tag_stb_p_o => tag_a_p,
tag_stb_p1_o => tag_a_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_thr_lo_i => std_logic_vector(to_unsigned(g_deglitch_thr_lo, 12)),
deglitch_thr_hi_i => std_logic_vector(to_unsigned(g_deglitch_thr_hi, 12)),
deglitch_thr_glitch_i => std_logic_vector(to_unsigned(g_deglitch_thr_glitch, 8)),
deglitch_threshold_i => std_logic_vector(to_unsigned(g_deglitcher_threshold, 16)),
dbg_dmtdout_o => open);
DMTD_B : dmtd_with_deglitcher
......@@ -167,12 +163,10 @@ begin -- syn
clk_sys_i => clk_sys_i,
clk_in_i => clk_b_i,
tag_o => tag_b,
tag_stb_p_o => tag_b_p,
tag_stb_p1_o => tag_b_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_thr_lo_i => std_logic_vector(to_unsigned(g_deglitch_thr_lo, 12)),
deglitch_thr_hi_i => std_logic_vector(to_unsigned(g_deglitch_thr_hi, 12)),
deglitch_thr_glitch_i => std_logic_vector(to_unsigned(g_deglitch_thr_glitch, 8)),
deglitch_threshold_i => std_logic_vector(to_unsigned(g_deglitcher_threshold, 16)),
dbg_dmtdout_o => open);
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-04-18
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -46,7 +46,7 @@ use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.common_components.all;
use work.gencores_pkg.all;
entity dmtd_with_deglitcher is
generic (
......@@ -83,13 +83,13 @@ entity dmtd_with_deglitcher is
deglitch_threshold_i : in std_logic_vector(15 downto 0);
-- [clk_dmtd_i] raw DDMTD output (for debugging purposes)
dbg_dmtdout_o : out std_logic
dbg_dmtdout_o : out std_logic;
-- [clk_sys_i] deglitched edge tag value
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
-- [clk_sys_i] pulse indicates new phase tag on tag_o
tag_stb_p1_o : out std_logic;
tag_stb_p1_o : out std_logic
);
end dmtd_with_deglitcher;
......@@ -147,7 +147,7 @@ begin -- rtl
case state is
when WAIT_STABLE_0 => -- out-of-sync
new_edge_sreg <= '0' & new_edge_sreg(new_edge_sreg'length downto 1);
new_edge_sreg <= '0' & new_edge_sreg(new_edge_sreg'length-1 downto 1);
if clk_i_d3 /= '0' then
stab_cntr <= (others => '0');
......@@ -184,9 +184,9 @@ begin -- rtl
end case;
end if;
end if;
end process deglitch;
end process p_deglitch;
U_sync_tag_strobe : sync_ffs
U_sync_tag_strobe : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -197,7 +197,7 @@ begin -- rtl
npulse_o => open,
ppulse_o => new_edge_p);
tag_stb_p_o <= new_edge_p;
tag_stb_p1_o <= new_edge_p;
tag_o <= std_logic_vector(tag_int);
dbg_dmtdout_o <= clk_i_d3;
end rtl;
......@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.common_components.all;
use work.gencores_pkg.all;
entity multi_dmtd_with_deglitcher is
generic (
......@@ -195,7 +195,7 @@ begin -- rtl
--n_zeroes <= f_count_zeroes(dmtd_in);
sync_reset_refclk : sync_ffs
sync_reset_refclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......
files = [ "minic_packet_buffer.vhd",
"minic_wb_slave.vhd",
"wr_mini_nic.vhd",
"wr_minic_ep_combo.vhd"];
"wr_mini_nic.vhd" ];
......@@ -13,8 +13,8 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library wbgen2;
use wbgen2.wbgen2_pkg.all;
use work.wbgen2_pkg.all;
entity minic_wb_slave is
port (
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 2011-03-27
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -29,7 +29,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global_defs.all;
use work.endpoint_pkg.all;
entity wr_mini_nic is
......@@ -56,7 +56,7 @@ entity wr_mini_nic is
-------------------------------------------------------------------------------
src_data_o : out std_logic_vector(15 downto 0);
src_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
src_ctrl_o : out std_logic_vector(4 - 1 downto 0);
src_bytesel_o : out std_logic;
src_sof_p1_o : out std_logic;
src_eof_p1_o : out std_logic;
......@@ -66,7 +66,7 @@ entity wr_mini_nic is
src_error_p1_i : in std_logic;
snk_data_i : in std_logic_vector(15 downto 0);
snk_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
snk_ctrl_i : in std_logic_vector(4 - 1 downto 0);
snk_bytesel_i : in std_logic;
snk_sof_p1_i : in std_logic;
snk_eof_p1_i : in std_logic;
......@@ -80,8 +80,8 @@ entity wr_mini_nic is
-------------------------------------------------------------------------------
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_tsval_i : in std_logic_vector(c_wrsw_timestamp_size_r + c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
......
......@@ -13,8 +13,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library wbgen2;
use wbgen2.wbgen2_pkg.all;
use work.wbgen2_pkg.all;
entity softpll_wb is
port (
......
......@@ -2,8 +2,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common_components.all;
use work.gencores_pkg.all;
entity wr_softpll is
generic(
......@@ -63,21 +62,19 @@ architecture rtl of wr_softpll is
generic (
g_counter_bits : natural);
port (
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
clk_in_i : in std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p_o : out std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_thr_lo_i : in std_logic_vector(11 downto 0);
deglitch_thr_hi_i : in std_logic_vector(11 downto 0);
deglitch_thr_glitch_i : in std_logic_vector(7 downto 0);
dbg_dmtdout_o : out std_logic);
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_in_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_threshold_i : in std_logic_vector(15 downto 0);
dbg_dmtdout_o : out std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p1_o : out std_logic);
end component;
component softpll_wb
port (
rst_n_i : in std_logic;
......@@ -174,7 +171,7 @@ architecture rtl of wr_softpll is
begin -- rtl
sync_ffs_rst1 : sync_ffs
sync_ffs_rst1 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -185,7 +182,7 @@ begin -- rtl
npulse_o => open,
ppulse_o => open);
sync_ffs_rst2 : sync_ffs
sync_ffs_rst2 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -196,7 +193,7 @@ begin -- rtl
npulse_o => open,
ppulse_o => open);
sync_ffs_rst3 : sync_ffs
sync_ffs_rst3 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -266,12 +263,10 @@ begin -- rtl
clk_in_i => clk_rx_buf,
tag_o => tag_ref,
tag_stb_p_o => tag_ref_p,
tag_stb_p1_o => tag_ref_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_thr_lo_i => deglitch_thr_slv(11 downto 0),
deglitch_thr_hi_i => "000000000000",
deglitch_thr_glitch_i => "00000000",
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
DMTD_FB : dmtd_with_deglitcher
......@@ -286,12 +281,11 @@ begin -- rtl
clk_in_i => clk_ref_buf,
tag_o => tag_fb,
tag_stb_p_o => tag_fb_p,
tag_stb_p1_o => tag_fb_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_thr_lo_i => deglitch_thr_slv(11 downto 0),
deglitch_thr_hi_i => "000000000000",
deglitch_thr_glitch_i => "00000000",
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
end generate gen_with_single_dmtd;
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2011-04-18
-- Last update: 2011-05-11
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -32,7 +32,6 @@ use ieee.std_logic_1164.all;
library work;
use work.wrcore_pkg.all;
use work.global_defs.all;
use work.wbconmax_pkg.all;
entity wr_core is
......@@ -140,99 +139,6 @@ end wr_core;
architecture struct of wr_core is
component wr_helper_pll
generic (
g_num_ref_inputs : integer := 1;
g_with_wishbone : integer := 1;
g_dacval_bits : integer := 16;
g_output_bias : integer := 32767;
g_div_ref : integer := 0;
g_div_fb : integer := 0;
g_kp_freq : integer := 0;
g_ki_freq : integer := 0;
g_kp_phase : integer := 0;
g_ki_phase : integer := 0;
g_ld_threshold : integer := 0;
g_ld_samples : integer := 0;
g_fd_gating : integer := 0;
g_pd_gating : integer := 0;
g_ferr_setpoint : integer := 0);
port (
rst_n_i : in std_logic;
cfg_enable_i : in std_logic;
cfg_force_freq_i : in std_logic;
cfg_clear_status_i : in std_logic;
cfg_refsel_i : in std_logic_vector(1 downto 0);
stat_flock_o : out std_logic;
stat_plock_o : out std_logic;
stat_lock_lost_o : out std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_sys_i : in std_logic;
clk_fbck_i : in std_logic;
dac_data_o : out std_logic_vector(g_dacval_bits-1 downto 0);
dac_load_p1_o : out std_logic;
auxout1_o : out std_logic;
auxout2_o : out std_logic;
auxout3_o : out std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
component wr_dmtd_pll
generic (
g_num_ref_inputs : integer := 1;
g_with_debug_fifo : integer := 0;
g_with_wishbone : integer := 1;
g_dacval_bits : integer := 16;
g_output_bias : integer := 32767;
g_kp_freq : integer := 0;
g_ki_freq : integer := 0;
g_kp_phase : integer := 0;
g_ki_phase : integer := 0;
g_ld_threshold : integer := 0;
g_ld_samples : integer := 0;
g_ref_gthr_lo : integer := 0;
g_ref_gthr_hi : integer := 0;
g_ref_gthr_glitch : integer := 0;
g_fb_gthr_lo : integer := 0;
g_fb_gthr_hi : integer := 0;
g_fb_gthr_glitch : integer := 0;
g_pshifter_speed : integer := 0);
port (
rst_n_i : in std_logic;
cfg_enable_i : in std_logic;
cfg_force_freq_i : in std_logic;
cfg_clear_status_i : in std_logic;
cfg_pshift_load_p1_i : in std_logic;
cfg_pshift_val_i : in std_logic_vector(23 downto 0);
stat_flock_o : out std_logic;
stat_plock_o : out std_logic;
stat_lock_lost_o : out std_logic;
stat_pshift_busy_o : out std_logic;
clk_sys_i : in std_logic;
clk_fbck_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
dac_data_o : out std_logic_vector(g_dacval_bits-1 downto 0);
dac_load_p1_o : out std_logic;
auxout1_o : out std_logic;
auxout2_o : out std_logic;
auxout3_o : out std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
signal s_rst : std_logic;
......@@ -257,7 +163,7 @@ architecture struct of wr_core is
--Endpoint
-----------------------------------------------------------------------------
signal s_ep_rx_data_o : std_logic_vector(15 downto 0);
signal s_ep_rx_ctrl_o : std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
signal s_ep_rx_ctrl_o : std_logic_vector(4 - 1 downto 0);
signal s_ep_rx_bytesel_o : std_logic;
signal s_ep_rx_sof_p1_o : std_logic;
signal s_ep_rx_eof_p1_o : std_logic;
......@@ -266,7 +172,7 @@ architecture struct of wr_core is
signal s_ep_rx_rerror_p1_o : std_logic;
signal s_ep_tx_data_i : std_logic_vector(15 downto 0);
signal s_ep_tx_ctrl_i : std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
signal s_ep_tx_ctrl_i : std_logic_vector(4 - 1 downto 0);
signal s_ep_tx_bytesel_i : std_logic;
signal s_ep_tx_sof_p1_i : std_logic;
signal s_ep_tx_eof_p1_i : std_logic;
......@@ -275,9 +181,8 @@ architecture struct of wr_core is
signal s_ep_tx_terror_p1_o : std_logic;
signal txtsu_port_id_o : std_logic_vector(4 downto 0);
signal txtsu_frame_id_o : std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
signal txtsu_tsval_o : std_logic_vector(c_wrsw_timestamp_size_r +
c_wrsw_timestamp_size_f - 1 downto 0);
signal txtsu_frame_id_o : std_logic_vector(16 -1 downto 0);
signal txtsu_tsval_o : std_logic_vector(28 + 4 - 1 downto 0);
signal txtsu_valid_o : std_logic;
signal txtsu_ack_i : std_logic;
......@@ -432,6 +337,7 @@ begin
wb_ack_o => ppsg_wb_o.ack,
-- Single-pulse PPS output for synchronizing endpoint to
pps_in_i => '0',
pps_csync_o => s_pps_csync,
pps_out_o => pps_p_o
);
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-15
-- Last update: 2011-04-07
-- Last update: 2011-05-11
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -73,7 +73,7 @@ begin
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
-- g_init_file => g_init_file,
g_dual_clock => g_dual_clock
)
port map(
......
......@@ -2,8 +2,6 @@ library ieee;
use ieee.std_logic_1164.all;
library work;
use work.global_defs.all;
use work.wrczpu_pkg.all;
use work.genram_pkg.all;
use work.wbconmax_pkg.all;
......@@ -23,29 +21,25 @@ package wrcore_pkg is
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
component wrsw_pps_gen is
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Single-pulse PPS output for synchronizing endpoint to
pps_csync_o : out std_logic;
pps_out_o : out std_logic
);
component wrsw_pps_gen
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic);
end component;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--WR Endpoint
-----------------------------------------------------------------------------
component wrsw_endpoint is
......@@ -83,7 +77,7 @@ package wrcore_pkg is
gtp_loopen_o : out std_logic;
--WRF Source
rx_data_o : out std_logic_vector(15 downto 0);
rx_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
rx_ctrl_o : out std_logic_vector(4 - 1 downto 0);
rx_bytesel_o : out std_logic;
rx_sof_p1_o : out std_logic;
rx_eof_p1_o : out std_logic;
......@@ -94,7 +88,7 @@ package wrcore_pkg is
rx_rerror_p1_o : out std_logic;
--WRF Sink
tx_data_i : in std_logic_vector(15 downto 0);
tx_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
tx_ctrl_i : in std_logic_vector(4 -1 downto 0);
tx_bytesel_i : in std_logic;
tx_sof_p1_i : in std_logic;
tx_eof_p1_i : in std_logic;
......@@ -105,19 +99,19 @@ package wrcore_pkg is
tx_terror_p1_o : out std_logic;
--TXTSU
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_frame_id_o : out std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_tsval_o : out std_logic_vector(c_wrsw_timestamp_size_r + c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
txtsu_tsval_o : out std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_o : out std_logic;
txtsu_ack_i : in std_logic;
--RTU
rtu_full_i : in std_logic;
rtu_almost_full_i : in std_logic;
rtu_rq_strobe_p1_o : out std_logic;
rtu_rq_smac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(c_wrsw_vid_width - 1 downto 0);
rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
rtu_rq_has_vid_o : out std_logic;
rtu_rq_prio_o : out std_logic_vector(c_wrsw_prio_width-1 downto 0);
rtu_rq_prio_o : out std_logic_vector(3-1 downto 0);
rtu_rq_has_prio_o : out std_logic;
--WB
wb_cyc_i : in std_logic;
......@@ -194,7 +188,7 @@ package wrcore_pkg is
mem_wr_o : out std_logic;
-- WRF source/sink
src_data_o : out std_logic_vector(15 downto 0);
src_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
src_ctrl_o : out std_logic_vector(4 - 1 downto 0);
src_bytesel_o : out std_logic;
src_sof_p1_o : out std_logic;
src_eof_p1_o : out std_logic;
......@@ -204,7 +198,7 @@ package wrcore_pkg is
src_error_p1_i : in std_logic;
snk_data_i : in std_logic_vector(15 downto 0);
snk_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
snk_ctrl_i : in std_logic_vector(4 -1 downto 0);
snk_bytesel_i : in std_logic;
snk_sof_p1_i : in std_logic;
snk_eof_p1_i : in std_logic;
......@@ -214,9 +208,8 @@ package wrcore_pkg is
snk_error_p1_i : in std_logic;
-- TXTSU i/f
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_tsval_i : in std_logic_vector(c_wrsw_timestamp_size_r +
c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 -1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
--WB
......@@ -232,6 +225,7 @@ package wrcore_pkg is
);
end component;
constant maxAddrBitIncIO : integer := 10;
component wrc_zpu
generic (
......
files = [ "wrc_lm32.vhd", "lm32_top.v" ];
\ No newline at end of file
files = [ "wrc_lm32.vhd",
"lm32_cpu.v",
"lm32_addsub.v",
"lm32_top.v",
"lm32_instruction_unit.v",
"lm32_decoder.v",
"lm32_load_store_unit.v",
"lm32_adder.v",
"lm32_logic_op.v",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_interrupt.v",
"lm32_dp_ram.v"
];
\ No newline at end of file
......@@ -2,11 +2,8 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.global_defs.all;
package endpoint_pkg is
constant c_endpoint_rx_buffer_size : integer := 4096;
constant c_endpoint_rx_buffer_size_log2 : integer := 12;
......@@ -34,6 +31,19 @@ package endpoint_pkg is
constant c_WRF_DATA : std_logic_vector(1 downto 0) := "00";
constant c_WRF_OOB : std_logic_vector(1 downto 0) := "01";
-- fixme: remove these along with the non-WB version of the endpoint
constant c_wrsw_ctrl_none : std_logic_vector(4 - 1 downto 0) := x"0";
constant c_wrsw_ctrl_dst_mac : std_logic_vector(4 - 1 downto 0) := x"1";
constant c_wrsw_ctrl_src_mac : std_logic_vector(4 - 1 downto 0) := x"2";
constant c_wrsw_ctrl_ethertype : std_logic_vector(4 - 1 downto 0) := x"3";
constant c_wrsw_ctrl_vid_prio : std_logic_vector(4 - 1 downto 0) := x"4";
constant c_wrsw_ctrl_tx_oob : std_logic_vector(4 - 1 downto 0) := x"5";
constant c_wrsw_ctrl_rx_oob : std_logic_vector(4 - 1 downto 0) := x"6";
constant c_wrsw_ctrl_payload : std_logic_vector(4 - 1 downto 0) := x"7";
constant c_wrsw_ctrl_fcs : std_logic_vector(4 - 1 downto 0) := x"8";
type t_wrf_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
......@@ -131,7 +141,7 @@ package endpoint_pkg is
pcs_fifo_write_o : out std_logic;
pcs_fifo_almostfull_i : in std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
tx_ctrl_i : in std_logic_vector(4 -1 downto 0);
tx_bytesel_i : in std_logic;
tx_sof_p1_i : in std_logic;
tx_eof_p1_i : in std_logic;
......@@ -169,7 +179,7 @@ package endpoint_pkg is
oob_ack_o : out std_logic;
rbuf_sof_p1_o : out std_logic;
rbuf_eof_p1_o : out std_logic;
rbuf_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
rbuf_ctrl_o : out std_logic_vector(4 - 1 downto 0);
rbuf_data_o : out std_logic_vector(15 downto 0);
rbuf_bytesel_o : out std_logic;
rbuf_valid_o : out std_logic;
......@@ -192,11 +202,11 @@ package endpoint_pkg is
ep_rfcr_fix_prio_i : in std_logic;
ep_rfcr_prio_val_i : in std_logic_vector(2 downto 0);
ep_rfcr_vid_val_i : in std_logic_vector(11 downto 0);
rtu_rq_smac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(c_wrsw_vid_width - 1 downto 0);
rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
rtu_rq_has_vid_o : out std_logic;
rtu_rq_prio_o : out std_logic_vector(c_wrsw_prio_width - 1 downto 0);
rtu_rq_prio_o : out std_logic_vector(3 - 1 downto 0);
rtu_rq_has_prio_o : out std_logic;
rtu_full_i : in std_logic;
rtu_rq_strobe_p1_o : out std_logic);
......@@ -217,14 +227,14 @@ package endpoint_pkg is
pps_csync_p1_i : in std_logic;
tx_timestamp_stb_p_i : in std_logic;
rx_timestamp_stb_p_i : in std_logic;
txoob_fid_i : in std_logic_vector(c_wrsw_oob_frame_id_size - 1 downto 0);
txoob_fid_i : in std_logic_vector(16 - 1 downto 0);
txoob_stb_p_i : in std_logic;
rxoob_data_o : out std_logic_vector(47 downto 0);
rxoob_valid_o : out std_logic;
rxoob_ack_i : in std_logic;
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_fid_o : out std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_tsval_o : out std_logic_vector(c_wrsw_timestamp_size_r + c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_fid_o : out std_logic_vector(16 -1 downto 0);
txtsu_tsval_o : out std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_o : out std_logic;
txtsu_ack_i : in std_logic;
ep_tscr_en_txts_i : in std_logic;
......@@ -260,7 +270,7 @@ package endpoint_pkg is
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
fra_data_i : in std_logic_vector(15 downto 0);
fra_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
fra_ctrl_i : in std_logic_vector(4 -1 downto 0);
fra_sof_p_i : in std_logic;
fra_eof_p_i : in std_logic;
fra_error_p_i : in std_logic;
......@@ -268,7 +278,7 @@ package endpoint_pkg is
fra_drop_o : out std_logic;
fra_bytesel_i : in std_logic;
fab_data_o : out std_logic_vector(15 downto 0);
fab_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
fab_ctrl_o : out std_logic_vector(4 -1 downto 0);
fab_sof_p_o : out std_logic;
fab_eof_p_o : out std_logic;
fab_error_p_o : out std_logic;
......@@ -394,7 +404,7 @@ package endpoint_pkg is
gtp_rst_o : out std_logic;
gtp_loopen_o : out std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
rx_ctrl_o : out std_logic_vector(4 - 1 downto 0);
rx_bytesel_o : out std_logic;
rx_sof_p1_o : out std_logic;
rx_eof_p1_o : out std_logic;
......@@ -404,7 +414,7 @@ package endpoint_pkg is
rx_idle_o : out std_logic;
rx_rerror_p1_o : out std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
tx_ctrl_i : in std_logic_vector(4 -1 downto 0);
tx_bytesel_i : in std_logic;
tx_sof_p1_i : in std_logic;
tx_eof_p1_i : in std_logic;
......@@ -414,18 +424,18 @@ package endpoint_pkg is
tx_tabort_p1_i : in std_logic;
tx_terror_p1_o : out std_logic;
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_frame_id_o : out std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_tsval_o : out std_logic_vector(c_wrsw_timestamp_size_r + c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
txtsu_tsval_o : out std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_o : out std_logic;
txtsu_ack_i : in std_logic;
rtu_full_i : in std_logic := '0';
rtu_almost_full_i : in std_logic := '0';
rtu_rq_strobe_p1_o : out std_logic;
rtu_rq_smac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(c_wrsw_vid_width - 1 downto 0);
rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
rtu_rq_has_vid_o : out std_logic;
rtu_rq_prio_o : out std_logic_vector(c_wrsw_prio_width-1 downto 0);
rtu_rq_prio_o : out std_logic_vector(3-1 downto 0);
rtu_rq_has_prio_o : out std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
......
......@@ -44,8 +44,6 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common_components.all;
use work.endpoint_pkg.all;
entity ep_rmon_counters is
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2011-01-30
-- Last update: 2011-05-11
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -26,10 +26,7 @@ use ieee.numeric_std.all;
library work;
use work.global_defs.all;
use work.common_components.all;
use work.endpoint_pkg.all;
use work.genram_pkg.all;
entity ep_rx_buffer is
......@@ -45,7 +42,7 @@ entity ep_rx_buffer is
-------------------------------------------------------------------------------
fra_data_i : in std_logic_vector(15 downto 0);
fra_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
fra_ctrl_i : in std_logic_vector(4 -1 downto 0);
fra_sof_p_i : in std_logic;
fra_eof_p_i : in std_logic;
fra_error_p_i : in std_logic;
......@@ -58,7 +55,7 @@ entity ep_rx_buffer is
-------------------------------------------------------------------------------
fab_data_o : out std_logic_vector(15 downto 0);
fab_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
fab_ctrl_o : out std_logic_vector(4 -1 downto 0);
fab_sof_p_o : out std_logic;
fab_eof_p_o : out std_logic;
fab_error_p_o : out std_logic;
......@@ -80,19 +77,19 @@ architecture behavioral of ep_rx_buffer is
constant c_drop_threshold : integer := 2**g_size_log2 - 800;
constant c_release_threshold : integer := 2**(g_size_log2-1);
constant c_ctrl_sof : std_logic_vector(c_wrsw_ctrl_size - 1 downto 0) := x"8";
constant c_ctrl_payload_1b : std_logic_vector(c_wrsw_ctrl_size - 1 downto 0) := x"9";
constant c_ctrl_eof : std_logic_vector(c_wrsw_ctrl_size - 1 downto 0) := x"a";
constant c_ctrl_eof_1b : std_logic_vector(c_wrsw_ctrl_size - 1 downto 0) := x"b";
constant c_ctrl_eof_2b : std_logic_vector(c_wrsw_ctrl_size - 1 downto 0) := x"c";
constant c_ctrl_eof_error : std_logic_vector(c_wrsw_ctrl_size - 1 downto 0) := x"d";
constant c_ctrl_sof : std_logic_vector(4 - 1 downto 0) := x"8";
constant c_ctrl_payload_1b : std_logic_vector(4 - 1 downto 0) := x"9";
constant c_ctrl_eof : std_logic_vector(4 - 1 downto 0) := x"a";
constant c_ctrl_eof_1b : std_logic_vector(4 - 1 downto 0) := x"b";
constant c_ctrl_eof_2b : std_logic_vector(4 - 1 downto 0) := x"c";
constant c_ctrl_eof_error : std_logic_vector(4 - 1 downto 0) := x"d";
signal threshold_hit : std_logic;
signal wr_packed_ctrl : std_logic_vector(c_wrsw_ctrl_size-1 downto 0);
signal wr_packed_ctrl : std_logic_vector(4-1 downto 0);
signal wr_valid : std_logic;
signal rd_packed_ctrl : std_logic_vector(c_wrsw_ctrl_size-1 downto 0);
signal rd_packed_ctrl : std_logic_vector(4-1 downto 0);
signal rd_valid : std_logic;
signal fifo_reset_n : std_logic;
......
......@@ -3,8 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.global_defs.all;
use work.common_components.all;
use work.gencores_pkg.all; -- for gc_crc_gen
use work.endpoint_pkg.all;
-- 1st deframing pipeline stage - CRC/PCS error/Size checker
......@@ -86,7 +85,7 @@ begin -- behavioral
crc_gen_reset <= snk_sof_p1_i or (not rst_n_i);
crc_gen_enable <= snk_valid_i;
U_rx_crc_generator : crc_gen
U_rx_crc_generator : gc_crc_gen
generic map (
g_polynomial => x"04C11DB7",
g_init_value => x"ffffffff",
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2011-02-04
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -29,8 +29,6 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.global_defs.all;
use work.common_components.all;
use work.endpoint_pkg.all;
entity ep_rx_deframer is
......@@ -56,7 +54,7 @@ entity ep_rx_deframer is
-- RX Buffer interface
rbuf_sof_p1_o : out std_logic;
rbuf_eof_p1_o : out std_logic;
rbuf_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
rbuf_ctrl_o : out std_logic_vector(4 - 1 downto 0);
rbuf_data_o : out std_logic_vector(15 downto 0);
rbuf_bytesel_o : out std_logic;
rbuf_valid_o : out std_logic;
......@@ -98,15 +96,15 @@ entity ep_rx_deframer is
-------------------------------------------------------------------------------
-- source/MAC address
rtu_rq_smac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
-- VLAN Id/VID present flag
rtu_rq_vid_o : out std_logic_vector(c_wrsw_vid_width - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
rtu_rq_has_vid_o : out std_logic;
-- packet priority / priority present flag
rtu_rq_prio_o : out std_logic_vector(c_wrsw_prio_width - 1 downto 0);
rtu_rq_prio_o : out std_logic_vector(3 - 1 downto 0);
rtu_rq_has_prio_o : out std_logic;
-- RTU idle input (indicates that the RTU is ready to serve another request)
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2011-02-07
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -50,9 +50,9 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common_components.all;
use work.endpoint_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.endpoint_pkg.all;
entity ep_rx_pcs_tbi is
generic (
......@@ -240,7 +240,7 @@ begin
-- synchronizer chains for Wishbone-accessible control signals
-------------------------------------------------------------------------------
U_sync_pcs_busy : sync_ffs
U_sync_pcs_busy : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -252,7 +252,7 @@ begin
ppulse_o => open);
U_sync_rx_reset : sync_ffs
U_sync_rx_reset : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -263,7 +263,7 @@ begin
npulse_o => open,
ppulse_o => open);
U_sync_an_rx_enable : sync_ffs
U_sync_an_rx_enable : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -274,7 +274,7 @@ begin
npulse_o => open,
ppulse_o => open);
U_sync_power_down : sync_ffs
U_sync_power_down : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -341,7 +341,7 @@ begin
cal_i => d_is_cal);
-- synchronizer chain for rx_synced signal, also serving as a loss-of-sync detector
U_sync_los : sync_ffs
U_sync_los : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -899,7 +899,7 @@ begin
an_rx_val_o <= lcr_cur_val;
U_sync_an_rx_ready : sync_ffs
U_sync_an_rx_ready : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -910,7 +910,7 @@ begin
npulse_o => open,
ppulse_o => open);
U_sync_an_idle_match : sync_ffs
U_sync_an_idle_match : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -921,7 +921,7 @@ begin
npulse_o => open,
ppulse_o => open);
U_ext_rmon_1 : extend_pulse
U_ext_rmon_1 : gc_extend_pulse
generic map (
g_width => 3)
port map (
......@@ -930,7 +930,7 @@ begin
pulse_i => rmon_invalid_code_p_int,
extended_o => rmon_invalid_code_p_o);
U_ext_rmon_2 : extend_pulse
U_ext_rmon_2 : gc_extend_pulse
generic map (
g_width => 3)
port map (
......
......@@ -7,7 +7,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2011-03-16
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -34,9 +34,8 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.global_defs.all;
use work.gencores_pkg.all;
use work.endpoint_pkg.all;
use work.common_components.all;
entity ep_timestamping_unit is
generic (
......@@ -68,7 +67,7 @@ entity ep_timestamping_unit is
-------------------------------------------------------------------------------
-- TX OOB frame ID (extracted from OOB fields from fabric interface by TX framer)
txoob_fid_i : in std_logic_vector(c_wrsw_oob_frame_id_size - 1 downto 0);
txoob_fid_i : in std_logic_vector(16 - 1 downto 0);
-- TX OOB strobe, denotes valid FID on txoob_fid_i.
txoob_stb_p_i : in std_logic;
......@@ -90,9 +89,9 @@ entity ep_timestamping_unit is
-- Port ID value
txtsu_port_id_o : out std_logic_vector(4 downto 0);
-- Frame ID value
txtsu_fid_o : out std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_fid_o : out std_logic_vector(16 -1 downto 0);
-- Encoded timestamps
txtsu_tsval_o : out std_logic_vector(c_wrsw_timestamp_size_r + c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_tsval_o : out std_logic_vector(28 + 4 - 1 downto 0);
-- TX timestamp valid: HI tells the TX timestamping unit that there is a valid
-- timestmap on txtsu_tsval_o, txtsu_fid_o and txtsu_port_id_o. Line remains HI
......@@ -186,7 +185,7 @@ begin -- syn
);
-- Sync chains for timestamp strobes: 4 combinations - (TX-RX) -> (rising/falling)
sync_ffs_tx_r : sync_ffs
sync_ffs_tx_r : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -197,7 +196,7 @@ begin -- syn
npulse_o => open,
ppulse_o => take_tx_synced_p);
sync_ffs_rx_r : sync_ffs
sync_ffs_rx_r : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -209,7 +208,7 @@ begin -- syn
ppulse_o => take_rx_synced_p);
sync_ffs_tx_f : sync_ffs
sync_ffs_tx_f : gc_sync_ffs
generic map (
g_sync_edge => "negative")
port map (
......@@ -220,7 +219,7 @@ begin -- syn
npulse_o => open,
ppulse_o => take_tx_synced_p_fedge);
sync_ffs_rx_f : sync_ffs
sync_ffs_rx_f : gc_sync_ffs
generic map (
g_sync_edge => "negative")
port map (
......@@ -281,7 +280,7 @@ begin -- syn
-- timestamping "done" signals sync chains (refclk/rbclk -> refclk2)
tx_done_gen : sync_ffs
tx_done_gen : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -292,7 +291,7 @@ begin -- syn
npulse_o => tx_ts_done,
ppulse_o => open);
rx_done_gen : sync_ffs
rx_done_gen : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2011-04-12
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -32,8 +32,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.global_defs.all;
use work.common_components.all;
use work.gencores_pkg.all;
use work.endpoint_pkg.all;
entity ep_tx_framer is
......@@ -66,7 +65,7 @@ entity ep_tx_framer is
-- RX control bus: indicates type of word currently present on rx_data_o:
-- SRC_MAC, DST_MAC, VID_PRIO, PAYLOAD, CRC, OOB, END_OF_FRAME
tx_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
tx_ctrl_i : in std_logic_vector(4 - 1 downto 0);
-- active HI: indicates the last byte of odd-sized frame. Byte is transferred
-- on MSB of tx_data_i.
......@@ -177,7 +176,7 @@ begin -- behavioral
crc_gen_reset <= '1' when rst_n_i = '0' else ((tx_sof_p1_i and (not tx_pause_mode)) or crc_gen_force_reset);
crc_gen_enable <= tx_data_t2f_valid and crc_gen_enable_mask;
U_tx_crc_generator : crc_gen
U_tx_crc_generator : gc_crc_gen
generic map (
g_polynomial => x"04C11DB7",
g_init_value => x"ffffffff",
......@@ -444,7 +443,7 @@ begin -- behavioral
if(tx_valid_i = '1') then
if(tx_ctrl_i = c_wrsw_ctrl_tx_oob) then
oob_fid_value_o <= tx_data_i (c_wrsw_oob_frame_id_size - 1 downto 0);
oob_fid_value_o <= tx_data_i (15 downto 0);
oob_fid_stb_o <= '1';
tx_data_t2f_valid <= '0';
crc_gen_enable_mask <= '0';
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT section
-- Created : 2009-06-16
-- Last update: 2011-02-01
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -57,9 +57,9 @@ use ieee.numeric_std.all;
library work;
use work.common_components.all;
use work.endpoint_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.endpoint_pkg.all;
entity ep_tx_pcs_tbi is
......@@ -202,7 +202,7 @@ begin
U_sync_pcs_busy_o : sync_ffs
U_sync_pcs_busy_o : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -213,7 +213,7 @@ begin
npulse_o => open,
ppulse_o => open);
U_sync_pcs_error_o : sync_ffs
U_sync_pcs_error_o : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -224,7 +224,7 @@ begin
npulse_o => open,
ppulse_o => pcs_error_p_o);
U_sync_tx_reset : sync_ffs
U_sync_tx_reset : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -235,7 +235,7 @@ begin
npulse_o => open,
ppulse_o => open);
U_sync_power_down : sync_ffs
U_sync_power_down : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......
......@@ -13,8 +13,8 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library wbgen2;
use wbgen2.wbgen2_pkg.all;
use work.wbgen2_pkg.all;
entity ep_wishbone_controller is
port (
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2011-05-07
-- Last update: 2011-05-11
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -35,11 +35,8 @@ use ieee.numeric_std.all;
library work;
use work.global_defs.all;
use work.common_components.all;
use work.gencores_pkg.all;
use work.endpoint_pkg.all;
use work.platform_specific.all;
entity wrsw_endpoint is
......@@ -124,7 +121,7 @@ entity wrsw_endpoint is
-- RX control bus: indicates type of word currently present on rx_data_o:
-- SRC_MAC, DST_MAC, VID_PRIO, PAYLOAD, CRC, OOB
rx_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
rx_ctrl_o : out std_logic_vector(4 - 1 downto 0);
-- RX byte enable signal: when active, only MSB of rx_data_o contains valid
-- data byte (the last byte of the frame). Used for handling odd-sized frames.
......@@ -167,7 +164,7 @@ entity wrsw_endpoint is
-- RX control bus: indicates type of word currently present on rx_data_o:
-- SRC_MAC, DST_MAC, VID_PRIO, PAYLOAD, CRC, OOB, END_OF_FRAME
tx_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
tx_ctrl_i : in std_logic_vector(4 - 1 downto 0);
-- active HI: indicates the last byte of odd-sized frame. Byte is transferred
-- on MSB of tx_data_i.
......@@ -208,10 +205,10 @@ entity wrsw_endpoint is
txtsu_port_id_o : out std_logic_vector(4 downto 0);
-- frame ID value
txtsu_frame_id_o : out std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_frame_id_o : out std_logic_vector(16 - 1 downto 0);
-- timestamp values: gathered on rising clock edge (the main timestamp)
txtsu_tsval_o : out std_logic_vector(c_wrsw_timestamp_size_r + c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_tsval_o : out std_logic_vector(28 + 4 - 1 downto 0);
-- HI indicates a valid timestamp/frame ID pair for the TXTSU
txtsu_valid_o : out std_logic;
......@@ -233,18 +230,18 @@ entity wrsw_endpoint is
rtu_rq_strobe_p1_o : out std_logic;
-- source and destination MAC addresses extracted from the packet header
rtu_rq_smac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
-- VLAN id (extracted from the header for TRUNK ports and assigned by the port
-- for ACCESS ports)
rtu_rq_vid_o : out std_logic_vector(c_wrsw_vid_width - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
-- HI means that packet has valid assigned a valid VID (low - packet is untagged)
rtu_rq_has_vid_o : out std_logic;
-- packet priority (either extracted from the header or assigned per port).
rtu_rq_prio_o : out std_logic_vector(c_wrsw_prio_width-1 downto 0);
rtu_rq_prio_o : out std_logic_vector(3 - 1 downto 0);
-- HI indicates that packet has assigned priority.
rtu_rq_has_prio_o : out std_logic;
......@@ -270,22 +267,20 @@ architecture syn of wrsw_endpoint is
component dmtd_phase_meas
generic (
g_deglitch_thr_lo : integer;
g_deglitch_thr_hi : integer;
g_deglitch_thr_glitch : integer;
g_counter_bits : integer);
g_deglitcher_threshold : integer;
g_counter_bits : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_a_i : in std_logic;
clk_b_i : in std_logic;
clk_dmtd_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
navg_i : in std_logic_vector(11 downto 0);
phase_meas_o : out std_logic_vector(31 downto 0);
phase_meas_p_o : out std_logic);
end component;
signal sv_zero : std_logic_vector(63 downto 0);
signal sv_one : std_logic_vector(63 downto 0);
......@@ -320,8 +315,8 @@ architecture syn of wrsw_endpoint is
signal txpcs_timestamp_stb_p : std_logic;
signal rxpcs_timestamp_stb_p : std_logic;
signal txts_timestamp_value : std_logic_vector(c_wrsw_timestamp_size_f + c_wrsw_timestamp_size_r - 1 downto 0);
signal rxts_timestamp_value : std_logic_vector(c_wrsw_timestamp_size_f + c_wrsw_timestamp_size_r - 1 downto 0);
signal txts_timestamp_value : std_logic_vector(28 + 4 - 1 downto 0);
signal rxts_timestamp_value : std_logic_vector(28 + 4 - 1 downto 0);
signal rxts_done_p : std_logic;
signal txts_done_p : std_logic;
......@@ -356,7 +351,7 @@ architecture syn of wrsw_endpoint is
-------------------------------------------------------------------------------
signal rbuf_data : std_logic_vector(15 downto 0);
signal rbuf_ctrl : std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
signal rbuf_ctrl : std_logic_vector(4-1 downto 0);
signal rbuf_sof_p : std_logic;
signal rbuf_eof_p : std_logic;
signal rbuf_error_p : std_logic;
......@@ -774,8 +769,8 @@ begin
U_EP_TSU : ep_timestamping_unit
generic map (
g_timestamp_bits_r => c_wrsw_timestamp_size_r,
g_timestamp_bits_f => c_wrsw_timestamp_size_f)
g_timestamp_bits_r => 28,
g_timestamp_bits_f => 4)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......@@ -810,12 +805,11 @@ begin
U_DMTD : dmtd_phase_meas
generic map (
g_deglitch_thr_lo => 150,
g_deglitch_thr_hi => 150,
g_deglitch_thr_glitch => 60,
g_counter_bits => 14)
g_counter_bits => 14,
g_deglitcher_threshold => 1000 )
port map (
clk_sys_i => clk_sys_i,
clk_a_i => tx_clk,
clk_b_i => rx_clk,
clk_dmtd_i => clk_dmtd_i,
......
files = ["pps_gen_wb.vhd",
"wrsw_pps_gen.vhd"];
\ No newline at end of file
This diff is collapsed.
This diff is collapsed.
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Switch PPS generator and RTC";
description = "Unit generating PPS signals and acting as a UTC real-time clock";
hdl_entity = "pps_gen_wb";
prefix = "ppsg";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Reset counter";
description = "write 1: resets the counter\
write 0: no effect";
prefix = "CNT_RST";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "Enable counter";
description = "1: PPS counter is enabled";
prefix = "CNT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Adjust offset";
description = "write 1: Starts adjusting PPS/UTC offsets by adding the values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers to the current PPS counter value. These registers need to be programmed prior to update.\
write 0: no effect\
read 0: adjustment operation is done\
read 1: adjustment operation is in progress";
prefix = "CNT_ADJ";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "Set time";
description = "write 1: Sets the UTC/PPS counter to values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers";
prefix = "CNT_SET";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "PPS Pulse width";
description = "Width of generated PPS pulses in 125 MHz refernce clock cycles";
prefix = "PWIDTH";
size = 28;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock= "refclk_i";
};
};
reg {
name = "Nanosecond counter register";
description = "Nanosecond part of current time, expressed as number of 125 MHz reference clock cycles";
prefix = "CNTR_NSEC";
field {
name = "Nanosecond counter";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (least-significant part)";
description = "Lower 32 bits of current UTC time";
prefix = "CNTR_UTCLO";
field {
name = "UTC Counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (most-significant part)";
description = "Highest 8 bits of current UTC time";
prefix = "CNTR_UTCHI";
field {
name = "UTC Counter";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "Nanosecond adjustment register";
description = "Adjustment value for nanosecond counter";
prefix = "ADJ_NSEC";
field {
name = "Nanosecond adjustment";
type = PASS_THROUGH;
size = 28;
};
};
reg {
name = "UTC Adjustment register (least-significant part)";
description = "Lower 32 bits of adjustment value for UTC";
prefix = "ADJ_UTCLO";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "UTC Adjustment register (most-significant part)";
description = "Highest 8 bits of adjustment value for UTC";
prefix = "ADJ_UTCHI";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 8;
};
};
reg {
name = "External sync control register";
prefix = "ESCR";
field {
name = "Sync to external PPS input";
description = "write 1: Waits until a pulse on external PPS input arrives and re-synchronizes the PPS counter to it\
write 0: no effect\
read 1: external synchronization done\
read 0: external synchronization in progress";
type = BIT;
prefix = "SYNC";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
};
};
SRCS_VHDL = gtp_bitslide.vhd \
gtp_phase_align.vhd \
wr_gtp_phy_spartan6.vhd \
whiterabbitgtp_wrapper.vhd \
whiterabbitgtp_wrapper_tile.vhd
WORK = work
#directories in which we should search for the VHDL/verilog source files
VPATH =
include ../../scripts/modules.mk
......@@ -48,7 +48,7 @@ library unisim;
use unisim.all;
library work;
use work.common_components.all;
use work.gencores_pkg.all;
entity wr_gtp_phy_spartan6 is
......@@ -547,7 +547,7 @@ begin -- rtl
ch0_rx_enable_output <= ch0_rx_synced and ch0_align_done;
ch1_rx_enable_output <= ch1_rx_synced and ch1_align_done;
U_sync_oen_ch0 : sync_ffs
U_sync_oen_ch0 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -558,7 +558,7 @@ begin -- rtl
npulse_o => open,
ppulse_o => open);
U_sync_oen_ch1 : sync_ffs
U_sync_oen_ch1 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......
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