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White Rabbit core collection
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White Rabbit core collection
Commits
35b77aba
Commit
35b77aba
authored
Apr 26, 2013
by
Wesley W. Terpstra
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altera: improve Makefile clean rule
parent
f9ff1af1
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4 changed files
with
2 additions
and
4 deletions
+2
-4
Makefile
syn/gsi_exploder/wr_core_demo/Makefile
+1
-1
exploder_top.qsf
syn/gsi_exploder/wr_core_demo/exploder_top.qsf
+0
-1
Makefile
syn/gsi_scu/wr_core_demo/Makefile
+1
-1
scu.qsf
syn/gsi_scu/wr_core_demo/scu.qsf
+0
-1
No files found.
syn/gsi_exploder/wr_core_demo/Makefile
View file @
35b77aba
...
...
@@ -10,7 +10,7 @@ all: $(TARGET).sof $(TARGET).jic $(TARGET).rpd
clean
:
rm
-rf
db incremental_db PLLJ_PLLSPE_INFO.txt
rm
-f
$(TARGET)
.
*
.rpt
$(TARGET)
.
*
.summary
$(TARGET)
.map
*
$(TARGET)
.fit.
*
$(TARGET)
.pin
$(TARGET)
.jdi
$(TARGET)
*
.qdf
$(TARGET)
.done
$(TARGET)
.qws
rm
-f
$(TARGET)
.
jam
$(TARGET)
.jic
$(TARGET)
.pof
$(TARGET)
.sof
$(TARGET)
.dep
rm
-f
$(TARGET)
.
rpd
$(TARGET)
.jic
$(TARGET)
.pof
$(TARGET)
.sof
$(TARGET)
.dep
%.sof
:
%.qsf
$(QUARTUS_BIN)
/quartus_map
$*
...
...
syn/gsi_exploder/wr_core_demo/exploder_top.qsf
View file @
35b77aba
...
...
@@ -433,7 +433,6 @@ set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/co
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
...
...
syn/gsi_scu/wr_core_demo/Makefile
View file @
35b77aba
...
...
@@ -10,7 +10,7 @@ all: $(TARGET).sof $(TARGET).jic $(TARGET).rpd
clean
:
rm
-rf
db incremental_db PLLJ_PLLSPE_INFO.txt
rm
-f
$(TARGET)
.
*
.rpt
$(TARGET)
.
*
.summary
$(TARGET)
.map
*
$(TARGET)
.fit.
*
$(TARGET)
.pin
$(TARGET)
.jdi
$(TARGET)
*
.qdf
$(TARGET)
.done
$(TARGET)
.qws
rm
-f
$(TARGET)
.
jam
$(TARGET)
.jic
$(TARGET)
.pof
$(TARGET)
.sof
$(TARGET)
.dep
rm
-f
$(TARGET)
.
rpd
$(TARGET)
.jic
$(TARGET)
.pof
$(TARGET)
.sof
$(TARGET)
.dep
%.sof
:
%.qsf
$(QUARTUS_BIN)
/quartus_map
$*
...
...
syn/gsi_scu/wr_core_demo/scu.qsf
View file @
35b77aba
...
...
@@ -832,7 +832,6 @@ set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/co
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
...
...
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