Add CUTE-WR-DP board support by Tsinghua University

35276bb9 · Vraliens · Grzegorz Daniluk · a1602aaf · 35276bb9 · 35276bb9
Commit 35276bb9 authored Aug 23, 2018 by Vraliens Committed by Grzegorz Daniluk Jan 21, 2019
15 changed files
--- a/board/cute/Manifest.py
+++ b/board/cute/Manifest.py
+files = [
+    "cute_reset_gen.vhd",
+    "wr_cute_pkg.vhd",
+    "xwrc_board_cute.vhd",
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/cute/cute_reset_gen.vhd
+++ b/board/cute/cute_reset_gen.vhd
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity cute_reset_gen is
+port (
+  clk_sys_i : in std_logic;
+  rst_button_n_a_i : in std_logic;
+  rst_n_o : out std_logic);
+end cute_reset_gen;
+
+architecture behavioral of cute_reset_gen is
+
+  signal powerup_cnt     : unsigned(7 downto 0) := x"00";
+  signal powerup_n       : std_logic            := '0';
+  signal button_synced_n : std_logic;
+  
+  component gc_sync_ffs is
+    generic(
+      g_sync_edge : string := "positive"
+      );
+    port(
+      clk_i    : in  std_logic;  -- clock from the destination clock domain
+      rst_n_i  : in  std_logic;           -- reset
+      data_i   : in  std_logic;           -- async input
+      synced_o : out std_logic;           -- synchronized output
+      npulse_o : out std_logic;  -- negative edge detect output (single-clock
+      -- pulse)
+      ppulse_o : out std_logic   -- positive edge detect output (single-clock
+     -- pulse)
+      );
+  end component;
+
+begin  -- behavioral
+  
+  U_Sync_Button : gc_sync_ffs port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => '1',
+    data_i   => rst_button_n_a_i,
+    synced_o => button_synced_n);
+
+  p_powerup_reset : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(powerup_cnt /= x"ff") then
+        powerup_cnt <= powerup_cnt + 1;
+        powerup_n   <= '0';
+      else
+        powerup_n <= '1';
+      end if;
+    end if;
+  end process;
+
+  rst_n_o <= powerup_n and button_synced_n;
+
+end behavioral;
--- a/board/cute/wr_cute_pkg.vhd
+++ b/board/cute/wr_cute_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for CUTE package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_cute_pkg.vhd
+-- Author(s)  : Hongming Li <lihm.thu@foxmail.com>
+-- Company    : Tsinghua Univ. (DEP)
+-- Created    : 2018-07-14
+-- Last update: 2018-07-14
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_board_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_cute_pkg is
+
+  component xwrc_board_cute is
+    generic (
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := false;
+      g_aux_clks                  : integer              := 0;
+      g_fabric_iface              : t_board_fabric_iface := plain;
+      g_streamers_op_mode         : t_streamers_op_mode  := TX_AND_RX;
+      g_tx_streamer_params        : t_tx_streamer_params := c_tx_streamer_params_defaut;
+      g_rx_streamer_params        : t_rx_streamer_params := c_rx_streamer_params_defaut;
+      g_aux_sdb                   : t_sdb_device         := c_wrc_periph3_sdb;
+      g_dpram_initf               : string               := "default_xilinx";
+      g_diag_id                   : integer              := 0;
+      g_diag_ver                  : integer              := 0;
+      g_diag_ro_size              : integer              := 0;
+      g_diag_rw_size              : integer              := 0;
+      -- cute special
+      g_sfp0_enable               : boolean:= true;
+      g_sfp1_enable               : boolean:= false;
+      g_multiboot_enable          : boolean:= false);
+    port (
+      rst_n_i               : in  std_logic;
+      clk_20m_i             : in  std_logic;
+      clk_dmtd_i            : in  std_logic;
+      clk_sys_i             : in  std_logic;
+      clk_ref_i             : in  std_logic;
+      clk_sfp0_i            : in  std_logic :='0';
+      clk_sfp1_i            : in  std_logic :='0';
+      clk_aux_i             : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      clk_10m_ext_i         : in  std_logic := '0';
+      pps_ext_i             : in  std_logic := '0';
+      dac_hpll_load_p1_o    : out std_logic;
+      dac_hpll_data_o       : out std_logic_vector(15 downto 0);
+      dac_dpll_load_p1_o    : out std_logic;
+      dac_dpll_data_o       : out std_logic_vector(15 downto 0);
+      sfp0_txp_o            : out std_logic;
+      sfp0_txn_o            : out std_logic;
+      sfp0_rxp_i            : in  std_logic;
+      sfp0_rxn_i            : in  std_logic;
+      sfp0_det_i            : in  std_logic;
+      sfp0_scl_i            : in  std_logic;
+      sfp0_scl_o            : out std_logic;
+      sfp0_sda_i            : in  std_logic;
+      sfp0_sda_o            : out std_logic;
+      sfp0_rate_select_o    : out std_logic;
+      sfp0_tx_fault_i       : in  std_logic;
+      sfp0_tx_disable_o     : out std_logic;
+      sfp0_los_i            : in  std_logic;
+      sfp0_refclk_sel_i     : in std_logic_vector(2 downto 0):="110"; 
+      sfp0_rx_rbclk_o       : out std_logic;
+      sfp1_txp_o            : out std_logic;
+      sfp1_txn_o            : out std_logic;
+      sfp1_rxp_i            : in  std_logic;
+      sfp1_rxn_i            : in  std_logic;
+      sfp1_det_i            : in  std_logic;
+      sfp1_scl_i            : in  std_logic;
+      sfp1_scl_o            : out std_logic;
+      sfp1_sda_i            : in  std_logic;
+      sfp1_sda_o            : out std_logic;
+      sfp1_rate_select_o    : out std_logic;
+      sfp1_tx_fault_i       : in  std_logic;
+      sfp1_tx_disable_o     : out std_logic;
+      sfp1_los_i            : in  std_logic;
+      sfp1_refclk_sel_i     : in std_logic_vector(2 downto 0):="110"; 
+      sfp1_rx_rbclk_o       : out std_logic;
+      eeprom_sda_i         : in  std_logic                                        := '1';
+      eeprom_sda_o         : out std_logic;
+      eeprom_scl_i         : in  std_logic                                        := '1';
+      eeprom_scl_o         : out std_logic;
+      onewire_i            : in  std_logic;
+      onewire_oen_o        : out std_logic;
+      uart_rxd_i           : in  std_logic;
+      uart_txd_o           : out std_logic;
+      flash_sclk_o         : out std_logic;
+      flash_ncs_o          : out std_logic;
+      flash_mosi_o         : out std_logic;
+      flash_miso_i         : in  std_logic:='1';
+      wb_slave_o           : out t_wishbone_slave_out;
+      wb_slave_i           : in  t_wishbone_slave_in                              := cc_dummy_slave_in;
+      aux_master_o         : out t_wishbone_master_out;
+      aux_master_i         : in  t_wishbone_master_in                             := cc_dummy_master_in;
+      wrf_src_o            : out t_wrf_source_out;
+      wrf_src_i            : in  t_wrf_source_in                                  := c_dummy_src_in;
+      wrf_snk_o            : out t_wrf_sink_out;
+      wrf_snk_i            : in  t_wrf_sink_in                                    := c_dummy_snk_in;
+      wb_eth_master_o      : out t_wishbone_master_out;
+      wb_eth_master_i      : in  t_wishbone_master_in                             := cc_dummy_master_in;
+      aux_diag_i           : in  t_generic_word_array(g_diag_ro_size-1 downto 0)  := (others => (others => '0'));
+      aux_diag_o           : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0)          := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+      timestamps_o         : out t_txtsu_timestamp;
+      timestamps_ack_i     : in  std_logic                                        := '1';
+      abscal_txts_o        : out std_logic;
+      abscal_rxts_o        : out std_logic;
+      fc_tx_pause_req_i    : in  std_logic                                        := '0';
+      fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0)                    := x"0000";
+      fc_tx_pause_ready_o  : out std_logic;
+      tm_link_up_o         : out std_logic;
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      led_act_o            : out std_logic;
+      led_link_o           : out std_logic;
+      btn1_i               : in  std_logic                                        := '1';
+      btn2_i               : in  std_logic                                        := '1';
+      pps_valid_o          : out std_logic;
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+      pps_csync_o          : out std_logic;
+      link_ok_o            : out std_logic);
+  end component xwrc_board_cute;
+
+constant c_xwb_tcpip_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+    addr_first  => x"0000000000000000",
+    addr_last   => x"00000000000000ff",
+    product     => (
+    vendor_id => x"0000000000001103",  -- thu
+    device_id => x"c0413599",
+    version   => x"00000001",
+    date      => x"20160424",
+    name      => "wr-tcp-ip-stack    ")));
+end wr_cute_pkg;
--- a/board/cute/xwrc_board_cute.vhd
+++ b/board/cute/xwrc_board_cute.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for CUTE
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_cute.vhd
+-- Author(s)  : Hongming Li <lihm.thu@foxmail.com>
+-- Company    : Tsinghua Univ. (DEP)
+-- Created    : 2018-07-14
+-- Last update: 2018-07-14
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level wrapper for WR PTP core including all the modules
+-- needed to operate the core on the CUTE board.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_cute_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity xwrc_board_cute is
+  generic(
+    -- set to 1 to speed up some initialization processes during simulation
+    g_simulation                : integer              := 0;
+    -- Select whether to include external ref clock input
+    g_with_external_clock_input : boolean              := false;
+    -- Number of aux clocks syntonized by WRPC to WR timebase
+    g_aux_clks                  : integer              := 0;
+    -- plain     = expose WRC fabric interface
+    -- streamers = attach WRC streamers to fabric interface
+    -- etherbone = attach Etherbone slave to fabric interface
+    g_fabric_iface              : t_board_fabric_iface := plain;
+    -- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
+    g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    g_aux_sdb                   : t_sdb_device         := c_wrc_periph3_sdb;
+    -- memory initialisation file for embedded CPU
+    g_dpram_initf               : string               := "default_xilinx";
+    -- identification (id and ver) of the layout of words in the generic diag interface
+    g_diag_id                   : integer              := 0;
+    g_diag_ver                  : integer              := 0;
+    -- size the generic diag interface
+    g_diag_ro_size              : integer              := 0;
+    g_diag_rw_size              : integer              := 0;
+    -- cute special
+    g_sfp0_enable               : boolean:= true;
+    g_sfp1_enable               : boolean:= false;
+    g_multiboot_enable          : boolean:= false
+    );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- Reset input (active low, can be async)
+    rst_n_i       : in  std_logic;
+    -- Clock input, used to derive the DDMTD clock
+    clk_20m_i     : in std_logic;
+    -- 62.5m dmtd clock, from pll drived by clk_20m_vcxo
+    clk_dmtd_i    : in std_logic;
+    -- 62.5m system clock, from pll drived by clk_125m_pllref
+    clk_sys_i     : in std_logic;    
+    -- 125m reference clock, from pll drived by clk_125m_pllref
+    clk_ref_i     : in std_logic;
+    -- Dedicated clock for the Xilinx GTP transceiver.
+    clk_sfp0_i    : in std_logic :='0';
+    clk_sfp1_i    : in std_logic :='0';
+    -- Aux clocks, which can be disciplined by the WR Core
+    clk_aux_i     : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
+    clk_10m_ext_i : in  std_logic := '0';
+    -- External PPS input (g_with_external_clock_input = TRUE)
+    pps_ext_i     : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- Shared SPI interface to DACs
+    ---------------------------------------------------------------------------
+    dac_hpll_load_p1_o : out std_logic;
+    dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+    dac_dpll_load_p1_o : out std_logic;
+    dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver and SFP management info
+    ---------------------------------------------------------------------------
+    sfp0_txp_o         : out std_logic;
+    sfp0_txn_o         : out std_logic;
+    sfp0_rxp_i         : in  std_logic;
+    sfp0_rxn_i         : in  std_logic;
+    sfp0_det_i         : in  std_logic := '1';
+    sfp0_sda_i         : in  std_logic;
+    sfp0_sda_o         : out std_logic;
+    sfp0_scl_i         : in  std_logic;
+    sfp0_scl_o         : out std_logic;
+    sfp0_rate_select_o : out std_logic;
+    sfp0_tx_fault_i    : in  std_logic := '0';
+    sfp0_tx_disable_o  : out std_logic;
+    sfp0_los_i         : in  std_logic := '0';
+    sfp0_refclk_sel_i  : in  std_logic_vector(2 downto 0);
+    sfp0_rx_rbclk_o    : out std_logic;
+
+    sfp1_txp_o         : out std_logic;
+    sfp1_txn_o         : out std_logic;
+    sfp1_rxp_i         : in  std_logic;
+    sfp1_rxn_i         : in  std_logic;
+    sfp1_det_i         : in  std_logic := '1';
+    sfp1_sda_i         : in  std_logic;
+    sfp1_sda_o         : out std_logic;
+    sfp1_scl_i         : in  std_logic;
+    sfp1_scl_o         : out std_logic;
+    sfp1_rate_select_o : out std_logic;
+    sfp1_tx_fault_i    : in  std_logic := '0';
+    sfp1_tx_disable_o  : out std_logic;
+    sfp1_los_i         : in  std_logic := '0';
+    sfp1_refclk_sel_i  : in  std_logic_vector(2 downto 0);
+    sfp1_rx_rbclk_o    : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- I2C EEPROM
+    ---------------------------------------------------------------------------
+    eeprom_sda_i : in  std_logic;
+    eeprom_sda_o : out std_logic;
+    eeprom_scl_i : in  std_logic;
+    eeprom_scl_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+    onewire_i     : in  std_logic;
+    onewire_oen_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- External WB interface
+    ---------------------------------------------------------------------------
+    wb_slave_o : out t_wishbone_slave_out;
+    wb_slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- WR fabric interface (when g_fabric_iface = "plainfbrc")
+    ---------------------------------------------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = "etherbone")
+    ---------------------------------------------------------------------------
+    wb_eth_master_o : out t_wishbone_master_out;
+    wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- Generic diagnostics interface (access from WRPC via SNMP or uart console
+    ---------------------------------------------------------------------------
+    aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Aux clocks control
+    ---------------------------------------------------------------------------
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    timestamps_o     : out t_txtsu_timestamp;
+    timestamps_ack_i : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o       : out std_logic;
+    abscal_rxts_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    tm_link_up_o    : out std_logic;
+    tm_time_valid_o : out std_logic;
+    tm_tai_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    -- 1PPS output
+    pps_valid_o: out std_logic;
+    pps_p_o    : out std_logic;
+    pps_led_o  : out std_logic;
+    pps_csync_o: out std_logic;
+    -- Link ok indication
+    link_ok_o  : out std_logic
+    );
+
+end entity xwrc_board_cute;
+
+
+architecture struct of xwrc_board_cute is
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+  -- OneWire
+  signal onewire_in : std_logic_vector(1 downto 0);
+  signal onewire_en : std_logic_vector(1 downto 0);
+
+  -- PHY
+  signal phy8_to_wrc   : t_phy_8bits_to_wrc;
+  signal phy8_from_wrc : t_phy_8bits_from_wrc;
+
+  -- External reference
+  signal ext_ref_mul         : std_logic;
+  signal ext_ref_mul_locked  : std_logic;
+  signal ext_ref_mul_stopped : std_logic;
+  signal ext_ref_rst         : std_logic;
+
+  signal sfp_det_i   : std_logic;
+  signal sfp_scl_i   : std_logic;
+  signal sfp_scl_o   : std_logic;
+  signal sfp_sda_i   : std_logic;
+  signal sfp_sda_o   : std_logic;
+ 
+  signal aux_master_out  :  t_wishbone_master_out;
+  signal aux_master_in   :  t_wishbone_master_in := cc_dummy_master_in;
+
+  signal multiboot_wb_out  : t_wishbone_master_out;
+  signal multiboot_wb_in   : t_wishbone_master_in;
+  signal multiboot_slave_out : t_wishbone_slave_out;
+  signal multiboot_slave_in  : t_wishbone_slave_in := cc_dummy_slave_in;
+
+begin  -- architecture struct
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core with optional fabric interface attached
+  -----------------------------------------------------------------------------
+
+  cmp_board_common : xwrc_board_common
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_board_name                => "CUTE",
+      g_flash_secsz_kb            => 64,         -- sector size for M25P32
+      g_flash_sdbfs_baddr         => 16#2e0000#, -- sdbfs after multiboot bitstream
+      g_phys_uart                 => TRUE,
+      g_virtual_uart              => TRUE,
+      g_aux_clks                  => g_aux_clks,
+      g_ep_rxbuf_size             => 1024,
+      g_tx_runt_padding           => TRUE,
+      g_dpram_initf               => g_dpram_initf,
+      g_dpram_size                => 131072/4,
+      g_interface_mode            => PIPELINED,
+      g_address_granularity       => BYTE,
+      g_aux_sdb                   => g_aux_sdb,
+      g_softpll_enable_debugger   => FALSE,
+      g_vuart_fifo_size           => 1024,
+      g_pcs_16bit                 => FALSE,
+      g_diag_id                   => g_diag_id,
+      g_diag_ver                  => g_diag_ver,
+      g_diag_ro_size              => g_diag_ro_size,
+      g_diag_rw_size              => g_diag_rw_size,
+      g_streamers_op_mode         => g_streamers_op_mode,
+      g_tx_streamer_params        => g_tx_streamer_params,
+      g_rx_streamer_params        => g_rx_streamer_params,
+      g_fabric_iface              => g_fabric_iface
+      )
+    port map (
+      clk_sys_i            => clk_sys_i,
+      clk_dmtd_i           => clk_dmtd_i,
+      clk_ref_i            => clk_ref_i,
+      clk_aux_i            => clk_aux_i,
+      clk_10m_ext_i        => clk_10m_ext_i,
+      clk_ext_mul_i        => ext_ref_mul,
+      clk_ext_mul_locked_i => ext_ref_mul_locked,
+      clk_ext_stopped_i    => ext_ref_mul_stopped,
+      clk_ext_rst_o        => ext_ref_rst,
+      pps_ext_i            => pps_ext_i,
+      rst_n_i              => rst_n_i,
+      dac_hpll_load_p1_o   => dac_hpll_load_p1_o,
+      dac_hpll_data_o      => dac_hpll_data_o,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1_o,
+      dac_dpll_data_o      => dac_dpll_data_o,
+      phy8_o               => phy8_from_wrc,
+      phy8_i               => phy8_to_wrc,
+      scl_o                => eeprom_scl_o,
+      scl_i                => eeprom_scl_i,
+      sda_o                => eeprom_sda_o,
+      sda_i                => eeprom_sda_i,
+      sfp_scl_o            => sfp_scl_o,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_sda_o            => sfp_sda_o,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_det_i            => sfp_det_i,
+      spi_sclk_o           => flash_sclk_o,
+      spi_ncs_o            => flash_ncs_o,
+      spi_mosi_o           => flash_mosi_o,
+      spi_miso_i           => flash_miso_i,
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      owr_pwren_o          => open,
+      owr_en_o             => onewire_en,
+      owr_i                => onewire_in,
+      wb_slave_i           => wb_slave_i,
+      wb_slave_o           => wb_slave_o,
+      aux_master_o         => aux_master_out,
+      aux_master_i         => aux_master_in,
+      wrf_src_o            => wrf_src_o,
+      wrf_src_i            => wrf_src_i,
+      wrf_snk_o            => wrf_snk_o,
+      wrf_snk_i            => wrf_snk_i,
+      wb_eth_master_o      => wb_eth_master_o,
+      wb_eth_master_i      => wb_eth_master_i,
+      aux_diag_i           => aux_diag_i,
+      aux_diag_o           => aux_diag_o,
+      tm_dac_value_o       => tm_dac_value_o,
+      tm_dac_wr_o          => tm_dac_wr_o,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      timestamps_o         => timestamps_o,
+      timestamps_ack_i     => timestamps_ack_i,
+      abscal_txts_o        => abscal_txts_o,
+      abscal_rxts_o        => abscal_rxts_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      tm_link_up_o         => tm_link_up_o,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
+      led_act_o            => led_act_o,
+      led_link_o           => led_link_o,
+      btn1_i               => btn1_i,
+      btn2_i               => btn2_i,
+      pps_valid_o          => pps_valid_o,
+      pps_p_o              => pps_p_o,
+      pps_csync_o          => pps_csync_o,
+      pps_led_o            => pps_led_o,
+      link_ok_o            => link_ok_o);
+
+  sfp0_rate_select_o <= '1';
+  sfp1_rate_select_o <= '1';
+
+  onewire_oen_o <= onewire_en(0);
+  onewire_in(0) <= onewire_i;
+  onewire_in(1) <= '1';
+
+U_WRPC_SFP0: if (g_sfp0_enable = true) generate
+
+  phy8_to_wrc.ref_clk        <= clk_ref_i;
+  phy8_to_wrc.sfp_tx_fault   <= sfp0_tx_fault_i;
+  phy8_to_wrc.sfp_los        <= sfp0_los_i;
+  sfp0_tx_disable_o          <= phy8_from_wrc.sfp_tx_disable;
+  sfp_det_i                  <= sfp0_det_i;
+  sfp_scl_i                  <= sfp0_scl_i;
+  sfp0_scl_o                 <= sfp_scl_o;
+  sfp_sda_i                  <= sfp0_sda_i;
+  sfp0_sda_o                 <= sfp_sda_o;
+  sfp0_rx_rbclk_o            <= phy8_to_wrc.rx_clk;
+
+  u_gtp0 : wr_gtp_phy_spartan6
+  generic map (
+    g_enable_ch0 => 0,
+    g_enable_ch1 => 1,
+    g_simulation => g_simulation)
+  port map (
+    gtp1_clk_i         => clk_sfp0_i,
+    ch1_ref_clk_i      => clk_ref_i,
+    ch1_tx_data_i      => phy8_from_wrc.tx_data,
+    ch1_tx_k_i         => phy8_from_wrc.tx_k(0),
+    ch1_tx_disparity_o => phy8_to_wrc.tx_disparity,
+    ch1_tx_enc_err_o   => phy8_to_wrc.tx_enc_err,
+    ch1_rx_rbclk_o     => phy8_to_wrc.rx_clk,
+    ch1_rx_data_o      => phy8_to_wrc.rx_data,
+    ch1_rx_k_o         => phy8_to_wrc.rx_k(0),
+    ch1_rx_enc_err_o   => phy8_to_wrc.rx_enc_err,
+    ch1_rx_bitslide_o  => phy8_to_wrc.rx_bitslide,
+    ch1_rst_i          => phy8_from_wrc.rst,
+    ch1_loopen_i       => phy8_from_wrc.loopen,
+    ch1_loopen_vec_i   => phy8_from_wrc.loopen_vec,
+    ch1_tx_prbs_sel_i  => phy8_from_wrc.tx_prbs_sel,
+    ch1_rdy_o          => phy8_to_wrc.rdy,
+    pad_txn1_o         => sfp0_txn_o,
+    pad_txp1_o         => sfp0_txp_o,
+    pad_rxn1_i         => sfp0_rxn_i,
+    pad_rxp1_i         => sfp0_rxp_i,
+
+    gtp0_clk_i         => '0',
+    ch0_ref_clk_i      => clk_ref_i,
+    ch0_tx_data_i      => x"00",
+    ch0_tx_k_i         => '0',
+    ch0_tx_disparity_o => open,
+    ch0_tx_enc_err_o   => open,
+    ch0_rx_data_o      => open,
+    ch0_rx_rbclk_o     => open,
+    ch0_rx_k_o         => open,
+    ch0_rx_enc_err_o   => open,
+    ch0_rx_bitslide_o  => open,
+    ch0_rst_i          => '1',
+    ch0_loopen_i       => '0',
+    ch0_loopen_vec_i   => (others=>'0'),
+    ch0_tx_prbs_sel_i  => (others=>'0'),
+    ch0_rdy_o          => open,
+
+    ch0_ref_sel_pll    => "100",
+    ch1_ref_sel_pll    => sfp0_refclk_sel_i,
+
+    pad_txn0_o         => open,
+    pad_txp0_o         => open,
+    pad_rxn0_i         => '0',
+    pad_rxp0_i         => '0'
+);
+
+end generate;
+
+U_WRPC_SFP1: if (g_sfp1_enable = true) generate
+  
+  phy8_to_wrc.ref_clk        <= clk_ref_i;
+  phy8_to_wrc.sfp_tx_fault   <= sfp1_tx_fault_i;
+  phy8_to_wrc.sfp_los        <= sfp1_los_i;
+  sfp0_tx_disable_o          <= phy8_from_wrc.sfp_tx_disable;
+
+  sfp_det_i                  <= sfp1_det_i;
+  sfp_scl_i                  <= sfp1_scl_i;
+  sfp1_scl_o                 <= sfp_scl_o;
+  sfp_sda_i                  <= sfp1_sda_i;
+  sfp1_sda_o                 <= sfp_sda_o;
+  sfp1_rx_rbclk_o            <= phy8_to_wrc.rx_clk;
+
+  u_gtp1 : wr_gtp_phy_spartan6
+  generic map (
+    g_enable_ch0 => 0,
+    g_enable_ch1 => 1,
+    g_simulation => g_simulation)
+  port map (
+    gtp1_clk_i         => clk_sfp1_i,
+    ch1_ref_clk_i      => clk_ref_i,
+    ch1_tx_data_i      => phy8_from_wrc.tx_data,
+    ch1_tx_k_i         => phy8_from_wrc.tx_k(0),
+    ch1_tx_disparity_o => phy8_to_wrc.tx_disparity,
+    ch1_tx_enc_err_o   => phy8_to_wrc.tx_enc_err,
+    ch1_rx_rbclk_o     => phy8_to_wrc.rx_clk,
+    ch1_rx_data_o      => phy8_to_wrc.rx_data,
+    ch1_rx_k_o         => phy8_to_wrc.rx_k(0),
+    ch1_rx_enc_err_o   => phy8_to_wrc.rx_enc_err,
+    ch1_rx_bitslide_o  => phy8_to_wrc.rx_bitslide,
+    ch1_rst_i          => phy8_from_wrc.rst,
+    ch1_loopen_i       => phy8_from_wrc.loopen,
+    ch1_loopen_vec_i   => phy8_from_wrc.loopen_vec,
+    ch1_tx_prbs_sel_i  => phy8_from_wrc.tx_prbs_sel,
+    ch1_rdy_o          => phy8_to_wrc.rdy,
+    pad_txn1_o         => sfp1_txn_o,
+    pad_txp1_o         => sfp1_txp_o,
+    pad_rxn1_i         => sfp1_rxn_i,
+    pad_rxp1_i         => sfp1_rxp_i,
+    gtp0_clk_i         => '0',
+    ch0_ref_clk_i      => clk_ref_i,
+    ch0_tx_data_i      => x"00",
+    ch0_tx_k_i         => '0',
+    ch0_tx_disparity_o => open,
+    ch0_tx_enc_err_o   => open,
+    ch0_rx_data_o      => open,
+    ch0_rx_rbclk_o     => open,
+    ch0_rx_k_o         => open,
+    ch0_rx_enc_err_o   => open,
+    ch0_rx_bitslide_o  => open,
+    ch0_rst_i          => '1',
+    ch0_loopen_i       => '0',
+    ch0_loopen_vec_i   => (others=>'0'),
+    ch0_tx_prbs_sel_i  => (others=>'0'),
+    ch0_rdy_o          => open,
+
+    ch0_ref_sel_pll    => "100",
+    ch1_ref_sel_pll    => sfp1_refclk_sel_i,
+
+    pad_txn0_o         => open,
+    pad_txp0_o         => open,
+    pad_rxn0_i         => '0',
+    pad_rxp0_i         => '0'
+  );
+
+end generate;
+  
+
+U_WRPC_MULTIBOOT: if (g_multiboot_enable = true) generate
+
+  multiboot_slave_in   <= aux_master_out;
+  aux_master_in        <= multiboot_slave_out;
+  aux_master_o         <= cc_dummy_master_out;
+
+  cmp_clock_crossing: xwb_clock_crossing
+    port map (
+      slave_clk_i     => clk_sys_i,
+      slave_rst_n_i   => rst_n_i,
+      slave_i         => multiboot_slave_in,
+      slave_o         => multiboot_slave_out,
+      master_clk_i    => clk_20m_i,
+      master_rst_n_i  => rst_n_i,
+      master_i        => multiboot_wb_in,
+      master_o        => multiboot_wb_out);
+
+  u_multiboot: xwb_xil_multiboot
+    port map (
+      clk_i   => clk_20m_i,
+      rst_n_i => rst_n_i,
+      wbs_i   => multiboot_wb_out,
+      wbs_o   => multiboot_wb_in,
+      spi_cs_n_o => open,
+      spi_sclk_o => open,
+      spi_mosi_o => open,
+      spi_miso_i => '0');
+
+end generate;
+
+U_WRPC_NO_MULTIBOOT: if (g_multiboot_enable = false) generate
+  aux_master_o   <= aux_master_out;
+  aux_master_in  <= aux_master_i;
+end generate;
+
+end architecture struct;
--- a/modules/wr_dacs/Manifest.py
+++ b/modules/wr_dacs/Manifest.py
 files = [
  "spec_serial_dac_arb.vhd",
-  "spec_serial_dac.vhd"
+  "spec_serial_dac.vhd",
+  "cute_serial_dac_arb.vhd",
+  "cute_serial_dac.vhd"
 ]
--- a/modules/wr_dacs/cute_serial_dac.vhd
+++ b/modules/wr_dacs/cute_serial_dac.vhd
+-------------------------------------------------------------------------------
+-- Title      : Serial DAC interface
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : serial_dac.vhd
+-- Author     : paas, slayer
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-25
+-- Last update: 2011-05-10
+-- Platform   : fpga-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible) 
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :1
+-- Date        Version  Author  Description
+-- 2009-01-24  1.0      paas    Created
+-- 2010-02-25  1.1      slayer  Modified for rev 1.1 switch
+-- 2012-10-15  2.0      pwb     Modified for AD5663R of CUTE-WR
+-------------------------------------------------------------------------------
+
+
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity cute_serial_dac is
+
+  generic (
+    g_num_data_bits  : integer := 16;
+    g_num_extra_bits : integer := 8
+    );
+
+  port (
+-- clock & reset
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+-- channel 1 value and value load strobe
+    cmd_i    : in std_logic_vector(g_num_extra_bits-1 downto 0);
+    value_i  : in std_logic_vector(g_num_data_bits-1 downto 0);
+    load_i   : in std_logic;
+
+-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
+    sclk_divsel_i : in std_logic_vector(2 downto 0);
+
+-- DAC I/F
+    dac_sclk_o   : out std_logic;
+    dac_sdata_o  : out std_logic;
+    dac_sync_n_o : out std_logic;   
+
+    xdone_o : out std_logic
+    );
+end cute_serial_dac;
+
+
+architecture syn of cute_serial_dac is
+
+  signal divider        : unsigned(11 downto 0);
+  signal dataSh         : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
+  signal bitCounter     : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
+  signal endSendingData : std_logic;
+  signal sendingData    : std_logic;
+  signal iDacClk        : std_logic;
+  signal iValidValue    : std_logic;
+
+  signal divider_muxed : std_logic;
+
+begin
+
+  -- Modified by Weibin
+  
+  select_divider : process (divider, sclk_divsel_i)
+  begin  -- process
+    case sclk_divsel_i is
+      when "000"  => divider_muxed <= divider(2);  -- sclk = clk_i/8
+      when "001"  => divider_muxed <= divider(3);  -- sclk = clk_i/16
+      when "010"  => divider_muxed <= divider(4);  -- sclk = clk_i/32
+      when "011"  => divider_muxed <= divider(5);  -- sclk = clk_i/64
+      when "100"  => divider_muxed <= divider(6);  -- sclk = clk_i/128
+      when "101"  => divider_muxed <= divider(7);  -- sclk = clk_i/256
+      when "110"  => divider_muxed <= divider(8);  -- sclk = clk_i/512
+      when "111"  => divider_muxed <= divider(9);  -- sclk = clk_i/1024
+      when others => null;
+    end case;
+  end process;
+
+
+  iValidValue <= load_i;
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        sendingData <= '0';
+      else
+        if iValidValue = '1' and sendingData = '0' then
+          sendingData <= '1';
+        elsif endSendingData = '1' then
+          sendingData <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if iValidValue = '1' then
+        divider <= (divider'high downto 1 => '0') & '1';
+      elsif sendingData = '1' then
+        if(divider_muxed = '1') then
+          divider <= (divider'high downto 1 => '0') & '1';
+        else
+          divider <= divider + 1;
+        end if;
+      elsif endSendingData = '1' then
+        divider <= (divider'high downto 1 => '0') & '1';
+      end if;
+    end if;
+  end process;
+
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        iDacClk <= '1';                 -- 0
+      else
+        if iValidValue = '1' then
+          iDacClk <= '1';               -- 0
+        elsif divider_muxed = '1' then
+          iDacClk <= not(iDacClk);
+        elsif endSendingData = '1' then
+          iDacClk <= '1';               -- 0
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        dataSh <= (others => '0');
+      else
+        if iValidValue = '1' and sendingData = '0' then
+          dataSh(g_num_data_bits-1 downto 0)     <= value_i;
+          dataSh(dataSh'left downto g_num_data_bits) <= cmd_i;
+        elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
+          dataSh(0)                    <= dataSh(dataSh'left);
+          dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if iValidValue = '1' and sendingData = '0' then
+        bitCounter(0)                        <= '1';
+        bitCounter(bitCounter'left downto 1) <= (others => '0');
+      elsif sendingData = '1' and to_integer(divider) = 1 and iDacClk = '1' then
+        bitCounter(0)                        <= '0';
+        bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
+      end if;
+    end if;
+  end process;
+
+  endSendingData <= bitCounter(bitCounter'left);
+
+  xdone_o <= not SendingData;
+
+  dac_sdata_o <= dataSh(dataSh'left);
+  
+  dac_sync_n_o <= not sendingData;
+
+  dac_sclk_o <= iDacClk;
+
+
+end syn;
--- a/modules/wr_dacs/cute_serial_dac_arb.vhd
+++ b/modules/wr_dacs/cute_serial_dac_arb.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity cute_serial_dac_arb is
+  generic(
+    g_invert_sclk    : boolean;
+    g_num_extra_bits : integer
+    );
+  port(
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    val1_i  : in std_logic_vector(15 downto 0);
+    load1_i : in std_logic;
+    val2_i  : in std_logic_vector(15 downto 0);
+    load2_i : in std_logic;
+
+    dac_ldac_n_o : out std_logic;
+    dac_clr_n_o  : out std_logic;
+    dac_sync_n_o : out std_logic;
+    dac_sclk_o   : out std_logic;
+    dac_din_o    : out std_logic);
+
+end cute_serial_dac_arb;
+
+architecture behavioral of cute_serial_dac_arb is
+
+  component cute_serial_dac
+    generic (
+      g_num_data_bits  : integer;
+      g_num_extra_bits : integer);
+    port (
+      clk_i         : in  std_logic;
+      rst_n_i       : in  std_logic;
+      value_i       : in  std_logic_vector(g_num_data_bits-1 downto 0);
+      cmd_i         : in  std_logic_vector(g_num_extra_bits-1 downto 0);
+      load_i        : in  std_logic;
+      sclk_divsel_i : in  std_logic_vector(2 downto 0);
+      dac_sclk_o    : out std_logic;
+      dac_sdata_o   : out std_logic;
+      dac_sync_n_o  : out std_logic;
+      xdone_o       : out std_logic);
+  end component;
+
+  signal d1, d2             : std_logic_vector(15 downto 0);
+  signal d1_ready, d2_ready : std_logic;
+
+
+  signal dac_data     : std_logic_vector(15 downto 0);
+  signal dac_load     : std_logic;
+  signal dac_cs_sel   : std_logic_vector(1 downto 0);
+  signal dac_done     : std_logic;
+  signal dac_sclk_int : std_logic;
+  signal dac_cmd      : std_logic_vector(g_num_extra_bits-1 downto 0);
+
+  signal init_cnt : unsigned(7 downto 0);
+
+  type t_state is (INIT, ENABLE_INT_REF, WAIT_DONE, LOAD_DAC, WAIT_DATA);
+
+  signal state : t_state;
+
+  signal trig0    : std_logic_vector(31 downto 0);
+  signal trig1    : std_logic_vector(31 downto 0);
+  signal trig2    : std_logic_vector(31 downto 0);
+  signal trig3    : std_logic_vector(31 downto 0);
+  signal CONTROL0 : std_logic_vector(35 downto 0);
+
+begin  -- behavioral
+
+  dac_clr_n_o <= '1';
+  dac_ldac_n_o <= '0';
+
+  U_DAC : cute_serial_dac
+    generic map (
+      g_num_data_bits  => 16,
+      g_num_extra_bits => g_num_extra_bits)
+    port map (
+      clk_i         => clk_i,
+      rst_n_i       => rst_n_i,
+      value_i       => dac_data,   
+      cmd_i         => dac_cmd,
+      load_i        => dac_load,
+      sclk_divsel_i => "001",
+      dac_sclk_o    => dac_sclk_int,
+      dac_sdata_o   => dac_din_o,
+      dac_sync_n_o  => dac_sync_n_o,
+      xdone_o       => dac_done);
+
+
+  p_drive_sclk: process(dac_sclk_int)
+    begin
+      if(g_invert_sclk) then
+        dac_sclk_o <= not dac_sclk_int;
+       else
+        dac_sclk_o <= dac_sclk_int;
+       end if;
+      end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        d1         <= (others => '0');
+        d1_ready   <= '0';
+        d2         <= (others => '0');
+        d2_ready   <= '0';
+        dac_load   <= '0';
+        init_cnt   <= (others => '0');
+        state      <= INIT;
+      else
+
+        if(load1_i = '1' or load2_i = '1') then
+          
+          if(load1_i = '1') then
+            d1_ready <= '1';
+            d1       <= val1_i;
+          end if;
+
+          if(load2_i = '1') then
+            d2_ready <= '1';
+            d2       <= val2_i;
+          end if;
+        else
+          case state is
+            when INIT => 
+              if init_cnt(6) = '1' then
+                state <= ENABLE_INT_REF;
+              else
+                init_cnt <= init_cnt +1;
+              end if;
+
+            when ENABLE_INT_REF =>
+              dac_cmd  <= "00111000";
+              dac_data <= (dac_data'high downto 1 => '0') & '0';  -- internal reference setup
+              dac_load <= '1';
+              state <= LOAD_DAC;
+              
+            when WAIT_DATA =>
+              if(d1_ready = '1') then
+                dac_data   <= d1;
+                dac_cmd    <= "00011001"; -- write and update DAC B
+                dac_load   <= '1';
+                d1_ready   <= '0';
+                state      <= LOAD_DAC;
+              elsif(d2_ready = '1') then
+                dac_data   <= d2;
+                dac_cmd    <= "00011000"; -- write and update DAC A
+                dac_load   <= '1';
+                d2_ready   <= '0';
+                state      <= LOAD_DAC;
+              end if;
+
+            when LOAD_DAC=>
+              dac_load <= '0';
+              state    <= WAIT_DONE;
+
+            when WAIT_DONE =>
+              if(dac_done = '1') then
+                state <= WAIT_DATA;
+              end if;
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  
+  
+end behavioral;
--- a/syn/cute_ref_design/Makefile
+++ b/syn/cute_ref_design/Makefile
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := cute_wr_ref.xise
+ISE_CRAP := *.b cute_wr_ref_top_summary.html *.tcl cute_wr_ref_top.bld cute_wr_ref_top.cmd_log *.drc cute_wr_ref_top.lso *.ncd cute_wr_ref_top.ngc cute_wr_ref_top.ngd cute_wr_ref_top.ngr cute_wr_ref_top.pad cute_wr_ref_top.par cute_wr_ref_top.pcf cute_wr_ref_top.prj cute_wr_ref_top.ptwx cute_wr_ref_top.stx cute_wr_ref_top.syr cute_wr_ref_top.twr cute_wr_ref_top.twx cute_wr_ref_top.gise $(PROJECT).gise cute_wr_ref_top.bgn cute_wr_ref_top.unroutes cute_wr_ref_top.ut cute_wr_ref_top.xpi cute_wr_ref_top.xst cute_wr_ref_top_bitgen.xwbt cute_wr_ref_top_envsettings.html cute_wr_ref_top_guide.ncd cute_wr_ref_top_map.map cute_wr_ref_top_map.mrp cute_wr_ref_top_map.ncd cute_wr_ref_top_map.ngm cute_wr_ref_top_map.xrpt cute_wr_ref_top_ngdbuild.xrpt cute_wr_ref_top_pad.csv cute_wr_ref_top_pad.txt cute_wr_ref_top_par.xrpt cute_wr_ref_top_summary.xml cute_wr_ref_top_usage.xml cute_wr_ref_top_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
+
+generate_tcl:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Synthesize - XST}" >> run.tcl
+		echo "process run {Translate}" >> run.tcl
+		echo "process run {Map}" >> run.tcl
+		echo "process run {Place & Route}" >> run.tcl
+		echo "process run {Generate Programming File}" >> run.tcl
+
+synthesis:
+		/home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
+
+check_tool:
+		
+
+syn_post_cmd:
+		
+
+syn_pre_cmd:
+		
+
+#target for cleaning all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
+.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
+
+USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
+SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
+ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
+R_NAME:=greg/cute_wr_ref
+PORT:=22
+
+__test_for_remote_synthesis_variables:
+ifeq (x$(USER),x)
+	@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
+endif
+ifeq (x$(SERVER),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
+endif
+ifeq (x$(ISE_PATH),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
+endif
+
+CWD := $(shell pwd)
+
+FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
+../../modules/wr_si57x_interface/xwr_si57x_interface.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd \
+../../modules/wr_endpoint/ep_sync_detect.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
+../../modules/fabric/xwrf_loopback/wrf_loopback.vhd \
+../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
+../../modules/wr_endpoint/ep_wishbone_controller.vhd \
+../../modules/wr_endpoint/endpoint_pkg.vhd \
+../../modules/wr_tbi_phy/enc_8b10b.vhd \
+../../modules/wrc_core/wrc_syscon_pkg.vhd \
+../../modules/wr_eca/eca_tlu_fsm.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
+../../platform/xilinx/chipscope/chipscope_icon.ngc \
+../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
+../../modules/wr_eca/eca_free.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
+../../modules/wr_endpoint/ep_rtu_header_extract.vhd \
+../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
+../../modules/wr_endpoint/ep_tx_path.vhd \
+../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
+../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
+../../modules/wrc_core/wrc_periph.vhd \
+../../modules/wr_eca/eca_pkg.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
+../../board/cute/wr_cute_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
+../../modules/wr_endpoint/ep_rx_oob_insert.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
+../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
+../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
+../../modules/wr_eca/eca_msi.vhd \
+../../modules/wrc_core/wr_core.vhd \
+../../ip_cores/general-cores/modules/common/gc_reset.vhd \
+../../modules/timing/multi_dmtd_with_deglitcher.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
+../../modules/wr_mini_nic/xwr_mini_nic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
+../../modules/wr_endpoint/ep_tx_header_processor.vhd \
+../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
+../../modules/wr_eca/eca_channel.vhd \
+../../modules/wr_eca/wr_eca.vhd \
+run.tcl \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
+../../modules/wr_eca/eca_offset.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
+../../modules/wr_endpoint/ep_crc32_pkg.vhd \
+../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
+../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
+../../modules/wr_eca/eca_wb_event.vhd \
+../../modules/wr_tlu/tlu_fsm.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd \
+../../modules/fabric/xwrf_loopback/lbk_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
+../../modules/wr_dacs/cute_serial_dac_arb.vhd \
+../../modules/wr_streamers/xrx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
+../../modules/wr_eca/eca_auto.vhd \
+../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
+../../modules/wr_endpoint/ep_rx_crc_size_check.vhd \
+../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
+../../modules/wr_tlu/tlu_pkg.vhd \
+../../modules/wr_eca/eca_ac_wbm_auto.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
+../../modules/wr_softpll_ng/xwr_softpll_ng.vhd \
+../../board/cute/cute_reset_gen.vhd \
+../../board/cute/xwrc_board_cute.vhd \
+../../modules/wr_eca/eca_tlu.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
+../../modules/wr_mini_nic/minic_wb_slave.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
+../../platform/xilinx/wr_xilinx_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
+../../modules/fabric/wr_fabric_pkg.vhd \
+../../modules/wr_eca/eca_sdp.vhd \
+../../modules/wr_eca/eca_scan.vhd \
+../../modules/wr_streamers/xrtx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
+../../modules/wr_endpoint/ep_rx_path.vhd \
+../../modules/wr_streamers/dropping_buffer.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
+../../modules/fabric/xwrf_reg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
+../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
+../../modules/timing/dmtd_phase_meas.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
+../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
+../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
+../../modules/wr_eca/eca_scubus_channel.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
+../../modules/timing/pulse_stamper.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
+../../modules/wr_streamers/streamers_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
+../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \
+../../modules/wr_streamers/rx_streamer.vhd \
+../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
+../../modules/timing/dmtd_with_deglitcher.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
+../../platform/xilinx/xwrc_platform_xilinx.vhd \
+../../modules/wr_endpoint/ep_timestamping_unit.vhd \
+../../modules/fabric/xwb_fabric_sink.vhd \
+../../modules/wrc_core/wrc_diags_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
+../../modules/wr_si57x_interface/si570_if_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
+../../modules/wr_endpoint/ep_rx_wb_master.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd \
+../../modules/wrc_core/wrcore_pkg.vhd \
+../../modules/wr_endpoint/ep_sync_detect_16bit.vhd \
+../../modules/wr_eca/eca_adder.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
+../../modules/fabric/xwrf_mux.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
+../../modules/wrc_core/xwrc_diags_wb.vhd \
+../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
+../../modules/wr_tlu/tlu.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
+../../modules/wr_eca/eca_piso_fifo.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
+../../modules/wrc_core/wrc_syscon_wb.vhd \
+../../modules/wrc_core/xwr_core.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
+../../top/cute_ref_design/cute_wr_ref_top.ucf \
+../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
+../../modules/wr_eca/eca_rmw.vhd \
+../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme64x_core.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
+../../platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
+../../modules/wr_endpoint/ep_tx_vlan_unit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
+../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
+../../modules/wr_dacs/cute_serial_dac.vhd \
+../../modules/wrc_core/wrc_diags_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
+../../modules/wr_pps_gen/xwr_pps_gen.vhd \
+../../board/common/xwrc_board_common.vhd \
+../../ip_cores/gn4124-core/hdl/cute/ip_cores/l2p_fifo.ngc \
+../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
+../../modules/fabric/xwb_fabric_source.vhd \
+../../modules/wr_eca/eca_tlu_auto.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
+../../modules/wr_eca/eca_tlu_auto_pkg.vhd \
+../../modules/wr_tbi_phy/wr_tbi_phy.vhd \
+../../platform/xilinx/chipscope/chipscope_ila.ngc \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
+../../modules/wr_streamers/xwr_streamers.vhd \
+../../modules/wr_softpll_ng/spll_wb_slave.vhd \
+../../modules/timing/hpll_period_detect.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
+../../modules/wr_tbi_phy/disparity_gen_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
+../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
+../../modules/wr_pps_gen/pps_gen_wb.vhd \
+../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
+../../modules/wr_streamers/xtx_streamers_stats.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
+../../modules/wr_endpoint/xwr_endpoint.vhd \
+../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd \
+../../modules/wr_streamers/streamers_priv_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
+../../modules/wr_endpoint/ep_registers_pkg.vhd \
+../../modules/wr_endpoint/ep_autonegotiation.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
+../../modules/wr_endpoint/ep_tx_packet_injection.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
+../../modules/wr_endpoint/endpoint_private_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
+../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
+../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
+../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
+../../modules/wr_endpoint/ep_tx_crc_inserter.vhd \
+../../modules/wr_eca/eca.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
+../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
+../../board/common/wr_board_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
+../../modules/wr_endpoint/ep_rx_early_address_match.vhd \
+../../modules/wr_si57x_interface/wr_si57x_interface.vhd \
+../../modules/wr_softpll_ng/spll_aligner.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_funct_match.vhd \
+cute_wr_ref.xise \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
+../../modules/wr_endpoint/wr_endpoint.vhd \
+../../modules/wr_streamers/escape_detector.vhd \
+../../modules/wr_softpll_ng/spll_period_detect.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
+../../modules/wr_endpoint/ep_ts_counter.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
+../../modules/wr_eca/eca_ac_wbm.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
+../../modules/wr_eca/eca_data.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
+../../modules/wr_eca/eca_queue.vhd \
+../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
+../../modules/wr_eca/eca_auto_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
+../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
+../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
+../../modules/wr_endpoint/ep_rx_buffer.vhd \
+../../modules/wr_mini_nic/minic_packet_buffer.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
+../../modules/wr_eca/eca_internals_pkg.vhd \
+../../modules/wr_streamers/xtx_streamer.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
+../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
+../../modules/wr_mini_nic/wr_mini_nic.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
+../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
+../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
+../../modules/timing/pulse_gen.vhd \
+../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
+../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
+../../modules/wr_softpll_ng/wr_softpll_ng.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
+../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
+../../board/cute/wrc_board_cute.vhd \
+../../modules/wr_streamers/wr_streamers_wb.vhd \
+../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_line.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+../../modules/wr_eca/eca_tag_channel.vhd \
+../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
+../../modules/wr_eca/eca_tdp.vhd \
+../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
+../../modules/wr_eca/eca_search.vhd \
+../../modules/wr_eca/eca_queue_auto_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_cr_csr_space.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
+../../modules/wr_eca/eca_queue_auto.vhd \
+../../modules/wr_streamers/tx_streamer.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
+../../top/cute_ref_design/cute_core_ref_top.vhd \
+../../top/cute_ref_design/cute_wr_ref_top.vhd \
+../../modules/wr_eca/eca_wr_time.vhd \
+../../modules/wr_streamers/xrx_streamer.vhd \
+../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
+../../modules/wr_streamers/escape_inserter.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
+../../modules/wr_endpoint/ep_leds_controller.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
+../../modules/wr_eca/eca_walker.vhd \
+../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
+../../modules/wr_softpll_ng/softpll_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
+../../modules/wr_endpoint/ep_packet_filter.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
+
+#target for running synthesis in the remote location
+remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
+__send_back: __do_synthesis
+__do_synthesis: __send
+__send: __test_for_remote_synthesis_variables
+
+__send:
+		ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
+		rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
+
+__do_synthesis:
+ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
+		ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
+else
+		ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
+endif
+
+
+sync: 
+		cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
+
+#target for removing stuff from the remote location
+cleanremote:
+		ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
+
--- a/syn/cute_ref_design/Manifest.py
+++ b/syn/cute_ref_design/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "csg324"
+
+syn_top = "cute_wr_ref_top"
+syn_project = "cute_wr_ref.xise"
+
+syn_tool = "ise"
+
+modules = { "local" : "../../top/cute_ref_design/"}
--- a/syn/cute_ref_design/cute_wr_ref.xise
+++ b/syn/cute_ref_design/cute_wr_ref.xise
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
+  </autoManagedFiles>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|cute_wr_ref_top|rtl" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/cute_ref_design/cute_wr_ref_top.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cute_wr_ref_top" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="cute_wr_ref_top" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Outputs Only" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="cute_wr_ref_top_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="cute_wr_ref_top_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="cute_wr_ref_top_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="cute_wr_ref_top_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="cute_wr_ref" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-02-20T14:40:16" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6841520F5DB4380D7FA352D3187A85B6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <libraries/>
+
+  <files>
+    <file xil_pn:name="../../platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../top/cute_ref_design/cute_wr_ref_top.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+    </file>
+    <file xil_pn:name="../../modules/fabric/xwrf_loopback/wrf_loopback.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
+    <file xil_pn:name="../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_free.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+    </file>
+    <file xil_pn:name="../../modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../board/cute/wr_cute_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_msi.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/fabric/xwrf_loopback/lbk_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_dacs/cute_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_streamers/xrx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_auto.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
+    </file>
+    <file xil_pn:name="../../modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_streamers/wr_streamers_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_tag_channel.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_queue_auto_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_cr_csr_space.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_queue_auto.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_streamers/tx_streamer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../top/cute_ref_design/cute_wr_ref_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_streamers/escape_inserter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
+    </file>
+    <file xil_pn:name="../../board/cute/cute_reset_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="332"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
+    </file>
+    <file xil_pn:name="../../top/cute_ref_design/cute_core_ref_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="336"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
+    </file>
+  </files>
+
+  <bindings/>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+</project>
--- a/top/cute_ref_design/Manifest.py
+++ b/top/cute_ref_design/Manifest.py
+fetchto = "../../ip_cores"
+
+files = [
+    "cute_core_ref_top.vhd",
+    "cute_wr_ref_top.vhd",
+    "cute_wr_ref_top.ucf",
+]
+
+modules = {
+    "local" : [
+        "../../",
+        "../../board/cute",
+    ],
+    "git" : [
+        "git://ohwr.org/hdl-core-lib/general-cores.git",
+        "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+    ],
+}
--- a/top/cute_ref_design/cute_core_ref_top.vhd
+++ b/top/cute_ref_design/cute_core_ref_top.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_cute_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.endpoint_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity cute_core_ref_top is
+  generic
+    (
+      -- set to 1 to speed up some initialization processes during simulation
+      g_simulation                : integer              := 0;
+      g_dpram_initf               : string :=   "../../bin/wrpc/wrc_phy8.bram";
+      g_sfp0_enable               : boolean:= true;
+      g_sfp1_enable               : boolean:= false;
+      g_aux_sdb                   : t_sdb_device  := c_xwb_tcpip_sdb;
+      g_multiboot_enable          : boolean:= false
+     );
+  port
+    (
+      ---------------------------------------------------------------------------
+      -- Clocks/resets
+      ---------------------------------------------------------------------------
+      -- Reset input (active low, can be async)
+      rst_n_i       : in  std_logic;
+      -- Clock input, used to derive the DDMTD clock
+      clk_20m_i     : in std_logic;
+      -- 62.5m dmtd clock, from pll drived by clk_20m_vcxo
+      clk_dmtd_i    : in std_logic;
+      -- 62.5m system clock, from pll drived by clk_125m_pllref
+      clk_sys_i     : in std_logic;    
+      -- 125m reference clock, from pll drived by clk_125m_pllref
+      clk_ref_i     : in std_logic;
+      -- Dedicated clock for the Xilinx GTP transceiver.
+      clk_sfp0_i    : in std_logic :='0';
+      clk_sfp1_i    : in std_logic :='0';
+      ---------------------------------------------------------------------------
+      -- Shared SPI interface to DACs
+      ---------------------------------------------------------------------------
+      dac_hpll_load_p1_o : out std_logic;
+      dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+      dac_dpll_load_p1_o : out std_logic;
+      dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+      ---------------------------------------------------------------------------
+      -- I2C EEPROM
+      ---------------------------------------------------------------------------
+      eeprom_scl_i : in  std_logic;
+      eeprom_scl_o : out std_logic;
+      eeprom_sda_i : in  std_logic;
+      eeprom_sda_o : out std_logic;
+
+      ---------------------------------------------------------------------------
+      -- Flash memory SPI interface
+      ---------------------------------------------------------------------------
+      flash_sclk_o : out std_logic;
+      flash_ncs_o  : out std_logic;
+      flash_mosi_o : out std_logic;
+      flash_miso_i : in  std_logic:='1';
+
+      ---------------------------------------------------------------------------
+      -- Onewire interface, Temp Sensor DS18B20
+      ---------------------------------------------------------------------------
+      onewire_i     : in  std_logic;
+      onewire_oen_o : out std_logic;
+
+      ---------------------------------------------------------------------------
+      -- UART
+      ---------------------------------------------------------------------------
+      uart_rxd_i : in  std_logic:='0';
+      uart_txd_o : out std_logic;
+
+      ---------------------------------------------------------------------------
+      -- SFP I/O for transceiver and SFP management info
+      ---------------------------------------------------------------------------
+      sfp0_txp_o        : out std_logic;
+      sfp0_txn_o        : out std_logic;
+      sfp0_rxp_i        : in  std_logic:='0';
+      sfp0_rxn_i        : in  std_logic:='0';
+      sfp0_det_i        : in  std_logic:='0';  -- sfp detect
+      sfp0_scl_i        : in  std_logic:='0';  -- scl
+      sfp0_scl_o        : out std_logic;  -- scl
+      sfp0_sda_i        : in  std_logic:='0';  -- sda
+      sfp0_sda_o        : out std_logic;  -- sda
+      sfp0_rate_select_o: out std_logic;
+      sfp0_tx_fault_i   : in  std_logic:='0';
+      sfp0_tx_disable_o : out std_logic;
+      sfp0_los_i        : in  std_logic:='0';
+      sfp0_refclk_sel_i : in std_logic_vector(2 downto 0);
+      sfp0_rx_rbclk_o   : out std_logic;
+      sfp1_txp_o        : out std_logic;
+      sfp1_txn_o        : out std_logic;
+      sfp1_rxp_i        : in  std_logic:='0';
+      sfp1_rxn_i        : in  std_logic:='0';
+      sfp1_det_i        : in  std_logic:='0';
+      sfp1_scl_i        : in  std_logic:='0';
+      sfp1_scl_o        : out std_logic:='0';
+      sfp1_sda_i        : in  std_logic:='0';
+      sfp1_sda_o        : out std_logic:='0';
+      sfp1_rate_select_o: out std_logic;
+      sfp1_tx_fault_i   : in  std_logic:='0';
+      sfp1_tx_disable_o : out std_logic;
+      sfp1_los_i        : in  std_logic:='0';
+      sfp1_refclk_sel_i : in std_logic_vector(2 downto 0);
+      sfp1_rx_rbclk_o   : out std_logic;
+      
+      ---------------------------------------------------------------------------
+      -- External WB interface
+      ---------------------------------------------------------------------------
+      wb_slave_o   : out t_wishbone_slave_out;
+      wb_slave_i   : in  t_wishbone_slave_in := cc_dummy_slave_in;
+
+      aux_master_o : out t_wishbone_master_out;
+      aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+      
+      ---------------------------------------------------------------------------
+      -- WR fabric interface (when g_fabric_iface = "plainfbrc")
+      ---------------------------------------------------------------------------
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+      ---------------------------------------------------------------------------
+      -- Etherbone WB master interface (when g_fabric_iface = "etherbone")
+      ---------------------------------------------------------------------------
+      wb_eth_master_o : out t_wishbone_master_out;
+      wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+      ---------------------------------------------------------------------------
+      -- Timecode I/F
+      ---------------------------------------------------------------------------
+      tm_link_up_o    : out std_logic;
+      tm_time_valid_o : out std_logic;
+      tm_tai_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+      ---------------------------------------------------------------------------
+      -- Buttons, LEDs and PPS output
+      ---------------------------------------------------------------------------
+      led_act_o      : out std_logic;
+      led_link_o     : out std_logic;
+      btn1_i         : in  std_logic := '1';
+      btn2_i         : in  std_logic := '1';
+      -- 1PPS output
+      pps_valid_o    : out std_logic;
+      pps_p_o        : out std_logic;
+      pps_led_o      : out std_logic;
+      pps_csync_o    : out std_logic;
+      -- Link ok indication
+      link_ok_o      : out std_logic
+      );
+end cute_core_ref_top;
+
+architecture rtl of cute_core_ref_top is
+
+begin
+  
+  cmp_xwrc_board_cute : xwrc_board_cute
+  generic map (
+    g_simulation                => g_simulation,
+    g_with_external_clock_input => false,
+    g_dpram_initf               => g_dpram_initf,
+    g_fabric_iface              => PLAIN,
+    g_aux_sdb                   => g_aux_sdb,
+    g_sfp0_enable               => g_sfp0_enable,
+    g_sfp1_enable               => g_sfp1_enable,
+    g_multiboot_enable          => g_multiboot_enable)
+  port map (
+    rst_n_i                => rst_n_i,          
+    clk_20m_i              => clk_20m_i,            
+    clk_dmtd_i             => clk_dmtd_i,             
+    clk_sys_i              => clk_sys_i,            
+    clk_ref_i              => clk_ref_i,            
+    clk_sfp0_i             => clk_sfp0_i,             
+    clk_sfp1_i             => clk_sfp1_i,             
+    dac_hpll_load_p1_o     => dac_hpll_load_p1_o,
+    dac_hpll_data_o        => dac_hpll_data_o,
+    dac_dpll_load_p1_o     => dac_dpll_load_p1_o,
+    dac_dpll_data_o        => dac_dpll_data_o,
+    sfp0_txp_o             => sfp0_txp_o,
+    sfp0_txn_o             => sfp0_txn_o,
+    sfp0_rxp_i             => sfp0_rxp_i,
+    sfp0_rxn_i             => sfp0_rxn_i,
+    sfp0_det_i             => sfp0_det_i,
+    sfp0_scl_i             => sfp0_scl_i,
+    sfp0_scl_o             => sfp0_scl_o,
+    sfp0_sda_i             => sfp0_sda_i,
+    sfp0_sda_o             => sfp0_sda_o,
+    sfp0_rate_select_o     => sfp0_rate_select_o,
+    sfp0_tx_fault_i        => sfp0_tx_fault_i,
+    sfp0_tx_disable_o      => sfp0_tx_disable_o,
+    sfp0_los_i             => sfp0_los_i,
+    sfp0_refclk_sel_i      => sfp0_refclk_sel_i,
+    sfp0_rx_rbclk_o        => sfp0_rx_rbclk_o,
+    sfp1_txp_o             => sfp1_txp_o,
+    sfp1_txn_o             => sfp1_txn_o,
+    sfp1_rxp_i             => sfp1_rxp_i,
+    sfp1_rxn_i             => sfp1_rxn_i,
+    sfp1_det_i             => sfp1_det_i,
+    sfp1_scl_i             => sfp1_scl_i,
+    sfp1_scl_o             => sfp1_scl_o,
+    sfp1_sda_i             => sfp1_sda_i,
+    sfp1_sda_o             => sfp1_sda_o,
+    sfp1_rate_select_o     => sfp1_rate_select_o,
+    sfp1_tx_fault_i        => sfp1_tx_fault_i,
+    sfp1_tx_disable_o      => sfp1_tx_disable_o,
+    sfp1_los_i             => sfp1_los_i,
+    sfp1_refclk_sel_i      => sfp1_refclk_sel_i,
+    sfp1_rx_rbclk_o        => sfp1_rx_rbclk_o,
+    eeprom_scl_i           => eeprom_scl_i,
+    eeprom_scl_o           => eeprom_scl_o,
+    eeprom_sda_i           => eeprom_sda_i,
+    eeprom_sda_o           => eeprom_sda_o,
+    onewire_i              => onewire_i,
+    onewire_oen_o          => onewire_oen_o,
+    uart_rxd_i             => uart_rxd_i,
+    uart_txd_o             => uart_txd_o,
+    flash_sclk_o           => flash_sclk_o,
+    flash_ncs_o            => flash_ncs_o,
+    flash_mosi_o           => flash_mosi_o,
+    flash_miso_i           => flash_miso_i,
+    wb_slave_o             => wb_slave_o,
+    wb_slave_i             => wb_slave_i,
+    aux_master_o           => aux_master_o,
+    aux_master_i           => aux_master_i,
+    wrf_src_o              => wrf_src_o,
+    wrf_src_i              => wrf_src_i,
+    wrf_snk_o              => wrf_snk_o,
+    wrf_snk_i              => wrf_snk_i,
+    wb_eth_master_o        => wb_eth_master_o,
+    wb_eth_master_i        => wb_eth_master_i,
+    tm_link_up_o           => tm_link_up_o,
+    tm_time_valid_o        => tm_time_valid_o,
+    tm_tai_o               => tm_tai_o,
+    tm_cycles_o            => tm_cycles_o,
+    led_act_o              => led_act_o,
+    led_link_o             => led_link_o,
+    pps_led_o              => pps_led_o,
+    btn1_i                 => btn1_i,
+    btn2_i                 => btn2_i,
+    pps_valid_o            => pps_valid_o,
+    pps_p_o                => pps_p_o,
+    pps_csync_o            => pps_csync_o,
+    link_ok_o              => link_ok_o);
+
+end rtl;
--- a/top/cute_ref_design/cute_wr_ref_top.ucf
+++ b/top/cute_ref_design/cute_wr_ref_top.ucf
+config vccaux  = 3.3;
+
+# bank 0
+#net "clk1_m2c_p" loc = b3;net "clk1_m2c_p" iostandard = lvds_33;
+#net "clk1_m2c_n" loc = a3;net "clk1_m2c_n" iostandard = lvds_33;
+#net "la03_p" loc = e6;net "la03_p" iostandard = lvds_33;
+#net "la03_n" loc = f7;net "la03_n" iostandard = lvds_33;
+#net "la01_cc_p" loc = g8;net "la01_cc_p" iostandard = lvds_33;
+#net "la01_cc_n" loc = e8;net "la01_cc_n" iostandard = lvds_33;
+#net "la20_p" loc = g9;net "la20_p" iostandard = lvds_33;
+#net "la20_n" loc = g11;net "la20_n" iostandard = lvds_33;
+#net "la30_p" loc = c15;net "la30_p" iostandard = lvds_33;
+#net "la30_n" loc = a15;net "la30_n" iostandard = lvds_33;
+#net "la29_p" loc = b16;net "la29_p" iostandard = lvds_33;
+#net "la29_n" loc = a16;net "la29_n" iostandard = lvds_33;
+#net "la24_p" loc = e14;net "la24_p" iostandard = lvds_33;
+#net "la24_n" loc = d15;net "la24_n" iostandard = lvds_33;
+
+net "fpga_clk_p" loc = f12;net "fpga_clk_p" iostandard = lvds_33;
+net "fpga_clk_n" loc = e12;net "fpga_clk_n" iostandard = lvds_33;
+
+# bank 1
+net "pps_out" loc = c18;net "pps_out" iostandard = lvcmos33;
+net "usr_led1" loc = e18;net "usr_led1" iostandard = lvcmos33;
+net "usr_led2" loc = d17;net "usr_led2" iostandard = lvcmos33;
+
+#net "sfp1_tx_los" loc = f18;net "sfp1_tx_los" iostandard = lvcmos33;
+#net "sfp1_tx_fault" loc = h16;net "sfp1_tx_fault" iostandard = lvcmos33;
+#net "sfp1_det" loc = g16;net "sfp1_det" iostandard = lvcmos33;
+#net "sfp1_scl" loc = g18;net "sfp1_scl" iostandard = lvcmos33;
+#net "sfp1_sda" loc = h17;net "sfp1_sda" iostandard = lvcmos33;
+#net "sfp1_tx_disable" loc = h18;net "sfp1_tx_disable" iostandard = lvcmos33;
+
+net "eeprom_sda" loc = j18;net "eeprom_sda" iostandard = lvcmos33;
+net "eeprom_scl" loc = k17;net "eeprom_scl" iostandard = lvcmos33;
+
+#net "la32_p" loc = p17;net "la32_p" iostandard = lvds_33;
+#net "la32_n" loc = p18;net "la32_n" iostandard = lvds_33;
+#net "la33_p" loc = t17;net "la33_p" iostandard = lvds_33;
+#net "la33_n" loc = t18;net "la33_n" iostandard = lvds_33;
+#net "la31_p" loc = u17;net "la31_p" iostandard = lvds_33;
+#net "la31_n" loc = u18;net "la31_n" iostandard = lvds_33;
+
+# bank 2
+net "flash_sclk_o" loc = r15;net "flash_sclk_o" iostandard = lvcmos33;
+net "flash_ncs_o" loc = v3;net "flash_ncs_o" iostandard = lvcmos33;
+net "flash_mosi_o" loc = t13;net "flash_mosi_o" iostandard = lvcmos33;
+net "flash_miso_i" loc = r13;net "flash_miso_i" iostandard = lvcmos33;
+
+#net "la28_p" loc = u16;net "la28_p" iostandard = lvds_33;
+#net "la28_n" loc = v16;net "la28_n" iostandard = lvds_33;
+#net "la25_p" loc = u15;net "la25_p" iostandard = lvds_33;
+#net "la25_n" loc = v15;net "la25_n" iostandard = lvds_33;
+#net "la26_p" loc = t14;net "la26_p" iostandard = lvds_33;
+#net "la26_n" loc = v14;net "la26_n" iostandard = lvds_33;
+#net "la21_p" loc = u13;net "la21_p" iostandard = lvds_33;
+#net "la21_n" loc = v13;net "la21_n" iostandard = lvds_33;
+#net "la27_p" loc = m11;net "la27_p" iostandard = lvds_33;
+#net "la27_n" loc = n11;net "la27_n" iostandard = lvds_33;
+#net "la18_cc_p" loc = r11;net "la18_cc_p" iostandard = lvds_33;
+#net "la18_cc_n" loc = t11;net "la18_cc_n" iostandard = lvds_33;
+#net "la22_p" loc = t12;net "la22_p" iostandard = lvds_33;
+#net "la22_n" loc = v12;net "la22_n" iostandard = lvds_33;
+#net "la23_p" loc = n10;net "la23_p" iostandard = lvds_33;
+#net "la23_n" loc = p11;net "la23_n" iostandard = lvds_33;
+#net "la14_p" loc = m10;net "la14_p" iostandard = lvds_33;
+#net "la14_n" loc = n9;net "la14_n" iostandard = lvds_33;
+#net "la15_p" loc = u11;net "la15_p" iostandard = lvds_33;
+#net "la15_n" loc = v11;net "la15_n" iostandard = lvds_33;
+#net "la19_p" loc = r10;net "la19_p" iostandard = lvds_33;
+#net "la19_n" loc = t10;net "la19_n" iostandard = lvds_33;
+#net "la07_p" loc = u10;net "la07_p" iostandard = lvds_33;
+#net "la07_n" loc = v10;net "la07_n" iostandard = lvds_33;
+#net "la16_p" loc = r8;net "la16_p" iostandard = lvds_33;
+#net "la16_n" loc = t8;net "la16_n" iostandard = lvds_33;
+#net "la13_p" loc = t9;net "la13_p" iostandard = lvds_33;
+#net "la13_n" loc = v9;net "la13_n" iostandard = lvds_33;
+#net "la17_cc_p" loc = m8;net "la17_cc_p" iostandard = lvds_33;
+#net "la17_cc_n" loc = n8;net "la17_cc_n" iostandard = lvds_33;
+#net "la04_p" loc = t8;net "la04_p" iostandard = lvds_33;
+#net "la04_n" loc = v8;net "la04_n" iostandard = lvds_33;
+#net "la02_p" loc = u7;net "la02_p" iostandard = lvds_33;
+#net "la02_n" loc = v7;net "la02_n" iostandard = lvds_33;
+#net "la00_cc_p" loc = n7;net "la00_cc_p" iostandard = lvds_33;
+#net "la00_cc_n" loc = p8;net "la00_cc_n" iostandard = lvds_33;
+#net "la09_p" loc = t6;net "la09_p" iostandard = lvds_33;
+#net "la09_n" loc = v6;net "la09_n" iostandard = lvds_33;
+#net "la11_p" loc = r7;net "la11_p" iostandard = lvds_33;
+#net "la11_n" loc = t7;net "la11_n" iostandard = lvds_33;
+#net "la12_p" loc = n6;net "la12_p" iostandard = lvds_33;
+#net "la12_n" loc = p7;net "la12_n" iostandard = lvds_33;
+#net "la10_p" loc = r5;net "la10_p" iostandard = lvds_33;
+#net "la10_n" loc = t5;net "la10_n" iostandard = lvds_33;
+#net "clk0_m2c_p" loc = u5;net "clk0_m2c_p" iostandard = lvds_33;
+#net "clk0_m2c_n" loc = v5;net "clk0_m2c_n" iostandard = lvds_33;
+#net "la08_p" loc = r3;net "la08_p" iostandard = lvds_33;
+#net "la08_n" loc = t3;net "la08_n" iostandard = lvds_33;
+#net "la06_p" loc = t4;net "la06_p" iostandard = lvds_33;
+#net "la06_n" loc = v4;net "la06_n" iostandard = lvds_33;
+#net "la05_p" loc = n5;net "la05_p" iostandard = lvds_33;
+#net "la05_n" loc = p6;net "la05_n" iostandard = lvds_33;
+
+# bank 3
+net "clk20" loc = h1;net "clk20" iostandard = lvcmos33;
+net "usr_button" loc = h3;net "usr_button" iostandard = lvcmos33;
+net "one_wire" loc = h2;net "one_wire" iostandard = lvcmos33;
+net "uart_rx" loc = j1;net "uart_rx" iostandard = lvcmos33;
+net "uart_tx" loc = j3;net "uart_tx" iostandard = lvcmos33;
+
+net "plldac_din" loc = c1;net "plldac_din" iostandard = lvcmos33;
+net "plldac_clr_n" loc = e1;net "plldac_clr_n" iostandard = lvcmos33;
+net "plldac_sclk" loc = c2;net "plldac_sclk" iostandard = lvcmos33;
+net "plldac_sync_n" loc = d1;net "plldac_sync_n" iostandard = lvcmos33;
+net "plldac_load_n" loc = d2;net "plldac_load_n" iostandard = lvcmos33;
+
+#net "ext_clk"  loc = f2;net "ext_clk" iostandard = lvcmos33;
+net "sfp1_led" loc = g3;net "sfp1_led" iostandard = lvcmos33;
+net "sfp0_led" loc = k4;net "sfp0_led" iostandard = lvcmos33;
+net "sfp0_los" loc = g1;net "sfp0_los" iostandard = lvcmos33;
+net "sfp0_det" loc = f3;net "sfp0_det" iostandard = lvcmos33;
+net "sfp0_scl" loc = f1;net "sfp0_scl" iostandard = lvcmos33;
+net "sfp0_sda" loc = e4;net "sfp0_sda" iostandard = lvcmos33;
+net "sfp0_tx_fault" loc = d3;net "sfp0_tx_fault" iostandard = lvcmos33;
+net "sfp0_tx_disable" loc = e3;net "sfp0_tx_disable" iostandard = lvcmos33;
+
+# bank gtp
+net "sfp0_ref_clk_n" loc = c9;net "sfp0_ref_clk_n" iostandard = lvcmos33;
+net "sfp0_ref_clk_p" loc = d9;net "sfp0_ref_clk_p" iostandard = lvcmos33;
+net "sfp0_rx_n" loc = c7;
+net "sfp0_rx_p" loc = d7;
+net "sfp0_tx_n" loc = a6;
+net "sfp0_tx_p" loc = b6;
+
+net "sfp1_ref_clk_n" loc = e10;net "sfp1_ref_clk_n" iostandard = lvcmos33;
+net "sfp1_ref_clk_p" loc = f10;net "sfp1_ref_clk_p" iostandard = lvcmos33;
+#net "sfp1_rx_n" loc = c13;
+#net "sfp1_rx_p" loc = d13;
+#net "sfp1_tx_n" loc = a14;
+#net "sfp1_tx_p" loc = b14;
+
+#net "mgtrx0_n" loc = c5;
+#net "mgtrx0_p" loc = d5;
+#net "mgttx0_n" loc = a4;
+#net "mgttx0_p" loc = b4;
+
+#---------------------------------------------------------------------------------------------
+# clock period information 
+#---------------------------------------------------------------------------------------------
+net "clk20" tnm_net = "clk20";
+timespec ts_clk20 = period "clk20" 50 ns high 50 %;
+
+net "fpga_clk_i" tnm_net = "fpga_clk_i";
+timespec ts_fpga_clk_i = period "fpga_clk_i" 8 ns high 50 %;
+
+net "clk_sfp*_i" tnm_net = "clk_sfp_i";
+timespec ts_clk_sfp_i = period "clk_sfp_i" 8 ns high 50 %;
+
+net "u_wr_core/cmp_xwrc_board_cute/*u_gtp*/ch*_rx_rbclk_o" tnm_net = "phy_rx_clk";
+timespec ts_phy_rx_clk = period "phy_rx_clk" 8 ns high 50 %;
+
+net "u_wr_core/cmp_xwrc_board_cute/*u_gtp*/ch*_rx_divclk" tnm_net = "ch_rx_divclk";
+timespec ts_ch_rx_divclk = period "ch_rx_divclk" 8 ns high 50 %;
+
+net "u_wr_core/cmp_xwrc_board_cute/*u_gtp*/ch*_gtp_clkout_int[1]" tnm_net = "ch_gtp_clkout_int";
+timespec ts_ch_gtp_clkout_int = period "ch_gtp_clkout_int" 8 ns high 50 %;
\ No newline at end of file
--- a/top/cute_ref_design/cute_wr_ref_top.vhd
+++ b/top/cute_ref_design/cute_wr_ref_top.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_cute_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.endpoint_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity cute_wr_ref_top is
+generic (
+  g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
+  g_sfp0_enable : boolean:= true;
+  g_sfp1_enable : boolean:= false;
+  g_aux_sdb            : t_sdb_device  := c_xwb_xil_multiboot_sdb;
+  g_multiboot_enable   : boolean:= true
+);
+port
+(
+-- clock
+  clk20              : in std_logic;    -- 20mhz vcxo clock
+  fpga_clk_p         : in std_logic;  -- 125 mhz pll reference
+  fpga_clk_n         : in std_logic;
+  sfp0_ref_clk_p     : in std_logic;  -- dedicated clock for xilinx gtp transceiver
+  sfp0_ref_clk_n     : in std_logic;
+  sfp1_ref_clk_p     : in std_logic;  -- dedicated clock for xilinx gtp transceiver
+  sfp1_ref_clk_n     : in std_logic;
+  
+-- pll
+  plldac_sclk        : out std_logic;
+  plldac_din         : out std_logic;
+  plldac_clr_n       : out std_logic;
+  plldac_load_n      : out std_logic;
+  plldac_sync_n      : out std_logic;
+  
+-- eeprom
+  eeprom_scl         : inout std_logic;
+  eeprom_sda         : inout std_logic;
+  
+-- 1-wire
+  one_wire           : inout std_logic;      -- 1-wire interface to ds18b20
+  
+  -- flash
+  flash_sclk_o       : out std_logic;
+  flash_ncs_o        : out std_logic;
+  flash_mosi_o       : out std_logic;
+  flash_miso_i       : in  std_logic:='1';
+  
+  -- sfp0 pins
+  sfp0_tx_p          : out   std_logic;
+  sfp0_tx_n          : out   std_logic;
+  sfp0_rx_p          : in    std_logic;
+  sfp0_rx_n          : in    std_logic;
+  sfp0_det           : in    std_logic;  -- sfp detect
+  sfp0_scl           : inout std_logic;  -- scl
+  sfp0_sda           : inout std_logic;  -- sda
+  sfp0_tx_fault      : in    std_logic;
+  sfp0_tx_disable    : out   std_logic;
+  sfp0_los           : in    std_logic;  
+  --sfp1_tx_p          : out   std_logic;
+  --sfp1_tx_n          : out   std_logic;
+  --sfp1_rx_p          : in    std_logic;
+  --sfp1_rx_n          : in    std_logic;
+  --sfp1_det           : in    std_logic;  -- sfp detect
+  --sfp1_scl           : inout std_logic;  -- scl
+  --sfp1_sda           : inout std_logic;  -- sda
+  --sfp1_tx_fault      : in    std_logic;
+  --sfp1_tx_disable    : out   std_logic;
+  --sfp1_tx_los        : in    std_logic;
+
+  --uart
+  uart_rx            : in  std_logic;
+  uart_tx            : out std_logic;
+  
+  -- user interface
+  sfp0_led           : out std_logic;
+  sfp1_led           : out std_logic;
+  --ext_clk            : out std_logic;
+  usr_button         : in  std_logic;
+  usr_led1           : out std_logic;
+  usr_led2           : out std_logic;
+  pps_out            : out std_logic
+);
+end cute_wr_ref_top;
+
+architecture rtl of cute_wr_ref_top is
+
+------------------------------------------------------------------------------
+-- components declaration
+------------------------------------------------------------------------------
+component cute_reset_gen is
+  port (
+    clk_sys_i : in std_logic;
+    rst_button_n_a_i : in std_logic;
+    rst_n_o : out std_logic
+  );
+end component;
+
+component cute_serial_dac_arb is
+  generic(
+    g_invert_sclk    : boolean;
+    g_num_extra_bits : integer);
+  port(
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    val1_i  : in std_logic_vector(15 downto 0);
+    load1_i : in std_logic;
+    val2_i  : in std_logic_vector(15 downto 0);
+    load2_i : in std_logic;
+
+    dac_ldac_n_o : out std_logic;
+    dac_clr_n_o  : out std_logic;
+    dac_sync_n_o : out std_logic;
+    dac_sclk_o   : out std_logic;
+    dac_din_o    : out std_logic);
+
+end component;
+
+component cute_core_ref_top is
+  generic
+    (
+      g_simulation                : integer              := 0;
+      g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
+      g_sfp0_enable               : boolean:= true;
+      g_sfp1_enable               : boolean:= false;
+      g_aux_sdb                   : t_sdb_device  := c_xwb_xil_multiboot_sdb;
+      g_multiboot_enable          : boolean:= false);
+  port
+    (
+      rst_n_i              : in  std_logic;
+      clk_20m_i            : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      clk_sys_i            : in  std_logic;    
+      clk_ref_i            : in  std_logic;
+      clk_sfp0_i           : in  std_logic :='0';
+      clk_sfp1_i           : in  std_logic :='0';
+      dac_hpll_load_p1_o   : out std_logic;
+      dac_hpll_data_o      : out std_logic_vector(15 downto 0);
+      dac_dpll_load_p1_o   : out std_logic;
+      dac_dpll_data_o      : out std_logic_vector(15 downto 0);
+      eeprom_scl_i         : in  std_logic;
+      eeprom_scl_o         : out std_logic;
+      eeprom_sda_i         : in  std_logic;
+      eeprom_sda_o         : out std_logic;
+      flash_sclk_o         : out std_logic;
+      flash_ncs_o          : out std_logic;
+      flash_mosi_o         : out std_logic;
+      flash_miso_i         : in  std_logic:='1';
+      onewire_i            : in  std_logic;
+      onewire_oen_o        : out std_logic;
+      uart_rxd_i           : in  std_logic:='0';
+      uart_txd_o           : out std_logic;
+      sfp0_txp_o           : out std_logic;
+      sfp0_txn_o           : out std_logic;
+      sfp0_rxp_i           : in  std_logic:='0';
+      sfp0_rxn_i           : in  std_logic:='0';
+      sfp0_det_i           : in  std_logic:='0';  -- sfp detect
+      sfp0_scl_i           : in  std_logic:='0';  -- scl
+      sfp0_scl_o           : out std_logic;  -- scl
+      sfp0_sda_i           : in  std_logic:='0';  -- sda
+      sfp0_sda_o           : out std_logic;  -- sda
+      sfp0_rate_select_o   : out std_logic;
+      sfp0_tx_fault_i      : in  std_logic:='0';
+      sfp0_tx_disable_o    : out std_logic;
+      sfp0_los_i           : in  std_logic:='0';
+      sfp0_refclk_sel_i    : in  std_logic_vector(2 downto 0):="000";
+      sfp0_rx_rbclk_o      : out std_logic;
+      sfp1_txp_o           : out std_logic;
+      sfp1_txn_o           : out std_logic;
+      sfp1_rxp_i           : in  std_logic:='0';
+      sfp1_rxn_i           : in  std_logic:='0';
+      sfp1_det_i           : in  std_logic:='0';
+      sfp1_scl_i           : in  std_logic:='0';
+      sfp1_scl_o           : out std_logic:='0';
+      sfp1_sda_i           : in  std_logic:='0';
+      sfp1_sda_o           : out std_logic:='0';
+      sfp1_rate_select_o   : out std_logic;
+      sfp1_tx_fault_i      : in  std_logic:='0';
+      sfp1_tx_disable_o    : out std_logic;
+      sfp1_los_i           : in  std_logic:='0';
+      sfp1_refclk_sel_i    : in  std_logic_vector(2 downto 0):="000";
+      sfp1_rx_rbclk_o      : out std_logic;
+      wb_slave_o           : out t_wishbone_slave_out;
+      wb_slave_i           : in  t_wishbone_slave_in := cc_dummy_slave_in;
+      aux_master_o         : out t_wishbone_master_out;
+      aux_master_i         : in  t_wishbone_master_in := cc_dummy_master_in;
+      wrf_src_o            : out t_wrf_source_out;
+      wrf_src_i            : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o            : out t_wrf_sink_out;
+      wrf_snk_i            : in  t_wrf_sink_in   := c_dummy_snk_in;
+      wb_eth_master_o      : out t_wishbone_master_out;
+      wb_eth_master_i      : in  t_wishbone_master_in := cc_dummy_master_in;
+      tm_link_up_o         : out std_logic;
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      led_act_o            : out std_logic;
+      led_link_o           : out std_logic;
+      btn1_i               : in  std_logic := '1';
+      btn2_i               : in  std_logic := '1';
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+      pps_csync_o          : out std_logic;
+      link_ok_o            : out std_logic
+      );
+end component;
+
+------------------------------------------------------------------------------
+-- signals declaration
+------------------------------------------------------------------------------
+-- reset
+  signal local_reset_n : std_logic;
+-- clock
+  signal fpga_clk_i    : std_logic;
+  signal clk_ref_i     : std_logic;
+  signal clk_sys_i     : std_logic;
+  signal clk_dmtd_i    : std_logic;
+  signal clk_sfp0_i    : std_logic;
+  signal clk_sfp1_i    : std_logic;
+  signal clk_20m_buf   : std_logic;
+  signal pllout_clk_62_5   : std_logic;
+  signal pllout_clk_125    : std_logic;
+  signal pllout_clk_fb_ref : std_logic;
+  signal pllout_clk_fb_dmtd: std_logic;
+  signal pllout_clk_dmtd   : std_logic;
+  signal eeprom_scl_o      : std_logic;
+  signal eeprom_scl_i      : std_logic;
+  signal eeprom_sda_o      : std_logic;
+  signal eeprom_sda_i      : std_logic;
+  signal onewire_i         : std_logic;
+  signal onewire_oen_o     : std_logic;
+  signal sfp0_scl_i        : std_logic;
+  signal sfp0_scl_o        : std_logic;
+  signal sfp0_sda_i        : std_logic;
+  signal sfp0_sda_o        : std_logic;
+  signal sfp1_scl_i        : std_logic;
+  signal sfp1_scl_o        : std_logic;
+  signal sfp1_sda_i        : std_logic;
+  signal sfp1_sda_o        : std_logic;
+  signal dac_hpll_load_p1  : std_logic;
+  signal dac_dpll_load_p1  : std_logic;
+  signal dac_hpll_data     : std_logic_vector(15 downto 0);
+  signal dac_dpll_data     : std_logic_vector(15 downto 0);
+  
+  signal pps               : std_logic;
+  signal pps_p1            : std_logic;
+  signal tm_tai            : std_logic_vector(39 downto 0);
+  signal tm_tai_valid      : std_logic;
+  -- Wishbone buse(s) from masters attached to crossbar
+  signal cnx_master_out : t_wishbone_master_out_array(0 downto 0);
+  signal cnx_master_in  : t_wishbone_master_in_array(0 downto 0);
+  -- Wishbone buse(s) to slaves attached to crossbar
+  signal cnx_slave_out : t_wishbone_slave_out_array(0 downto 0);
+  signal cnx_slave_in  : t_wishbone_slave_in_array(0 downto 0);
+
+begin
+
+u_reset_gen : cute_reset_gen
+  port map (
+    clk_sys_i        => clk_sys_i,
+    rst_button_n_a_i => usr_button,
+    rst_n_o          => local_reset_n);
+
+cmp_refclk_buf : ibufgds
+  generic map (
+    diff_term    => true,             -- differential termination
+    ibuf_low_pwr => true,  -- low power (true) vs. performance (false) setting for referenced i/o standards
+    iostandard   => "default")
+  port map (
+    o  => fpga_clk_i,            -- buffer output
+    i  => fpga_clk_p,  -- diff_p buffer input (connect directly to top-level port)
+    ib => fpga_clk_n); -- diff_n buffer input (connect directly to top-level port)
+
+cmp_clk_vcxo_buf : bufg
+  port map (
+    o => clk_20m_buf,
+    i => clk20);
+    
+cmp_sfp0_dedicated_clk_buf : ibufds
+ generic map(
+   diff_term    => true,
+   ibuf_low_pwr => true,
+   iostandard   => "default")
+ port map (
+   o  => clk_sfp0_i,
+   i  => sfp0_ref_clk_p,
+   ib => sfp0_ref_clk_n);
+
+cmp_sfp1_dedicated_clk_buf : ibufds
+  generic map(
+    diff_term    => true,
+    ibuf_low_pwr => true,
+    iostandard   => "default")
+  port map (
+    o  => clk_sfp1_i,
+    i  => sfp1_ref_clk_p,
+    ib => sfp1_ref_clk_n);
+
+cmp_sys_clk_pll : pll_base
+  generic map (
+    bandwidth          => "optimized",
+    clk_feedback       => "clkfbout",
+    compensation       => "internal",
+    divclk_divide      => 1,
+    clkfbout_mult      => 8,
+    clkfbout_phase     => 0.000,
+    clkout0_divide     => 16,        -- 62.5 mhz
+    clkout0_phase      => 0.000,
+    clkout0_duty_cycle => 0.500,
+    clkout1_divide     => 8,         -- 125 mhz
+    clkout1_phase      => 0.000,
+    clkout1_duty_cycle => 0.500,
+    clkout2_divide     => 4,         -- 250 mhz
+    clkout2_phase      => 0.000,
+    clkout2_duty_cycle => 0.500,
+    clkin_period       => 8.0,
+    ref_jitter         => 0.016)
+  port map (
+    clkfbout => pllout_clk_fb_ref,
+    clkout0  => pllout_clk_62_5,
+    clkout1  => pllout_clk_125,
+    clkout2  => open,
+    clkout3  => open,
+    clkout4  => open,
+    clkout5  => open,
+    locked   => open,
+    rst      => '0',
+    clkfbin  => pllout_clk_fb_ref,
+    clkin    => fpga_clk_i);
+
+cmp_dmtd_clk_pll : pll_base
+  generic map (
+    bandwidth          => "optimized",
+    clk_feedback       => "clkfbout",
+    compensation       => "internal",
+    divclk_divide      => 1,
+    clkfbout_mult      => 50,
+    clkfbout_phase     => 0.000,
+    clkout0_divide     => 16,         -- 62.5 mhz
+    clkout0_phase      => 0.000,
+    clkout0_duty_cycle => 0.500,
+    clkout1_divide     => 16,         -- 62.5 mhz
+    clkout1_phase      => 0.000,
+    clkout1_duty_cycle => 0.500,
+    clkout2_divide     => 16,         -- 62.5 mhz
+    clkout2_phase      => 0.000,
+    clkout2_duty_cycle => 0.500,
+    clkin_period       => 50.0,
+    ref_jitter         => 0.016)
+  port map (
+    clkfbout => pllout_clk_fb_dmtd,
+    clkout0  => pllout_clk_dmtd,
+    clkout1  => open,
+    clkout2  => open,
+    clkout3  => open,
+    clkout4  => open,
+    clkout5  => open,
+    locked   => open,
+    rst      => '0',
+    clkfbin  => pllout_clk_fb_dmtd,
+    clkin    => clk_20m_buf);
+
+cmp_clk_sys_buf : bufg
+  port map (
+    o => clk_sys_i,
+    i => pllout_clk_62_5);
+
+cmd_clk_ref_buf: bufg
+  port map(
+    o => clk_ref_i,
+    i => pllout_clk_125);
+
+cmp_clk_dmtd_buf : bufg
+  port map (
+    o => clk_dmtd_i,
+    i => pllout_clk_dmtd);
+
+u_wr_core : cute_core_ref_top
+  generic map(
+    g_dpram_initf => g_dpram_initf,
+    g_sfp0_enable => g_sfp0_enable,
+    g_sfp1_enable => g_sfp1_enable,
+    g_aux_sdb     => g_aux_sdb,
+    g_multiboot_enable => g_multiboot_enable)
+  port map (
+    rst_n_i             => local_reset_n,
+    clk_20m_i           => clk_20m_buf,
+    clk_sys_i           => clk_sys_i,
+    clk_dmtd_i          => clk_dmtd_i,
+    clk_ref_i           => clk_ref_i,
+    clk_sfp0_i          => clk_sfp0_i,
+    clk_sfp1_i          => clk_sfp1_i,
+    dac_hpll_load_p1_o  => dac_hpll_load_p1,
+    dac_hpll_data_o     => dac_hpll_data,
+    dac_dpll_load_p1_o  => dac_dpll_load_p1,
+    dac_dpll_data_o     => dac_dpll_data,
+    eeprom_scl_i        => eeprom_scl_i,
+    eeprom_scl_o        => eeprom_scl_o,
+    eeprom_sda_i        => eeprom_sda_i,
+    eeprom_sda_o        => eeprom_sda_o,
+    onewire_i           => onewire_i,
+    onewire_oen_o       => onewire_oen_o,
+    flash_sclk_o        => flash_sclk_o,
+    flash_ncs_o         => flash_ncs_o,
+    flash_mosi_o        => flash_mosi_o,
+    flash_miso_i        => flash_miso_i,
+    uart_rxd_i          => uart_rx,
+    uart_txd_o          => uart_tx,
+    sfp0_txp_o          => sfp0_tx_p,
+    sfp0_txn_o          => sfp0_tx_n,
+    sfp0_rxp_i          => sfp0_rx_p,
+    sfp0_rxn_i          => sfp0_rx_n,
+    sfp0_det_i          => sfp0_det,
+    sfp0_scl_i          => sfp0_scl_i,
+    sfp0_scl_o          => sfp0_scl_o,
+    sfp0_sda_i          => sfp0_sda_i,
+    sfp0_sda_o          => sfp0_sda_o,
+    sfp0_rate_select_o  => open,
+    sfp0_tx_fault_i     => sfp0_tx_fault,
+    sfp0_tx_disable_o   => sfp0_tx_disable,
+    sfp0_los_i          => sfp0_los,
+    sfp0_refclk_sel_i   => "100",
+    sfp0_rx_rbclk_o     => open,
+    --sfp1_txp_o          => sfp1_tx_p,
+    --sfp1_txn_o          => sfp1_tx_n,
+    --sfp1_rxp_i          => sfp1_rx_p,
+    --sfp1_rxn_i          => sfp1_rx_n,
+    --sfp1_det_i          => sfp1_det,
+    --sfp1_scl_i          => sfp1_scl_i,
+    --sfp1_scl_o          => sfp1_scl_o,
+    --sfp1_sda_i          => sfp1_sda_i,
+    --sfp1_sda_o          => sfp1_sda_o,
+    --sfp1_rate_select_o  => open,
+    --sfp1_tx_fault_i     => sfp1_tx_fault,
+    --sfp1_tx_disable_o   => sfp1_tx_disable,
+    --sfp1_los_i          => sfp1_tx_los,
+    --sfp1_refclk_sel_i   => "100",
+    --sfp1_rx_rbclk_o     => open,
+    wb_slave_o          => cnx_slave_out(0),
+    wb_slave_i          => cnx_slave_in(0),
+    wb_eth_master_o     => cnx_master_out(0),
+    wb_eth_master_i     => cnx_master_in(0),
+    tm_link_up_o        => open,
+    tm_time_valid_o     => tm_tai_valid,
+    tm_tai_o            => tm_tai,
+    tm_cycles_o         => open,
+    led_act_o           => sfp0_led,
+    led_link_o          => sfp1_led,
+    pps_p_o             => pps_out,
+    pps_led_o           => usr_led1,
+    pps_csync_o         => pps_p1,
+    link_ok_o           => usr_led2);
+  
+  cnx_slave_in <= cnx_master_out;
+  cnx_master_in <= cnx_slave_out;
+
+  u_dac_arb: cute_serial_dac_arb
+  generic map (
+    g_invert_sclk => false,
+    g_num_extra_bits => 8)
+  port map (
+    clk_i         => clk_sys_i,
+    rst_n_i       => local_reset_n,
+    val1_i        => dac_dpll_data,
+    load1_i       => dac_dpll_load_p1,
+    val2_i        => dac_hpll_data,
+    load2_i       => dac_hpll_load_p1,
+    dac_sync_n_o  => plldac_sync_n,
+    dac_ldac_n_o  => plldac_load_n,
+    dac_clr_n_o   => plldac_clr_n,
+    dac_sclk_o    => plldac_sclk,
+    dac_din_o     => plldac_din);
+
+  eeprom_scl  <= '0' when eeprom_scl_o = '0' else 'Z';
+  eeprom_sda  <= '0' when eeprom_sda_o = '0' else 'Z';
+  eeprom_scl_i  <= eeprom_scl;
+  eeprom_sda_i  <= eeprom_sda;
+
+  sfp0_scl <= '0' when sfp0_scl_o = '0' else 'Z';
+  sfp0_sda <= '0' when sfp0_sda_o = '0' else 'Z';
+  sfp0_scl_i <= sfp0_scl;
+  sfp0_sda_i <= sfp0_sda;
+  --sfp1_scl <= '0' when sfp1_scl_o = '0' else 'Z';
+  --sfp1_sda <= '0' when sfp1_sda_o = '0' else 'Z';
+  --sfp1_scl_i <= sfp1_scl;
+  --sfp1_sda_i <= sfp1_sda;
+  
+  one_wire <= '0' when onewire_oen_o = '1' else 'Z';
+  onewire_i  <= one_wire;
+  
+end rtl;
--- a/top/readme_platforms.txt
+++ b/top/readme_platforms.txt
@@ -2,4 +2,5 @@ Available device plaftorms (so far):
 ------------------------------------

 gsi_scu - GSI's Scalable Control Unit (SCU), based on Altera ArriaII-GX (EP2AGX125)
-spec_1_1 - CERN's Simple PCI-Express Carrier (SPEC), based on Xilinx Spartan-6 (XC6SLX45). Version 1.1 or newer (pin-compatible)
\ No newline at end of file
+spec_1_1 - CERN's Simple PCI-Express Carrier (SPEC), based on Xilinx Spartan-6 (XC6SLX45). Version 1.1 or newer (pin-compatible)
+cute     - TSINGHUA's CUTEDP, based on Xilinx Spartan-6 (XC6SLX45T).
\ No newline at end of file