wr_streamers: included the generic to choose clk_data into streamers generic rx/tx records

Instead of adding another generic to streamers that later needs to be propagated outside of Board Support Package and potentially for each board, the choice of clock (clk_sys_i or clk_ref_i) is included in the record of generics for tx/rx path of streamers. Indeed, theoretically, such choice can be done per-path (rx and/or tx).

wr_streamers: included the generic to choose clk_data into streamers generic rx/tx records
Instead of adding another generic to streamers that later needs to be propagated outside of Board Support Package and potentially for each board, the choice of clock (clk_sys_i or clk_ref_i) is included in the record of generics for tx/rx path of streamers. Indeed, theoretically, such choice can be done per-path (rx and/or tx).
2f805ed6 · Maciej Lipinski · 4e9a8a43 · 2f805ed6 · 2f805ed6
Commit 2f805ed6 authored May 22, 2019 by Maciej Lipinski
Hide whitespace changes
Inline Side-by-side

Showing with 17 additions and 9 deletions

streamers_pkg.vhd modules/wr_streamers/streamers_pkg.vhd +12 -1

xwr_streamers.vhd modules/wr_streamers/xwr_streamers.vhd +5 -8

No files found.
--- a/modules/wr_streamers/streamers_pkg.vhd
+++ b/modules/wr_streamers/streamers_pkg.vhd
@@ -75,6 +75,11 @@ package streamers_pkg is
    -- legacy: the streamers initially used in Btrain did not check/insert the escape
    -- code. This is justified if only one block of a known number of words is sent/expected
    escape_code_disable   : boolean;
+    -- when non-zero, the datapath (tx port) are in the clk_ref_i clock
+    -- domain instead of clk_sys_i. This is a must for fixed latency mode if
+    -- clk_sys_i is asynchronous (i.e. not locked) to the WR timing.
+    use_ref_clk_for_data  : integer;
  end record;
  -----------------------------------------------------------------------------------------
@@ -105,6 +110,11 @@ package streamers_pkg is
    -- In combination with the g_escape_code_disable generic set to TRUE, the behaviour of
    -- the "Btrain streamers" can be recreated.
    expected_words_number : integer;
+    -- when non-zero, the datapath (rx port) are in the clk_ref_i clock
+    -- domain instead of clk_sys_i. This is a must for fixed latency mode if
+    -- clk_sys_i is asynchronous (i.e. not locked) to the WR timing.
+    use_ref_clk_for_data  : integer;
  end record;
  constant c_tx_streamer_params_defaut: t_tx_streamer_params :=(
@@ -113,12 +123,14 @@ package streamers_pkg is
      threshold             => 128,
      max_words_per_frame   => 256,
      timeout               => 1024,
+      use_ref_clk_for_data  => 0,
      escape_code_disable   => FALSE);
  constant c_rx_streamer_params_defaut: t_rx_streamer_params :=(
      data_width            => 32,
      buffer_size           => 256,
      escape_code_disable   => FALSE,
+      use_ref_clk_for_data  => 0,
      expected_words_number => 0);
  type t_rx_streamer_cfg is record
@@ -323,7 +335,6 @@ package streamers_pkg is
    g_slave_mode               : t_wishbone_interface_mode      := CLASSIC;
    g_slave_granularity        : t_wishbone_address_granularity := BYTE;
    g_simulation               : integer := 0;
-    g_use_ref_clock_for_data   : integer := 0;
    g_sim_cycle_counter_range  : integer := 125000
    );

--- a/modules/wr_streamers/xwr_streamers.vhd
+++ b/modules/wr_streamers/xwr_streamers.vhd
@@ -76,10 +76,7 @@ entity xwr_streamers is
    -- in the future, more frequences might be supported..
    g_clk_ref_rate             : integer := 125000000;
-    -- when non-zero, the datapath (tx_/rx_ ports) are in the clk_ref_i clock
-    -- domain instead of clk_sys_i. This is a must for fixed latency mode if
-    -- clk_sys_i is asynchronous (i.e. not locked) to the WR timing.
-    g_use_ref_clock_for_data : integer := 0;
    -----------------------------------------------------------------------------------------
    -- Transmission/reception parameters
@@ -114,12 +111,12 @@ entity xwr_streamers is
    ---------------------------------------------------------------------------
    -- System clock. Used always for the WR fabric interface (src/snk) and
-    -- for the data path (tx_/rx_ ports) if g_use_ref_clock_for_data = 0.
+    -- for the data path (tx_/rx_ ports) if use_ref_clk_for_data = 0.
    clk_sys_i                  : in std_logic;
    -- WR Reference clock, 62.5 or 125 MHz. Frequency must match g_ref_clk_rate
    -- generic. Used for latency measurement and timestamping (tm_ ports).
-    -- It also clocks Tx_/rx_ interfaces if g_use_ref_clock_for_data != 0.
+    -- It also clocks Tx_/rx_ interfaces if use_ref_clk_for_data != 0.
    clk_ref_i                  : in std_logic := '0';
    rst_n_i                    : in std_logic;
@@ -256,7 +253,7 @@ begin
        g_escape_code_disable    => g_tx_streamer_params.escape_code_disable,
        g_simulation             => g_simulation,
        g_clk_ref_rate           => g_clk_ref_rate,
-        g_use_ref_clock_for_data => g_use_ref_clock_for_data)
+        g_use_ref_clock_for_data => g_tx_streamer_params.use_ref_clk_for_data)
      port map(
        clk_sys_i                => clk_sys_i,
        clk_ref_i                => clk_ref_i,
@@ -296,7 +293,7 @@ begin
        g_clk_ref_rate           => g_clk_ref_rate,
        g_simulation => g_simulation,
        g_sim_cycle_counter_range => g_sim_cycle_counter_range,
-        g_use_ref_clock_for_data => g_use_ref_clock_for_data
+        g_use_ref_clock_for_data => g_rx_streamer_params.use_ref_clk_for_data
        )
      port map(
        clk_sys_i                => clk_sys_i,