remove aligned_10mhz_o and restore PPS on Spare BullsEye

25f431c5 · Peter Jansweijer · 309a4703 · 25f431c5 · 25f431c5
Commit 25f431c5 authored Apr 22, 2021 by Peter Jansweijer
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Showing with 14 additions and 14 deletions

spec7_wr_hpsec_top.xdc top/spec7_ref_design/spec7_wr_hpsec_top.xdc +12 -12

spec7_wr_ref_top.vhd top/spec7_ref_design/spec7_wr_ref_top.vhd +2 -2

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--- a/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
+++ b/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
@@ -4,11 +4,11 @@

 #   -- Local oscillators
 # Bank 112 -- 125.000 MHz GTX reference
-#set_property PACKAGE_PIN U6 [get_ports clk_125m_gtx_p_i]
-#set_property PACKAGE_PIN U5 [get_ports clk_125m_gtx_n_i]
+set_property PACKAGE_PIN U6 [get_ports clk_125m_gtx_p_i]
+set_property PACKAGE_PIN U5 [get_ports clk_125m_gtx_n_i]
 # Bank 111 -- 125.000 MHz GTX reference
-set_property PACKAGE_PIN W6 [get_ports clk_125m_gtx_p_i]
-set_property PACKAGE_PIN W5 [get_ports clk_125m_gtx_n_i]
+#set_property PACKAGE_PIN W6 [get_ports clk_125m_gtx_p_i]
+#set_property PACKAGE_PIN W5 [get_ports clk_125m_gtx_n_i]

 # Bank 35 (HP) VCCO - 1.8 V -- 124.992 MHz DMTD clock
 set_property PACKAGE_PIN D15 [get_ports clk_125m_dmtd_p_i]
@@ -245,11 +245,11 @@ set_property IOSTANDARD LVCMOS18 [get_ports sda_b]
 # PPS_OUT
 # Bulls-Eye A01, A02
 # Bank 35 (HP) VCCO - 1.8 V
-set_property PACKAGE_PIN G16 [get_ports be_pps_p_o]
-set_property IOSTANDARD LVDS [get_ports be_pps_p_o]
+#set_property PACKAGE_PIN G16 [get_ports be_pps_p_o]
+#set_property IOSTANDARD LVDS [get_ports be_pps_p_o]
 # Bank 35 (HP) VCCO - 1.8 V
-set_property PACKAGE_PIN G15 [get_ports be_pps_n_o]
-set_property IOSTANDARD LVDS [get_ports be_pps_n_o]
+#set_property PACKAGE_PIN G15 [get_ports be_pps_n_o]
+#set_property IOSTANDARD LVDS [get_ports be_pps_n_o]

 # 10MHz_out
 # Bulls-Eye A03, A04
@@ -286,10 +286,10 @@ set_property IOSTANDARD LVDS [get_ports be_abscal_txts_n_o]
 #set_property PACKAGE_PIN J15 [get_ports be_spare_n_o]
 #set_property IOSTANDARD LVDS [get_ports be_spare_n_o]
 # Use Spare outputs for PPS_o to avoid reclocking for the time being
-set_property PACKAGE_PIN K15 [get_ports aligned_10mhz_o]
-set_property IOSTANDARD LVCMOS18 [get_ports aligned_10mhz_o]
-#set_property PACKAGE_PIN J15 [get_ports be_pps_n_o]
-#set_property IOSTANDARD LVDS [get_ports be_pps_n_o]
+set_property PACKAGE_PIN K15 [get_ports be_pps_p_o]
+set_property IOSTANDARD LVDS [get_ports be_pps_p_o]
+set_property PACKAGE_PIN J15 [get_ports be_pps_n_o]
+set_property IOSTANDARD LVDS [get_ports be_pps_n_o]

 # PPS_IN
 # Bulls-Eye B01, B02

--- a/top/spec7_ref_design/spec7_wr_ref_top.vhd
+++ b/top/spec7_ref_design/spec7_wr_ref_top.vhd
@@ -161,7 +161,7 @@ entity spec7_wr_ref_top is

    -- blink 1-PPS.
    led_pps_o       : out std_logic;
-    aligned_10mhz_o : out std_logic;
+
    ---------------------------------------------------------------------------
    -- EEPROM interface
    ---------------------------------------------------------------------------
@@ -590,7 +590,7 @@ AXI2WB : xwb_axi4lite_bridge
      pps_ext_i           => wrc_pps_in,
      pps_p_o             => wrc_pps_out,
      pps_led_o           => wrc_pps_led,
-      aligned_10mhz_o     => aligned_10mhz_o,
+      aligned_10mhz_o     => open,
      clk_10m_out_o       => clk_10m_out,
      led_link_o          => led_link_o,
      led_act_o           => led_act_o);