Skip to content

W
White Rabbit core collection
Commit 25deb517 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
Browse files
Options

wr_endpoint: cleanup low phase drift calibration interface

parent 07eda292
Hide whitespace changes
Inline Side-by-side
Showing with 105 additions and 68 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 25deb517
......@@ -120,7 +120,7 @@ package endpoint_pkg is
rdy : std_logic;
sfp_tx_fault : std_logic;
sfp_los : std_logic;
debug : std_logic_vector(15 downto 0);
lpc_stat : std_logic_vector(15 downto 0);
end record;
type t_phy_16bits_from_wrc is record
......@@ -131,7 +131,7 @@ package endpoint_pkg is
loopen_vec : std_logic_vector(2 downto 0);
tx_prbs_sel : std_logic_vector(2 downto 0);
sfp_tx_disable : std_logic;
debug : std_logic_vector(15 downto 0);
lpc_ctrl : std_logic_vector(15 downto 0);
end record;
......@@ -200,6 +200,7 @@ package endpoint_pkg is
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false;
g_phy_lpcalib : boolean := false;
g_ep_idx : integer := 0);
port (
clk_ref_i : in std_logic;
......@@ -220,8 +221,8 @@ package endpoint_pkg is
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_rdy_i : in std_logic;
phy_debug_i : in std_logic_vector(15 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_lpc_stat_i : in std_logic_vector(15 downto 0) := (others=>'0');
phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......@@ -315,7 +316,8 @@ package endpoint_pkg is
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false;
g_ep_idx : integer := 0);
g_phy_lpcalib : boolean := false;
g_ep_idx : integer := 0);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -335,8 +337,8 @@ package endpoint_pkg is
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_rdy_i : in std_logic;
phy_debug_i : in std_logic_vector(15 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_lpc_stat_i : in std_logic_vector(15 downto 0) := (others=>'0');
phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 25deb517
......@@ -137,8 +137,8 @@ package endpoint_private_pkg is
txpcs_timestamp_trigger_p_a_o : out std_logic;
link_ok_o : out std_logic;
link_ctr_i : in std_logic := '1';
serdes_debug_i : in std_logic_vector(15 downto 0);
serdes_debug_o : out std_logic_vector(15 downto 0);
serdes_stat_i : in std_logic_vector(15 downto 0);
serdes_ctrl_o : out std_logic_vector(15 downto 0);
serdes_rst_o : out std_logic;
serdes_loopen_o : out std_logic;
serdes_loopen_vec_o : out std_logic_vector(2 downto 0);
......@@ -359,8 +359,8 @@ package endpoint_private_pkg is
mdio_ectrl_sfp_loss_i : in std_logic;
mdio_ectrl_sfp_tx_disable_o : out std_logic;
mdio_ectrl_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
mdio_dbg0_i : in std_logic_vector(15 downto 0);
mdio_dbg1_o : out std_logic_vector(15 downto 0));
mdio_lpc_phy_stat_i : in std_logic_vector(15 downto 0);
mdio_lpc_phy_ctrl_o : out std_logic_vector(15 downto 0));
end component ep_pcs_tbi_mdio_wb;
component ep_tx_header_processor
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ 25deb517
......@@ -146,9 +146,9 @@ entity ep_1000basex_pcs is
-- 1: serdes is locked and aligned
serdes_rdy_i : in std_logic;
-- debug/test feature signals to the PHY
serdes_debug_i : in std_logic_vector(15 downto 0);
serdes_debug_o : out std_logic_vector(15 downto 0);
-- low phase drift feature signals to the PHY
serdes_stat_i : in std_logic_vector(15 downto 0);
serdes_ctrl_o : out std_logic_vector(15 downto 0);
---------------------------------------------------------------------------
......@@ -478,9 +478,8 @@ begin -- rtl
mdio_ectrl_sfp_loss_i => serdes_sfp_los_i,
mdio_ectrl_sfp_tx_disable_o => serdes_sfp_tx_disable_o,
mdio_ectrl_tx_prbs_sel_o => serdes_tx_prbs_sel_o,
mdio_dbg0_i => serdes_debug_i,
mdio_dbg1_o => serdes_debug_o,
mdio_lpc_phy_stat_i => serdes_stat_i,
mdio_lpc_phy_ctrl_o => serdes_ctrl_o,
lstat_read_notify_o => lstat_read_notify
);
......
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
View file @ 25deb517
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created : Fri Jun 23 11:00:15 2017
-- Created : Fri Jul 12 10:34:39 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
......@@ -82,10 +82,10 @@ entity ep_pcs_tbi_mdio_wb is
mdio_ectrl_sfp_tx_disable_o : out std_logic;
-- Port for std_logic_vector field: 'tx_prbs_sel' in reg: 'MDIO Extended Control Register'
mdio_ectrl_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
-- Port for std_logic_vector field: 'Debug word 0' in reg: 'MDIO Debug Register 0'
mdio_dbg0_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Debug word 1' in reg: 'MDIO Debug Register 1'
mdio_dbg1_o : out std_logic_vector(15 downto 0)
-- Port for std_logic_vector field: 'Control word 0' in reg: 'Low phase drift calibration status register'
mdio_lpc_phy_stat_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Control word 0' in reg: 'Low phase drift calibration control register'
mdio_lpc_phy_ctrl_o : out std_logic_vector(15 downto 0)
);
end ep_pcs_tbi_mdio_wb;
......@@ -121,7 +121,7 @@ signal mdio_wr_spec_bslide_lwb_s2 : std_logic ;
signal mdio_ectrl_lpbck_vec_int : std_logic_vector(2 downto 0);
signal mdio_ectrl_sfp_tx_disable_int : std_logic ;
signal mdio_ectrl_tx_prbs_sel_int : std_logic_vector(2 downto 0);
signal mdio_dbg1_int : std_logic_vector(15 downto 0);
signal mdio_lpc_phy_ctrl_int : std_logic_vector(15 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -167,7 +167,7 @@ begin
mdio_ectrl_lpbck_vec_int <= "000";
mdio_ectrl_sfp_tx_disable_int <= '0';
mdio_ectrl_tx_prbs_sel_int <= "000";
mdio_dbg1_int <= "0000000000000000";
mdio_lpc_phy_ctrl_int <= "0000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -504,7 +504,7 @@ begin
when "10010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= mdio_dbg0_i;
rddata_reg(15 downto 0) <= mdio_lpc_phy_stat_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -525,9 +525,9 @@ begin
ack_in_progress <= '1';
when "10011" =>
if (wb_we_i = '1') then
mdio_dbg1_int <= wrdata_reg(15 downto 0);
mdio_lpc_phy_ctrl_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= mdio_dbg1_int;
rddata_reg(15 downto 0) <= mdio_lpc_phy_ctrl_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -681,9 +681,9 @@ begin
mdio_ectrl_sfp_tx_disable_o <= mdio_ectrl_sfp_tx_disable_int;
-- tx_prbs_sel
mdio_ectrl_tx_prbs_sel_o <= mdio_ectrl_tx_prbs_sel_int;
-- Debug word 0
-- Debug word 1
mdio_dbg1_o <= mdio_dbg1_int;
-- Control word 0
-- Control word 0
mdio_lpc_phy_ctrl_o <= mdio_lpc_phy_ctrl_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/wr_endpoint/ep_registers_pkg.vhd
View file @ 25deb517
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Mon Nov 12 15:47:03 2018
-- Created : Fri Jul 12 10:34:39 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -24,6 +24,7 @@ package ep_wbgen2_pkg is
ecr_feat_dmtd_i : std_logic;
ecr_feat_ptp_i : std_logic;
ecr_feat_dpi_i : std_logic;
ecr_feat_lpc_i : std_logic;
tscr_cs_done_i : std_logic;
tscr_rx_cal_result_i : std_logic;
tcar_pcp_map_i : std_logic_vector(23 downto 0);
......@@ -48,6 +49,7 @@ package ep_wbgen2_pkg is
ecr_feat_dmtd_i => '0',
ecr_feat_ptp_i => '0',
ecr_feat_dpi_i => '0',
ecr_feat_lpc_i => '0',
tscr_cs_done_i => '0',
tscr_rx_cal_result_i => '0',
tcar_pcp_map_i => (others => '0'),
......@@ -241,6 +243,7 @@ tmp.ecr_feat_vlan_i := f_x_to_zero(left.ecr_feat_vlan_i) or f_x_to_zero(right.ec
tmp.ecr_feat_dmtd_i := f_x_to_zero(left.ecr_feat_dmtd_i) or f_x_to_zero(right.ecr_feat_dmtd_i);
tmp.ecr_feat_ptp_i := f_x_to_zero(left.ecr_feat_ptp_i) or f_x_to_zero(right.ecr_feat_ptp_i);
tmp.ecr_feat_dpi_i := f_x_to_zero(left.ecr_feat_dpi_i) or f_x_to_zero(right.ecr_feat_dpi_i);
tmp.ecr_feat_lpc_i := f_x_to_zero(left.ecr_feat_lpc_i) or f_x_to_zero(right.ecr_feat_lpc_i);
tmp.tscr_cs_done_i := f_x_to_zero(left.tscr_cs_done_i) or f_x_to_zero(right.tscr_cs_done_i);
tmp.tscr_rx_cal_result_i := f_x_to_zero(left.tscr_rx_cal_result_i) or f_x_to_zero(right.tscr_rx_cal_result_i);
tmp.tcar_pcp_map_i := f_x_to_zero(left.tcar_pcp_map_i) or f_x_to_zero(right.tcar_pcp_map_i);
......
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @ 25deb517
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Mon Nov 12 15:47:03 2018
-- Created : Fri Jul 12 10:34:39 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -84,12 +84,22 @@ signal ep_mdio_asr_phyad_int : std_logic_vector(7 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -219,6 +229,7 @@ begin
rddata_reg(25) <= regs_i.ecr_feat_dmtd_i;
rddata_reg(26) <= regs_i.ecr_feat_ptp_i;
rddata_reg(27) <= regs_i.ecr_feat_dpi_i;
rddata_reg(28) <= regs_i.ecr_feat_lpc_i;
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -234,7 +245,6 @@ begin
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
......@@ -715,6 +725,7 @@ begin
-- Feature present: DDMTD phase measurement
-- Feature present: IEEE1588 timestamper
-- Feature present: DPI packet classifier
-- Feature present: low phase drift calibration
-- Transmit timestamping enable
regs_o.tscr_en_txts_o <= ep_tscr_en_txts_int;
-- Receive timestamping enable
......
modules/wr_endpoint/ep_wishbone_controller.wb
View file @ 25deb517
......@@ -141,6 +141,16 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: low phase drift calibration";
description = "1: this port can be calibrated for low phase uncertainty on link up\
0: this is a standard WR port with regular performance";
prefix = "FEAT_LPC";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......
modules/wr_endpoint/pcs_regs.wb
View file @ 25deb517
......@@ -36,6 +36,7 @@
peripheral {
name = "WR Endpoint 1000base-X TBI PCS register block";
description = "WR Endpoint 1000base-X TBI PCS register block";
hdl_entity = "ep_pcs_tbi_mdio_wb";
prefix = "MDIO";
......@@ -790,10 +791,11 @@ peripheral {
};
reg {
name = "MDIO Debug Register 0";
prefix = "DBG0";
name = "Low phase drift calibration status register";
description = "Low phase drift calibration status register - dependent on calibrated PHY";
prefix = "LPC_PHY_STAT";
field {
name = "Debug word 0";
name = "Control word 0";
size = 16;
type = SLV;
access_bus = READ_ONLY;
......@@ -801,10 +803,11 @@ peripheral {
};
};
reg {
name = "MDIO Debug Register 1";
prefix = "DBG1";
name = "Low phase drift calibration control register";
description = "Low phase drift calibration control register - dependent on calibrated PHY";
prefix = "LPC_PHY_CTRL";
field {
name = "Debug word 1";
name = "Control word 0";
size = 16;
type = SLV;
access_bus = READ_WRITE;
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 25deb517
......@@ -75,7 +75,8 @@ entity wr_endpoint is
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false;
g_ep_idx : integer := 0
g_phy_lpcalib : boolean := false;
g_ep_idx : integer := 0
);
port (
......@@ -118,8 +119,8 @@ entity wr_endpoint is
phy_sfp_los_i : in std_logic;
phy_sfp_tx_disable_o : out std_logic;
phy_rdy_i : in std_logic;
phy_debug_i : in std_logic_vector(15 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_lpc_stat_i : in std_logic_vector(15 downto 0) := (others=>'0');
phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......@@ -526,8 +527,8 @@ begin
serdes_sfp_los_i => phy_sfp_los_i,
serdes_sfp_tx_disable_o => phy_sfp_tx_disable_o,
serdes_rdy_i => phy_rdy_i,
serdes_debug_i => phy_debug_i,
serdes_debug_o => phy_debug_o,
serdes_stat_i => phy_lpc_stat_i,
serdes_ctrl_o => phy_lpc_ctrl_o,
serdes_tx_clk_i => phy_ref_clk_i,
serdes_tx_data_o => phy_tx_data_o,
......@@ -821,6 +822,8 @@ begin
regs_towb_ep.ecr_feat_dmtd_i <= '0';
regs_towb_ep.ecr_feat_ptp_i <= '0';
regs_towb_ep.ecr_feat_dpi_i <= '0';
regs_towb_ep.ecr_feat_lpc_i <= '1' when(g_phy_lpcalib = true) else
'0';
regs_towb_ep.tscr_cs_done_i <= '0';
regs_towb_ep.tscr_rx_cal_result_i <= '0';
regs_towb_ep.tcar_pcp_map_i <= (others => '0');
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 25deb517
......@@ -66,7 +66,8 @@ entity xwr_endpoint is
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false;
g_ep_idx : integer
g_phy_lpcalib : boolean := false;
g_ep_idx : integer
);
port (
......@@ -109,9 +110,8 @@ entity xwr_endpoint is
phy_sfp_los_i : in std_logic;
phy_sfp_tx_disable_o : out std_logic;
phy_rdy_i : in std_logic;
phy_debug_i : in std_logic_vector(15 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_lpc_stat_i : in std_logic_vector(15 downto 0) := (others=>'0');
phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......@@ -301,7 +301,8 @@ architecture syn of xwr_endpoint is
signal sfp_tx_fault : std_logic;
signal sfp_los : std_logic;
signal phy_debug_in, phy_debug_out: std_logic_vector(15 downto 0);
signal phy_lpc_stat_in : std_logic_vector(15 downto 0);
signal phy_lpc_ctrl_out : std_logic_vector(15 downto 0);
begin
U_Wrapped_Endpoint : wr_endpoint
......@@ -325,7 +326,8 @@ begin
g_use_new_rxcrc => g_use_new_rxcrc,
g_use_new_txcrc => g_use_new_txcrc,
g_with_stop_traffic => g_with_stop_traffic,
g_ep_idx => g_ep_idx)
g_phy_lpcalib => g_phy_lpcalib,
g_ep_idx => g_ep_idx)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......@@ -343,8 +345,8 @@ begin
phy_loopen_vec_o => phy_loopen_vec,
phy_tx_prbs_sel_o => phy_tx_prbs_sel,
phy_rdy_i => phy_rdy,
phy_debug_i => phy_debug_in,
phy_debug_o => phy_debug_out,
phy_lpc_stat_i => phy_lpc_stat_in,
phy_lpc_ctrl_o => phy_lpc_ctrl_out,
phy_sfp_tx_fault_i => sfp_tx_fault,
phy_sfp_los_i => sfp_los,
......@@ -452,7 +454,7 @@ begin
phy16_o.tx_k <= phy_tx_k;
phy16_o.tx_prbs_sel <= phy_tx_prbs_sel;
phy16_o.sfp_tx_disable <= sfp_tx_disable;
phy16_o.debug <= phy_debug_out;
phy16_o.lpc_ctrl <= phy_lpc_ctrl_out;
phy_tx_clk <= phy16_i.ref_clk;
phy_tx_disparity <= phy16_i.tx_disparity;
......@@ -463,7 +465,7 @@ begin
phy_rx_enc_err <= phy16_i.rx_enc_err;
phy_rx_bts <= phy16_i.rx_bitslide;
phy_rdy <= phy16_i.rdy;
phy_debug_in <= phy16_i.debug;
phy_lpc_stat_in <= phy16_i.lpc_stat;
sfp_tx_fault <= phy16_i.sfp_tx_fault;
sfp_los <= phy16_i.sfp_los;
......@@ -519,7 +521,7 @@ begin
phy_tx_k_o <= phy_tx_k;
phy_tx_prbs_sel_o <= phy_tx_prbs_sel;
phy_sfp_tx_disable_o <= sfp_tx_disable;
phy_debug_o <= phy_debug_out;
phy_lpc_ctrl_o <= phy_lpc_ctrl_out;
phy_tx_clk <= phy_ref_clk_i;
phy_tx_disparity <= phy_tx_disparity_i;
......@@ -530,7 +532,7 @@ begin
phy_rx_enc_err <= phy_rx_enc_err_i;
phy_rx_bts <= phy_rx_bitslide_i;
phy_rdy <= phy_rdy_i;
phy_debug_in <= phy_debug_i;
phy_lpc_stat_in <= phy_lpc_stat_i;
sfp_tx_fault <= phy_sfp_tx_fault_i;
sfp_los <= phy_sfp_los_i;
......
platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
View file @ 25deb517
......@@ -122,8 +122,8 @@ entity wr_gtx_phy_virtex6_lp is
rdy_o : out std_logic;
debug_i : in std_logic_vector(15 downto 0) := x"0000";
debug_o : out std_logic_vector(15 downto 0);
lpc_ctrl_i : in std_logic_vector(15 downto 0) := x"0000";
lpc_stat_o : out std_logic_vector(15 downto 0);
TX_CLK_o : out std_logic
......@@ -288,10 +288,10 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
begin -- rtl
tx_sw_reset <= debug_i(0);
tx_enable <= debug_i(1);
rx_enable <= debug_i(2);
rx_sw_reset <= debug_i(3);
tx_sw_reset <= lpc_ctrl_i(0);
tx_enable <= lpc_ctrl_i(1);
rx_enable <= lpc_ctrl_i(2);
rx_sw_reset <= lpc_ctrl_i(3);
U_SyncTxEnable : gc_sync_ffs
port map
......@@ -352,8 +352,8 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
clk_dmtd_i => clk_dmtd_i,
clk_sampled_o => tx_out_clk_sampled);
clk_sampled_o <= rx_rec_clk_sampled when debug_i(15 downto 14) = "00" else
tx_out_clk_sampled when debug_i(15 downto 14) = "01" else
clk_sampled_o <= rx_rec_clk_sampled when lpc_ctrl_i(15 downto 14) = "00" else
tx_out_clk_sampled when lpc_ctrl_i(15 downto 14) = "01" else
'0';
......@@ -394,7 +394,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
gtx_tx_reset_done_i => gtx_tx_rst_done,
done_o => tx_reset_done);
debug_o(0) <= tx_reset_done;
lpc_stat_o(0) <= tx_reset_done;
gen_rx_bufg : if(g_rxclk_bufr = false) generate
......@@ -524,8 +524,8 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
rx_disp_err <= (others => '0');
debug_o(1) <= link_up;
debug_o(2) <= link_aligned;
lpc_stat_o(1) <= link_up;
lpc_stat_o(2) <= link_aligned;
p_gen_rx_outputs : process(rx_rec_clk, gtx_rst)
begin
......
sim/endpoint_mdio.v
View file @ 25deb517
......@@ -140,3 +140,5 @@
`define MDIO_ECTRL_SFP_TX_DISABLE 32'h00000020
`define MDIO_ECTRL_TX_PRBS_SEL_OFFSET 8
`define MDIO_ECTRL_TX_PRBS_SEL 32'h00000700
`define ADDR_MDIO_LPC_PHY_STAT 7'h48
`define ADDR_MDIO_LPC_PHY_CTRL 7'h4c
sim/endpoint_regs.v
View file @ 25deb517
......@@ -17,6 +17,8 @@
`define EP_ECR_FEAT_PTP 32'h04000000
`define EP_ECR_FEAT_DPI_OFFSET 27
`define EP_ECR_FEAT_DPI 32'h08000000
`define EP_ECR_FEAT_LPC_OFFSET 28
`define EP_ECR_FEAT_LPC 32'h10000000
`define ADDR_EP_TSCR 7'h4
`define EP_TSCR_EN_TXTS_OFFSET 0
`define EP_TSCR_EN_TXTS 32'h00000001
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment