Commit 2464c1e2 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

adding Vivado project to generate Fasec board module with WR PTP Core

parent 0bc881d2
target = "xilinx"
action = "synthesis"
syn_device = "xc7z030"
syn_grade = "-2"
syn_package = "ffg676"
syn_top = "wrc_board_fasec"
syn_project = "fasec_wr_ref_top"
syn_tool = "vivado"
modules = { "local" : [
"../../",
"../../board/fasec/" ] }
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