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White Rabbit core collection
Commit 23901cd9 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Maciej Lipinski
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wr_streamers: post-cleanup/rebase fixes + update of sim wr_streamers header

parent cdad3f33
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Showing with 24 additions and 1 deletion
modules/wr_streamers/fixed_latency_delay.vhd
View file @ 23901cd9
......@@ -227,9 +227,11 @@ begin
ts_tai_i => fifo_target_ts_tai,
ts_cycles_i => fifo_target_ts_cycles,
ts_latency_i => rx_streamer_cfg_i.fixed_latency,
ts_timeout_i => rx_streamer_cfg_i.fixed_latency_timeout,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
timeout_o => delay_timeout,
match_o => delay_match,
late_o => delay_miss);
......
modules/wr_streamers/fixed_latency_ts_match.vhd
View file @ 23901cd9
......@@ -107,9 +107,11 @@ begin
if g_clk_ref_rate = 62500000 then
tm_cycles_scaled <= unsigned(tm_cycles_i & '0');
ts_latency_scaled <= unsigned(ts_latency_i & '0');
ts_timeout_scaled <= unsigned(ts_timeout_i & '0');
elsif g_clk_ref_rate = 125000000 then
tm_cycles_scaled <= unsigned('0' & tm_cycles_i);
ts_latency_scaled <= unsigned('0' & ts_latency_i);
ts_timeout_scaled <= unsigned('0' & ts_timeout_i);
else
report "Unsupported g_clk_ref_rate (62.5 / 125 MHz)" severity failure;
end if;
......@@ -182,7 +184,7 @@ begin
ts_timeout_tai <= ts_timeout_tai + 1;
end if;
State <= CHECK_LATE;
state <= CHECK_LATE;
when CHECK_LATE =>
......
modules/wr_streamers/xtx_streamer.vhd
View file @ 23901cd9
......@@ -199,6 +199,7 @@ architecture rtl of xtx_streamer is
signal tag_cycles : std_logic_vector(27 downto 0);
signal tag_valid, tag_valid_latched : std_logic;
signal tag_error : std_logic;
signal link_ok_delay_cnt : unsigned(25 downto 0);
signal link_ok_delay_expired : std_logic;
......
sim/wr_streamers_wb.svh
View file @ 23901cd9
......@@ -135,3 +135,21 @@
`define ADDR_WR_STREAMERS_DUMMY 8'h84
`define WR_STREAMERS_DUMMY_DUMMY_OFFSET 0
`define WR_STREAMERS_DUMMY_DUMMY 32'hffffffff
`define ADDR_WR_STREAMERS_RSTR 8'h88
`define WR_STREAMERS_RSTR_RST_SW_OFFSET 0
`define WR_STREAMERS_RSTR_RST_SW 32'h00000001
`define ADDR_WR_STREAMERS_RX_STAT14 8'h8c
`define WR_STREAMERS_RX_STAT14_RX_BUF_OVERFLOW_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT14_RX_BUF_OVERFLOW_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT15 8'h90
`define WR_STREAMERS_RX_STAT15_RX_LATE_FRAMES_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT15_RX_LATE_FRAMES_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT16 8'h94
`define WR_STREAMERS_RX_STAT16_RX_TIMEOUT_FRAMES_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT16_RX_TIMEOUT_FRAMES_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT17 8'h98
`define WR_STREAMERS_RX_STAT17_RX_MATCH_FRAMES_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT17_RX_MATCH_FRAMES_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG6 8'h9c
`define WR_STREAMERS_RX_CFG6_RX_FIXED_LATENCY_TIMEOUT_OFFSET 0
`define WR_STREAMERS_RX_CFG6_RX_FIXED_LATENCY_TIMEOUT 32'h0fffffff
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