Commit 228f9b7e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk

wr_endpoint: added MDIO debug registers and corresponding PHY ports

parent 75d89d93
......@@ -120,6 +120,8 @@ package endpoint_pkg is
rdy : std_logic;
sfp_tx_fault : std_logic;
sfp_los : std_logic;
debug : std_logic_vector(15 downto 0);
end record;
type t_phy_16bits_from_wrc is record
rst : std_logic;
......@@ -129,14 +131,16 @@ package endpoint_pkg is
loopen_vec : std_logic_vector(2 downto 0);
tx_prbs_sel : std_logic_vector(2 downto 0);
sfp_tx_disable : std_logic;
debug : std_logic_vector(15 downto 0);
end record;
constant c_dummy_phy16_to_wrc : t_phy_16bits_to_wrc :=
('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0',
(others=>'0'), '0', '0', '0');
(others=>'0'), '0', '0', '0', (others => '0'));
constant c_dummy_phy16_from_wrc : t_phy_16bits_from_wrc :=
('0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
(others=>'0'), '0');
(others=>'0'), '0', (others => '0'));
-- debug CS types
......@@ -216,6 +220,9 @@ package endpoint_pkg is
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_rdy_i : in std_logic;
phy_debug_i : in std_logic_vector(15 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
......@@ -328,6 +335,9 @@ package endpoint_pkg is
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_rdy_i : in std_logic;
phy_debug_i : in std_logic_vector(15 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
......
......@@ -137,6 +137,8 @@ package endpoint_private_pkg is
txpcs_timestamp_trigger_p_a_o : out std_logic;
link_ok_o : out std_logic;
link_ctr_i : in std_logic := '1';
serdes_debug_i : in std_logic_vector(15 downto 0);
serdes_debug_o : out std_logic_vector(15 downto 0);
serdes_rst_o : out std_logic;
serdes_loopen_o : out std_logic;
serdes_loopen_vec_o : out std_logic_vector(2 downto 0);
......@@ -356,8 +358,10 @@ package endpoint_private_pkg is
mdio_ectrl_sfp_tx_fault_i : in std_logic;
mdio_ectrl_sfp_loss_i : in std_logic;
mdio_ectrl_sfp_tx_disable_o : out std_logic;
mdio_ectrl_tx_prbs_sel_o : out std_logic_vector(2 downto 0));
end component;
mdio_ectrl_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
mdio_dbg0_i : in std_logic_vector(15 downto 0);
mdio_dbg1_o : out std_logic_vector(15 downto 0));
end component ep_pcs_tbi_mdio_wb;
component ep_tx_header_processor
generic (
......
......@@ -146,6 +146,11 @@ entity ep_1000basex_pcs is
-- 1: serdes is locked and aligned
serdes_rdy_i : in std_logic;
-- debug/test feature signals to the PHY
serdes_debug_i : in std_logic_vector(15 downto 0);
serdes_debug_o : out std_logic_vector(15 downto 0);
---------------------------------------------------------------------------
-- Serdes TX path (all synchronous to serdes_tx_clk_i)
---------------------------------------------------------------------------
......@@ -474,6 +479,9 @@ begin -- rtl
mdio_ectrl_sfp_tx_disable_o => serdes_sfp_tx_disable_o,
mdio_ectrl_tx_prbs_sel_o => serdes_tx_prbs_sel_o,
mdio_dbg0_i => serdes_debug_i,
mdio_dbg1_o => serdes_debug_o,
lstat_read_notify_o => lstat_read_notify
);
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created : Wed Aug 16 22:43:42 2017
-- Created : Fri Jun 23 11:00:15 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
......@@ -81,7 +81,11 @@ entity ep_pcs_tbi_mdio_wb is
-- Port for BIT field: 'SFP TX Disable' in reg: 'MDIO Extended Control Register'
mdio_ectrl_sfp_tx_disable_o : out std_logic;
-- Port for std_logic_vector field: 'tx_prbs_sel' in reg: 'MDIO Extended Control Register'
mdio_ectrl_tx_prbs_sel_o : out std_logic_vector(2 downto 0)
mdio_ectrl_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
-- Port for std_logic_vector field: 'Debug word 0' in reg: 'MDIO Debug Register 0'
mdio_dbg0_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Debug word 1' in reg: 'MDIO Debug Register 1'
mdio_dbg1_o : out std_logic_vector(15 downto 0)
);
end ep_pcs_tbi_mdio_wb;
......@@ -117,15 +121,26 @@ signal mdio_wr_spec_bslide_lwb_s2 : std_logic ;
signal mdio_ectrl_lpbck_vec_int : std_logic_vector(2 downto 0);
signal mdio_ectrl_sfp_tx_disable_int : std_logic ;
signal mdio_ectrl_tx_prbs_sel_int : std_logic_vector(2 downto 0);
signal mdio_dbg1_int : std_logic_vector(15 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -152,6 +167,7 @@ begin
mdio_ectrl_lpbck_vec_int <= "000";
mdio_ectrl_sfp_tx_disable_int <= '0';
mdio_ectrl_tx_prbs_sel_int <= "000";
mdio_dbg1_int <= "0000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -485,6 +501,51 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= mdio_dbg0_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
if (wb_we_i = '1') then
mdio_dbg1_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= mdio_dbg1_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -620,6 +681,9 @@ begin
mdio_ectrl_sfp_tx_disable_o <= mdio_ectrl_sfp_tx_disable_int;
-- tx_prbs_sel
mdio_ectrl_tx_prbs_sel_o <= mdio_ectrl_tx_prbs_sel_int;
-- Debug word 0
-- Debug word 1
mdio_dbg1_o <= mdio_dbg1_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
......@@ -788,5 +788,29 @@ peripheral {
access_dev = READ_ONLY;
};
};
reg {
name = "MDIO Debug Register 0";
prefix = "DBG0";
field {
name = "Debug word 0";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "MDIO Debug Register 1";
prefix = "DBG1";
field {
name = "Debug word 1";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
......@@ -118,6 +118,8 @@ entity wr_endpoint is
phy_sfp_los_i : in std_logic;
phy_sfp_tx_disable_o : out std_logic;
phy_rdy_i : in std_logic;
phy_debug_i : in std_logic_vector(15 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......@@ -524,6 +526,8 @@ begin
serdes_sfp_los_i => phy_sfp_los_i,
serdes_sfp_tx_disable_o => phy_sfp_tx_disable_o,
serdes_rdy_i => phy_rdy_i,
serdes_debug_i => phy_debug_i,
serdes_debug_o => phy_debug_o,
serdes_tx_clk_i => phy_ref_clk_i,
serdes_tx_data_o => phy_tx_data_o,
......
......@@ -110,6 +110,9 @@ entity xwr_endpoint is
phy_sfp_tx_disable_o : out std_logic;
phy_rdy_i : in std_logic;
phy_debug_i : in std_logic_vector(15 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
......@@ -298,6 +301,7 @@ architecture syn of xwr_endpoint is
signal sfp_tx_fault : std_logic;
signal sfp_los : std_logic;
signal phy_debug_in, phy_debug_out: std_logic_vector(15 downto 0);
begin
U_Wrapped_Endpoint : wr_endpoint
......@@ -339,6 +343,8 @@ begin
phy_loopen_vec_o => phy_loopen_vec,
phy_tx_prbs_sel_o => phy_tx_prbs_sel,
phy_rdy_i => phy_rdy,
phy_debug_i => phy_debug_in,
phy_debug_o => phy_debug_out,
phy_sfp_tx_fault_i => sfp_tx_fault,
phy_sfp_los_i => sfp_los,
......@@ -446,6 +452,7 @@ begin
phy16_o.tx_k <= phy_tx_k;
phy16_o.tx_prbs_sel <= phy_tx_prbs_sel;
phy16_o.sfp_tx_disable <= sfp_tx_disable;
phy16_o.debug <= phy_debug_out;
phy_tx_clk <= phy16_i.ref_clk;
phy_tx_disparity <= phy16_i.tx_disparity;
......@@ -456,6 +463,7 @@ begin
phy_rx_enc_err <= phy16_i.rx_enc_err;
phy_rx_bts <= phy16_i.rx_bitslide;
phy_rdy <= phy16_i.rdy;
phy_debug_in <= phy16_i.debug;
sfp_tx_fault <= phy16_i.sfp_tx_fault;
sfp_los <= phy16_i.sfp_los;
......@@ -511,6 +519,7 @@ begin
phy_tx_k_o <= phy_tx_k;
phy_tx_prbs_sel_o <= phy_tx_prbs_sel;
phy_sfp_tx_disable_o <= sfp_tx_disable;
phy_debug_o <= phy_debug_out;
phy_tx_clk <= phy_ref_clk_i;
phy_tx_disparity <= phy_tx_disparity_i;
......@@ -521,6 +530,7 @@ begin
phy_rx_enc_err <= phy_rx_enc_err_i;
phy_rx_bts <= phy_rx_bitslide_i;
phy_rdy <= phy_rdy_i;
phy_debug_in <= phy_debug_i;
sfp_tx_fault <= phy_sfp_tx_fault_i;
sfp_los <= phy_sfp_los_i;
......
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