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Commits
1c374dfc
Commit
1c374dfc
authored
Nov 06, 2020
by
Pascal Bos
Browse files
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Plain Diff
updated design
parent
a962be1c
Pipeline
#621
failed with stages
in 2 minutes and 1 second
Changes
4
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1
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4 changed files
with
250 additions
and
390 deletions
+250
-390
wr_spidr4_pkg.vhd
board/spidr4/wr_spidr4_pkg.vhd
+52
-104
xwrc_board_spidr4.vhd
board/spidr4/xwrc_board_spidr4.vhd
+6
-6
Manifest.py
platform/xilinx/wr_gtp_phy/Manifest.py
+2
-1
spidr4_wr_ref_top.vhd
top/spidr4_ref_design/spidr4_wr_ref_top.vhd
+190
-279
No files found.
board/spidr4/wr_spidr4_pkg.vhd
View file @
1c374dfc
...
...
@@ -151,121 +151,69 @@ package wr_spidr4_pkg is
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
xwrc_board_spidr4
;
component
Pcie_wrapper
is
port
(
aclk1_0
:
in
STD_LOGIC
;
pcie_clk
:
in
STD_LOGIC
;
pcie_rst_n
:
in
STD_LOGIC
;
user_lnk_up_0
:
out
STD_LOGIC
;
usr_irq_ack_0
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
usr_irq_req_0
:
in
STD_LOGIC_VECTOR
(
0
to
0
);
M00_AXI_0_awaddr
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_awlen
:
out
STD_LOGIC_VECTOR
(
7
downto
0
);
M00_AXI_0_awsize
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_awburst
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_awlock
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
M00_AXI_0_awcache
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_awprot
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_awqos
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_awvalid
:
out
STD_LOGIC
;
M00_AXI_0_awready
:
in
STD_LOGIC
;
M00_AXI_0_wdata
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_wstrb
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_wlast
:
out
STD_LOGIC
;
M00_AXI_0_wvalid
:
out
STD_LOGIC
;
M00_AXI_0_wready
:
in
STD_LOGIC
;
M00_AXI_0_bresp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_bvalid
:
in
STD_LOGIC
;
M00_AXI_0_bready
:
out
STD_LOGIC
;
M00_AXI_0_araddr
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_arlen
:
out
STD_LOGIC_VECTOR
(
7
downto
0
);
M00_AXI_0_arsize
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_arburst
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_arlock
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
M00_AXI_0_arcache
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_arprot
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_arqos
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_arvalid
:
out
STD_LOGIC
;
M00_AXI_0_arready
:
in
STD_LOGIC
;
M00_AXI_0_rdata
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_rresp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_rlast
:
in
STD_LOGIC
;
M00_AXI_0_rvalid
:
in
STD_LOGIC
;
M00_AXI_0_rready
:
out
STD_LOGIC
;
pcie_mgt_0_rxn
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_mgt_0_rxp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_mgt_0_txn
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_mgt_0_txp
:
out
STD_LOGIC_VECTOR
(
1
downto
0
)
);
end
component
Pcie_wrapper
;
component
processing_system_pcie_wrapper
is
port
(
aclk1_0
:
in
STD_LOGIC
;
pcie_clk
:
in
STD_LOGIC
;
pcie_rst_n
:
in
STD_LOGIC
;
user_lnk_up_0
:
out
STD_LOGIC
;
usr_irq_ack_0
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
usr_irq_req_0
:
in
STD_LOGIC_VECTOR
(
0
to
0
);
component
zynq_subsystem
is
port
(
ARESETN
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
AXI_CLK_100MHz
:
out
STD_LOGIC
;
DDR_addr
:
inout
STD_LOGIC_VECTOR
(
14
downto
0
);
DDR_ba
:
inout
STD_LOGIC_VECTOR
(
2
downto
0
);
DDR_cas_n
:
inout
STD_LOGIC
;
DDR_cke
:
inout
STD_LOGIC
;
DDR_ck_n
:
inout
STD_LOGIC
;
DDR_ck_p
:
inout
STD_LOGIC
;
DDR_cke
:
inout
STD_LOGIC
;
DDR_cs_n
:
inout
STD_LOGIC
;
DDR_reset_n
:
inout
STD_LOGIC
;
DDR_odt
:
inout
STD_LOGIC
;
DDR_ras_n
:
inout
STD_LOGIC
;
DDR_we_n
:
inout
STD_LOGIC
;
DDR_ba
:
inout
STD_LOGIC_VECTOR
(
2
downto
0
);
DDR_addr
:
inout
STD_LOGIC_VECTOR
(
14
downto
0
);
DDR_dm
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR_dq
:
inout
STD_LOGIC_VECTOR
(
31
downto
0
);
DDR_dqs_n
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR_dqs_p
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
FIXED_IO_mio
:
inout
STD_LOGIC_VECTOR
(
53
downto
0
);
DDR_odt
:
inout
STD_LOGIC
;
DDR_ras_n
:
inout
STD_LOGIC
;
DDR_reset_n
:
inout
STD_LOGIC
;
DDR_we_n
:
inout
STD_LOGIC
;
FIXED_IO_ddr_vrn
:
inout
STD_LOGIC
;
FIXED_IO_ddr_vrp
:
inout
STD_LOGIC
;
FIXED_IO_
ps_srstb
:
inout
STD_LOGIC
;
FIXED_IO_
mio
:
inout
STD_LOGIC_VECTOR
(
53
downto
0
)
;
FIXED_IO_ps_clk
:
inout
STD_LOGIC
;
FIXED_IO_ps_porb
:
inout
STD_LOGIC
;
M00_AXI_0_awaddr
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_awlen
:
out
STD_LOGIC_VECTOR
(
7
downto
0
);
M00_AXI_0_awsize
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_awburst
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_awlock
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
M00_AXI_0_awcache
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_awprot
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_awqos
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_awvalid
:
out
STD_LOGIC
;
M00_AXI_0_awready
:
in
STD_LOGIC
;
M00_AXI_0_wdata
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_wstrb
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_wlast
:
out
STD_LOGIC
;
M00_AXI_0_wvalid
:
out
STD_LOGIC
;
M00_AXI_0_wready
:
in
STD_LOGIC
;
M00_AXI_0_bresp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_bvalid
:
in
STD_LOGIC
;
M00_AXI_0_bready
:
out
STD_LOGIC
;
M00_AXI_0_araddr
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_arlen
:
out
STD_LOGIC_VECTOR
(
7
downto
0
);
M00_AXI_0_arsize
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_arburst
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_arlock
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
M00_AXI_0_arcache
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_arprot
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_arqos
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_arvalid
:
out
STD_LOGIC
;
M00_AXI_0_arready
:
in
STD_LOGIC
;
M00_AXI_0_rdata
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_rresp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_rlast
:
in
STD_LOGIC
;
M00_AXI_0_rvalid
:
in
STD_LOGIC
;
M00_AXI_0_rready
:
out
STD_LOGIC
;
pcie_mgt_0_rxn
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_mgt_0_rxp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_mgt_0_txn
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_mgt_0_txp
:
out
STD_LOGIC_VECTOR
(
1
downto
0
)
FIXED_IO_ps_srstb
:
inout
STD_LOGIC
;
M_AXI_0_araddr
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M_AXI_0_arprot
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M_AXI_0_arready
:
in
STD_LOGIC
;
M_AXI_0_arvalid
:
out
STD_LOGIC
;
M_AXI_0_awaddr
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M_AXI_0_awprot
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M_AXI_0_awready
:
in
STD_LOGIC
;
M_AXI_0_awvalid
:
out
STD_LOGIC
;
M_AXI_0_bready
:
out
STD_LOGIC
;
M_AXI_0_bresp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
M_AXI_0_bvalid
:
in
STD_LOGIC
;
M_AXI_0_rdata
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
M_AXI_0_rready
:
out
STD_LOGIC
;
M_AXI_0_rresp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
M_AXI_0_rvalid
:
in
STD_LOGIC
;
M_AXI_0_wdata
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M_AXI_0_wready
:
in
STD_LOGIC
;
M_AXI_0_wstrb
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M_AXI_0_wvalid
:
out
STD_LOGIC
;
SPI_0_0_io0_i
:
in
STD_LOGIC
;
SPI_0_0_io0_o
:
out
STD_LOGIC
;
SPI_0_0_io0_t
:
out
STD_LOGIC
;
SPI_0_0_io1_i
:
in
STD_LOGIC
;
SPI_0_0_io1_o
:
out
STD_LOGIC
;
SPI_0_0_io1_t
:
out
STD_LOGIC
;
SPI_0_0_sck_i
:
in
STD_LOGIC
;
SPI_0_0_sck_o
:
out
STD_LOGIC
;
SPI_0_0_sck_t
:
out
STD_LOGIC
;
SPI_0_0_ss1_o
:
out
STD_LOGIC
;
SPI_0_0_ss2_o
:
out
STD_LOGIC
;
SPI_0_0_ss_i
:
in
STD_LOGIC
;
SPI_0_0_ss_o
:
out
STD_LOGIC
;
SPI_0_0_ss_t
:
out
STD_LOGIC
;
SYS_CLK_20MHz
:
out
STD_LOGIC
;
SYS_CLK_40MHz
:
out
STD_LOGIC
;
UART_0_0_rxd
:
in
STD_LOGIC
;
UART_0_0_txd
:
out
STD_LOGIC
);
end
component
processing_system_pcie_wrapper
;
end
component
zynq_subsystem
;
end
wr_spidr4_pkg
;
board/spidr4/xwrc_board_spidr4.vhd
View file @
1c374dfc
...
...
@@ -4,16 +4,16 @@
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_board_spidr4.vhd
-- Author(s) : P
eter Jansweijer <peterj
@nikhef.nl>
-- Author(s) : P
ascal BOs <bosp
@nikhef.nl>
-- Company : Nikhef
-- Created : 20
17
-26-08
-- Last update: 20
17
-26-08
-- Created : 20
20
-26-08
-- Last update: 20
20
-26-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SPIDR4 board.
-------------------------------------------------------------------------------
-- Copyright (c) 20
17
Nikhef
-- Copyright (c) 20
20
Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
...
...
@@ -334,7 +334,7 @@ begin -- architecture struct
areset_n_i
=>
areset_n_i
,
clk_10m_ext_i
=>
clk_10m_ext_i
,
clk_125m_dmtd_i
=>
clk_125m_dmtd_buf
,
clk_125m_gtp_p_i
=>
clk_125m_gtx_p_i
,
--Note clbv4 used GTX instead of GTPs
clk_125m_gtp_p_i
=>
clk_125m_gtx_p_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtx_n_i
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_txp_o
=>
sfp_txp_o
,
...
...
@@ -444,7 +444,7 @@ begin -- architecture struct
generic
map
(
g_simulation
=>
g_simulation
,
g_with_external_clock_input
=>
g_with_external_clock_input
,
g_board_name
=>
"
CLB
4"
,
g_board_name
=>
"
SPIDR
4"
,
g_phys_uart
=>
TRUE
,
g_virtual_uart
=>
TRUE
,
g_aux_clks
=>
g_aux_clks
,
...
...
platform/xilinx/wr_gtp_phy/Manifest.py
View file @
1c374dfc
...
...
@@ -27,6 +27,7 @@ elif (syn_device[0:4].upper()=="XC7A"): # Family 7 GTP (Artix7)
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd"
,
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd"
]);
elif
(
syn_device
[
0
:
4
]
.
upper
()
==
"XC7K"
or
# Family 7 GTX (Kintex7 and Virtex7 585, 2000, X485)
syn_device
[
0
:
4
]
.
upper
()
==
"XC7Z"
or
syn_device
[
0
:
7
]
.
upper
()
==
"XC7V585"
or
syn_device
[
0
:
8
]
.
upper
()
==
"XC7V2000"
or
syn_device
[
0
:
8
]
.
upper
()
==
"XC7VX485"
):
...
...
@@ -37,4 +38,4 @@ elif (syn_device[0:4].upper()=="XC7V"): # Family 7 GTH (other Virtex7 devices)
"whiterabbit_gthe2_channel_wrapper_gt.vhd"
,
"whiterabbit_gthe2_channel_wrapper_gtrxreset_seq.vhd"
,
"whiterabbit_gthe2_channel_wrapper_sync_block.vhd"
]);
\ No newline at end of file
top/spidr4_ref_design/spidr4_wr_ref_top.vhd
View file @
1c374dfc
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