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White Rabbit core collection
Commit 1c134a8c authored by Tristan Gingold's avatar Tristan Gingold
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top: use loopback for spec and svec ref designs

parent 946baf6c
Pipeline #4253 failed with stage
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    top/spec_ref_design/spec_wr_ref_top.vhd
    View file @ 1c134a8c
    ......@@ -375,7 +375,7 @@ begin -- architecture top
    g_simulation => g_simulation,
    g_with_external_clock_input => TRUE,
    g_dpram_initf => g_dpram_initf,
    g_fabric_iface => ETHERBONE)
    g_fabric_iface => LOOPBACK)
    port map (
    areset_n_i => button1_i,
    areset_edge_n_i => gn_rst_n,
    ......
    top/svec_ref_design/svec_wr_ref_top.vhd
    View file @ 1c134a8c
    ......@@ -56,7 +56,7 @@ use work.wishbone_pkg.all;
    use work.vme64x_pkg.all;
    use work.wr_board_pkg.all;
    use work.wr_svec_pkg.all;
    use work.synthesis_descriptor.all;
    -- use work.synthesis_descriptor.all;
    library unisim;
    use unisim.vcomponents.all;
    ......@@ -363,7 +363,7 @@ begin -- architecture top
    g_simulation => g_simulation,
    g_with_external_clock_input => TRUE,
    g_dpram_initf => g_dpram_initf,
    g_fabric_iface => ETHERBONE)
    g_fabric_iface => LOOPBACK)
    port map (
    clk_20m_vcxo_i => clk_20m_vcxo_i,
    clk_125m_pllref_p_i => clk_125m_pllref_p_i,
    ......
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