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White Rabbit core collection
Commit 1bcdf807 authored by Maciej Lipinski's avatar Maciej Lipinski
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wr_streamers: extended new fixed-latency stats to 64 bits (as all other stats)

parent 2f805ed6
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modules/wr_streamers/wr_streamers_wb.vhd
View file @ 1bcdf807
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wr_streamers_wb.vhd -- File : wr_streamers_wb.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb -- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed May 22 18:20:08 2019 -- Created : Wed May 22 19:52:32 2019
-- Version : 0x00000001 -- Version : 0x00000001
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -641,22 +641,40 @@ begin ...@@ -641,22 +641,40 @@ begin
when "100100" => when "100100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat15_rx_late_frames_cnt_i; rddata_reg(31 downto 0) <= regs_i.rx_stat15_rx_late_frames_cnt_lsb_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "100101" => when "100101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat16_rx_timeout_frames_cnt_i; rddata_reg(31 downto 0) <= regs_i.rx_stat16_rx_late_frames_cnt_msb_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "100110" => when "100110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat17_rx_match_frames_cnt_i; rddata_reg(31 downto 0) <= regs_i.rx_stat17_rx_timeout_frames_cnt_lsb_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "100111" => when "100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat18_rx_timeout_frames_cnt_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat19_rx_match_frames_cnt_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat20_rx_match_frames_cnt_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int <= wrdata_reg(27 downto 0); wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int <= wrdata_reg(27 downto 0);
end if; end if;
...@@ -800,9 +818,12 @@ begin ...@@ -800,9 +818,12 @@ begin
-- WR Streamer RX Buffer Overflow Count -- WR Streamer RX Buffer Overflow Count
-- WR Streamer RX Late Frames Count -- WR Streamer RX Late Frames Count (LSB)
-- WR Streamer RX Timed-out Frames Count -- WR Streamer RX Late Frames Count (MSB)
-- WR Streamer RX OK Frames Count -- WR Streamer RX Timed-out Frames Count (LSB)
-- WR Streamer RX Timed-out Frames Count (MSB)
-- WR Streamer RX OK Frames Count (LSB)
-- WR Streamer RX OK Frames Count (MSB)
-- RX Fixed Latency Timeout (Default: 0x1000000=~134ms) -- RX Fixed Latency Timeout (Default: 0x1000000=~134ms)
regs_o.rx_cfg6_rx_fixed_latency_timeout_o <= wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int; regs_o.rx_cfg6_rx_fixed_latency_timeout_o <= wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int;
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
......
modules/wr_streamers/wr_streamers_wb.wb
View file @ 1bcdf807
...@@ -664,9 +664,9 @@ peripheral { ...@@ -664,9 +664,9 @@ peripheral {
name = "Rx statistics"; name = "Rx statistics";
prefix = "RX_STAT15"; prefix = "RX_STAT15";
field { field {
name = "WR Streamer RX Late Frames Count"; name = "WR Streamer RX Late Frames Count (LSB)";
description = "Number of RX frames that missed their fixed-latency deadline"; description = "Number of RX frames that missed their fixed-latency deadline";
prefix = "RX_LATE_FRAMES_CNT"; prefix = "RX_LATE_FRAMES_CNT_LSB";
type = SLV; type = SLV;
size = 32; size = 32;
access_bus = READ_ONLY; access_bus = READ_ONLY;
...@@ -678,9 +678,9 @@ peripheral { ...@@ -678,9 +678,9 @@ peripheral {
name = "Rx statistics"; name = "Rx statistics";
prefix = "RX_STAT16"; prefix = "RX_STAT16";
field { field {
name = "WR Streamer RX Timed-out Frames Count"; name = "WR Streamer RX Late Frames Count (MSB)";
description = "Number of RX frames that had their execution timestamp too far in the future (exceeding the RX_CFG6 value)"; description = "Number of RX frames that missed their fixed-latency deadline";
prefix = "RX_TIMEOUT_FRAMES_CNT"; prefix = "RX_LATE_FRAMES_CNT_MSB";
type = SLV; type = SLV;
size = 32; size = 32;
access_bus = READ_ONLY; access_bus = READ_ONLY;
...@@ -692,15 +692,56 @@ peripheral { ...@@ -692,15 +692,56 @@ peripheral {
name = "Rx statistics"; name = "Rx statistics";
prefix = "RX_STAT17"; prefix = "RX_STAT17";
field { field {
name = "WR Streamer RX OK Frames Count"; name = "WR Streamer RX Timed-out Frames Count (LSB)";
description = "Number of RX frames that had their execution timestamp too far in the future (exceeding the RX_CFG6 value)";
prefix = "RX_TIMEOUT_FRAMES_CNT_LSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT18";
field {
name = "WR Streamer RX Timed-out Frames Count (MSB)";
description = "Number of RX frames that had their execution timestamp too far in the future (exceeding the RX_CFG6 value)";
prefix = "RX_TIMEOUT_FRAMES_CNT_MSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT19";
field {
name = "WR Streamer RX OK Frames Count (LSB)";
description = "Number of RX executed on time in the fixed latency mode"; description = "Number of RX executed on time in the fixed latency mode";
prefix = "RX_MATCH_FRAMES_CNT"; prefix = "RX_MATCH_FRAMES_CNT_LSB";
type = SLV; type = SLV;
size = 32; size = 32;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
}; };
reg {
name = "Rx statistics";
prefix = "RX_STAT20";
field {
name = "WR Streamer RX OK Frames Count (MSB)";
description = "Number of RX executed on time in the fixed latency mode";
prefix = "RX_MATCH_FRAMES_CNT_MSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg { reg {
name = "Rx Config Reg 6"; name = "Rx Config Reg 6";
......
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @ 1bcdf807
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd -- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb -- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed May 22 18:20:08 2019 -- Created : Wed May 22 19:52:32 2019
-- Version : 0x00000001 -- Version : 0x00000001
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -42,9 +42,12 @@ package wr_streamers_wbgen2_pkg is ...@@ -42,9 +42,12 @@ package wr_streamers_wbgen2_pkg is
dbg_data_i : std_logic_vector(31 downto 0); dbg_data_i : std_logic_vector(31 downto 0);
dummy_dummy_i : std_logic_vector(31 downto 0); dummy_dummy_i : std_logic_vector(31 downto 0);
rx_stat14_rx_buf_overflow_cnt_i : std_logic_vector(31 downto 0); rx_stat14_rx_buf_overflow_cnt_i : std_logic_vector(31 downto 0);
rx_stat15_rx_late_frames_cnt_i : std_logic_vector(31 downto 0); rx_stat15_rx_late_frames_cnt_lsb_i : std_logic_vector(31 downto 0);
rx_stat16_rx_timeout_frames_cnt_i : std_logic_vector(31 downto 0); rx_stat16_rx_late_frames_cnt_msb_i : std_logic_vector(31 downto 0);
rx_stat17_rx_match_frames_cnt_i : std_logic_vector(31 downto 0); rx_stat17_rx_timeout_frames_cnt_lsb_i : std_logic_vector(31 downto 0);
rx_stat18_rx_timeout_frames_cnt_msb_i : std_logic_vector(31 downto 0);
rx_stat19_rx_match_frames_cnt_lsb_i : std_logic_vector(31 downto 0);
rx_stat20_rx_match_frames_cnt_msb_i : std_logic_vector(31 downto 0);
end record; end record;
constant c_wr_streamers_in_registers_init_value: t_wr_streamers_in_registers := ( constant c_wr_streamers_in_registers_init_value: t_wr_streamers_in_registers := (
...@@ -69,9 +72,12 @@ package wr_streamers_wbgen2_pkg is ...@@ -69,9 +72,12 @@ package wr_streamers_wbgen2_pkg is
dbg_data_i => (others => '0'), dbg_data_i => (others => '0'),
dummy_dummy_i => (others => '0'), dummy_dummy_i => (others => '0'),
rx_stat14_rx_buf_overflow_cnt_i => (others => '0'), rx_stat14_rx_buf_overflow_cnt_i => (others => '0'),
rx_stat15_rx_late_frames_cnt_i => (others => '0'), rx_stat15_rx_late_frames_cnt_lsb_i => (others => '0'),
rx_stat16_rx_timeout_frames_cnt_i => (others => '0'), rx_stat16_rx_late_frames_cnt_msb_i => (others => '0'),
rx_stat17_rx_match_frames_cnt_i => (others => '0') rx_stat17_rx_timeout_frames_cnt_lsb_i => (others => '0'),
rx_stat18_rx_timeout_frames_cnt_msb_i => (others => '0'),
rx_stat19_rx_match_frames_cnt_lsb_i => (others => '0'),
rx_stat20_rx_match_frames_cnt_msb_i => (others => '0')
); );
-- Output registers (WB slave -> user design) -- Output registers (WB slave -> user design)
...@@ -219,9 +225,12 @@ tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_ ...@@ -219,9 +225,12 @@ tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_
tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i); tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i); tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
tmp.rx_stat14_rx_buf_overflow_cnt_i := f_x_to_zero(left.rx_stat14_rx_buf_overflow_cnt_i) or f_x_to_zero(right.rx_stat14_rx_buf_overflow_cnt_i); tmp.rx_stat14_rx_buf_overflow_cnt_i := f_x_to_zero(left.rx_stat14_rx_buf_overflow_cnt_i) or f_x_to_zero(right.rx_stat14_rx_buf_overflow_cnt_i);
tmp.rx_stat15_rx_late_frames_cnt_i := f_x_to_zero(left.rx_stat15_rx_late_frames_cnt_i) or f_x_to_zero(right.rx_stat15_rx_late_frames_cnt_i); tmp.rx_stat15_rx_late_frames_cnt_lsb_i := f_x_to_zero(left.rx_stat15_rx_late_frames_cnt_lsb_i) or f_x_to_zero(right.rx_stat15_rx_late_frames_cnt_lsb_i);
tmp.rx_stat16_rx_timeout_frames_cnt_i := f_x_to_zero(left.rx_stat16_rx_timeout_frames_cnt_i) or f_x_to_zero(right.rx_stat16_rx_timeout_frames_cnt_i); tmp.rx_stat16_rx_late_frames_cnt_msb_i := f_x_to_zero(left.rx_stat16_rx_late_frames_cnt_msb_i) or f_x_to_zero(right.rx_stat16_rx_late_frames_cnt_msb_i);
tmp.rx_stat17_rx_match_frames_cnt_i := f_x_to_zero(left.rx_stat17_rx_match_frames_cnt_i) or f_x_to_zero(right.rx_stat17_rx_match_frames_cnt_i); tmp.rx_stat17_rx_timeout_frames_cnt_lsb_i := f_x_to_zero(left.rx_stat17_rx_timeout_frames_cnt_lsb_i) or f_x_to_zero(right.rx_stat17_rx_timeout_frames_cnt_lsb_i);
tmp.rx_stat18_rx_timeout_frames_cnt_msb_i := f_x_to_zero(left.rx_stat18_rx_timeout_frames_cnt_msb_i) or f_x_to_zero(right.rx_stat18_rx_timeout_frames_cnt_msb_i);
tmp.rx_stat19_rx_match_frames_cnt_lsb_i := f_x_to_zero(left.rx_stat19_rx_match_frames_cnt_lsb_i) or f_x_to_zero(right.rx_stat19_rx_match_frames_cnt_lsb_i);
tmp.rx_stat20_rx_match_frames_cnt_msb_i := f_x_to_zero(left.rx_stat20_rx_match_frames_cnt_msb_i) or f_x_to_zero(right.rx_stat20_rx_match_frames_cnt_msb_i);
return tmp; return tmp;
end function; end function;
end package body; end package body;
modules/wr_streamers/xwr_streamers.vhd
View file @ 1bcdf807
...@@ -401,9 +401,13 @@ begin ...@@ -401,9 +401,13 @@ begin
to_wb.rx_stat12_rx_latency_acc_cnt_lsb_i <= latency_cnt (31 downto 0); to_wb.rx_stat12_rx_latency_acc_cnt_lsb_i <= latency_cnt (31 downto 0);
to_wb.rx_stat13_rx_latency_acc_cnt_msb_i(c_cw-32-1 downto 0) <= latency_cnt (c_cw-1 downto 32); to_wb.rx_stat13_rx_latency_acc_cnt_msb_i(c_cw-32-1 downto 0) <= latency_cnt (c_cw-1 downto 32);
to_wb.rx_stat15_rx_late_frames_cnt_i <= rx_stat_late_cnt(31 downto 0); -- new stuff added for fixed-latency
to_wb.rx_stat16_rx_timeout_frames_cnt_i <= rx_stat_timeout_cnt(31 downto 0); to_wb.rx_stat15_rx_late_frames_cnt_lsb_i <= rx_stat_late_cnt(31 downto 0);
to_wb.rx_stat17_rx_match_frames_cnt_i <= rx_stat_match_cnt(31 downto 0); to_wb.rx_stat16_rx_late_frames_cnt_msb_i (c_cw-32-1 downto 0) <= rx_stat_late_cnt(c_cw-1 downto 32);
to_wb.rx_stat17_rx_timeout_frames_cnt_lsb_i <= rx_stat_timeout_cnt(31 downto 0);
to_wb.rx_stat18_rx_timeout_frames_cnt_msb_i (c_cw-32-1 downto 0) <= rx_stat_timeout_cnt(c_cw-1 downto 32);
to_wb.rx_stat19_rx_match_frames_cnt_lsb_i <= rx_stat_match_cnt(31 downto 0);
to_wb.rx_stat20_rx_match_frames_cnt_msb_i(c_cw-32-1 downto 0) <= rx_stat_match_cnt(c_cw-1 downto 32);
rx_data_o <= rx_data; rx_data_o <= rx_data;
......
sim/wr_streamers_wb.svh
View file @ 1bcdf807
...@@ -142,14 +142,23 @@ ...@@ -142,14 +142,23 @@
`define WR_STREAMERS_RX_STAT14_RX_BUF_OVERFLOW_CNT_OFFSET 0 `define WR_STREAMERS_RX_STAT14_RX_BUF_OVERFLOW_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT14_RX_BUF_OVERFLOW_CNT 32'hffffffff `define WR_STREAMERS_RX_STAT14_RX_BUF_OVERFLOW_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT15 8'h90 `define ADDR_WR_STREAMERS_RX_STAT15 8'h90
`define WR_STREAMERS_RX_STAT15_RX_LATE_FRAMES_CNT_OFFSET 0 `define WR_STREAMERS_RX_STAT15_RX_LATE_FRAMES_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT15_RX_LATE_FRAMES_CNT 32'hffffffff `define WR_STREAMERS_RX_STAT15_RX_LATE_FRAMES_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT16 8'h94 `define ADDR_WR_STREAMERS_RX_STAT16 8'h94
`define WR_STREAMERS_RX_STAT16_RX_TIMEOUT_FRAMES_CNT_OFFSET 0 `define WR_STREAMERS_RX_STAT16_RX_LATE_FRAMES_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT16_RX_TIMEOUT_FRAMES_CNT 32'hffffffff `define WR_STREAMERS_RX_STAT16_RX_LATE_FRAMES_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT17 8'h98 `define ADDR_WR_STREAMERS_RX_STAT17 8'h98
`define WR_STREAMERS_RX_STAT17_RX_MATCH_FRAMES_CNT_OFFSET 0 `define WR_STREAMERS_RX_STAT17_RX_TIMEOUT_FRAMES_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT17_RX_MATCH_FRAMES_CNT 32'hffffffff `define WR_STREAMERS_RX_STAT17_RX_TIMEOUT_FRAMES_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG6 8'h9c `define ADDR_WR_STREAMERS_RX_STAT18 8'h9c
`define WR_STREAMERS_RX_STAT18_RX_TIMEOUT_FRAMES_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT18_RX_TIMEOUT_FRAMES_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT19 8'ha0
`define WR_STREAMERS_RX_STAT19_RX_MATCH_FRAMES_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT19_RX_MATCH_FRAMES_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT20 8'ha4
`define WR_STREAMERS_RX_STAT20_RX_MATCH_FRAMES_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT20_RX_MATCH_FRAMES_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG6 8'ha8
`define WR_STREAMERS_RX_CFG6_RX_FIXED_LATENCY_TIMEOUT_OFFSET 0 `define WR_STREAMERS_RX_CFG6_RX_FIXED_LATENCY_TIMEOUT_OFFSET 0
`define WR_STREAMERS_RX_CFG6_RX_FIXED_LATENCY_TIMEOUT 32'h0fffffff `define WR_STREAMERS_RX_CFG6_RX_FIXED_LATENCY_TIMEOUT 32'h0fffffff
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