Commit 1a90b670 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk

sim/8b10b_encoder: fix logic signal aliasing with a port

parent 85b2022c
......@@ -210,7 +210,6 @@ task automatic f_8b10b_decode ( input [9:0] datain, input dispin, output [8:0] d
logic fghjp31 = ( (!feqg) & hi & ji) |
( !heqj & fi & gi) ;
logic dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ;
logic ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) |
(p13 & !ei & ii & gi & hi & ji) |
......@@ -243,6 +242,8 @@ task automatic f_8b10b_decode ( input [9:0] datain, input dispin, output [8:0] d
logic disp4p = fghjp31 ;
logic disp4n = fghjp13 ;
dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji);
code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) |
(p13 & !ei & !ii) | (p31 & ei & ii) |
(ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) |
......
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