Commit 0d636aa5 authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: add auto-generated SDB meta info to SPEC and SVEC ref designs

parent 676cf521
...@@ -20,3 +20,12 @@ modules = { ...@@ -20,3 +20,12 @@ modules = {
"../../top/spec_ref_design/", "../../top/spec_ref_design/",
], ],
} }
fetchto="../../ip_cores"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
#xilinx::project set "Register Balancing" "Yes"
#xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
...@@ -20,3 +20,12 @@ modules = { ...@@ -20,3 +20,12 @@ modules = {
"../../top/svec_ref_design/", "../../top/svec_ref_design/",
], ],
} }
fetchto="../../ip_cores"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
#xilinx::project set "Register Balancing" "Yes"
#xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch> -- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT) -- Company : CERN (BE-CO-HT)
-- Created : 2017-02-20 -- Created : 2017-02-20
-- Last update: 2018-03-20 -- Last update: 2018-11-30
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SPEC. -- Description: Top-level file for the WRPC reference design on the SPEC.
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
-- SPEC: http://www.ohwr.org/projects/spec/ -- SPEC: http://www.ohwr.org/projects/spec/
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN -- Copyright (c) 2017-2018 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- --
...@@ -53,20 +53,21 @@ use ieee.numeric_std.all; ...@@ -53,20 +53,21 @@ use ieee.numeric_std.all;
library work; library work;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.gn4124_core_pkg.all;
use work.wr_board_pkg.all; use work.wr_board_pkg.all;
use work.wr_spec_pkg.all; use work.wr_spec_pkg.all;
use work.gn4124_core_pkg.all; use work.synthesis_descriptor.all;
library unisim; library unisim;
use unisim.vcomponents.all; use unisim.vcomponents.all;
entity spec_wr_ref_top is entity spec_wr_ref_top is
generic ( generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram"; g_DPRAM_INITF : string := "../../bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench. -- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations. -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0 g_SIMULATION : integer := 0
); );
port ( port (
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -234,17 +235,23 @@ architecture top of spec_wr_ref_top is ...@@ -234,17 +235,23 @@ architecture top of spec_wr_ref_top is
-- Primary Wishbone slave(s) offsets -- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_WRC : integer := 0; constant c_WB_SLAVE_WRC : integer := 0;
-- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES + 1;
-- sdb header address on primary crossbar -- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00040000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr) -- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address -- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge := constant c_WRC_BRIDGE_SDB : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000"); f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Primary wishbone crossbar layout -- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := ( constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000")); c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_WRC_BRIDGE_SDB, x"00040000"),
c_SDB_GIT_REPO_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL),
c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO));
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Signals -- Signals
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch> -- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT) -- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16 -- Created : 2017-02-16
-- Last update: 2017-03-10 -- Last update: 2018-11-30
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SVEC. -- Description: Top-level file for the WRPC reference design on the SVEC.
...@@ -21,10 +21,10 @@ ...@@ -21,10 +21,10 @@
-- * provide a reference top HDL file showing how the WRPC can be instantiated -- * provide a reference top HDL file showing how the WRPC can be instantiated
-- in HDL projects. -- in HDL projects.
-- --
-- VFC-HD: http://www.ohwr.org/projects/svec/ -- SVEC: http://www.ohwr.org/projects/svec/
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN -- Copyright (c) 2017-2018 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- --
...@@ -56,17 +56,18 @@ use work.wishbone_pkg.all; ...@@ -56,17 +56,18 @@ use work.wishbone_pkg.all;
use work.vme64x_pkg.all; use work.vme64x_pkg.all;
use work.wr_board_pkg.all; use work.wr_board_pkg.all;
use work.wr_svec_pkg.all; use work.wr_svec_pkg.all;
use work.synthesis_descriptor.all;
library unisim; library unisim;
use unisim.vcomponents.all; use unisim.vcomponents.all;
entity svec_wr_ref_top is entity svec_wr_ref_top is
generic ( generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram"; g_DPRAM_INITF : string := "../../bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench. -- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations. -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0 g_SIMULATION : integer := 0
); );
port ( port (
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -208,17 +209,23 @@ architecture top of svec_wr_ref_top is ...@@ -208,17 +209,23 @@ architecture top of svec_wr_ref_top is
-- Primary Wishbone slave(s) offsets -- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_WRC : integer := 0; constant c_WB_SLAVE_WRC : integer := 0;
-- sdb header address on primary crossbar -- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES + 1;
-- SDB header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr) -- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address -- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge := constant c_WRC_BRIDGE_SDB : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000"); f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Primary wishbone crossbar layout -- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := ( constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000")); c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_WRC_BRIDGE_SDB, x"00040000"),
c_SDB_GIT_REPO_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL),
c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO));
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Signals -- Signals
......
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