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White Rabbit core collection
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White Rabbit core collection
Commits
0a312869
Commit
0a312869
authored
May 12, 2020
by
Pascal Bos
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cleaned up code, removed deprecated stuff.
parent
8bde107b
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2 changed files
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68 additions
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283 deletions
+68
-283
wr_spec7_pkg.vhd
board/spec7/wr_spec7_pkg.vhd
+68
-162
spec7_write_top.vhd
top/spec7_write_design/spec7_write_top.vhd
+0
-121
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board/spec7/wr_spec7_pkg.vhd
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0a312869
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top/spec7_write_design/spec7_write_top.vhd
View file @
0a312869
...
...
@@ -323,75 +323,6 @@ architecture top of spec7_write_top is
);
end
component
gen_10mhz
;
component
processing_system_pcie_wrapper
is
port
(
DDR_addr
:
inout
STD_LOGIC_VECTOR
(
14
downto
0
);
DDR_ba
:
inout
STD_LOGIC_VECTOR
(
2
downto
0
);
DDR_cas_n
:
inout
STD_LOGIC
;
DDR_ck_n
:
inout
STD_LOGIC
;
DDR_ck_p
:
inout
STD_LOGIC
;
DDR_cke
:
inout
STD_LOGIC
;
DDR_cs_n
:
inout
STD_LOGIC
;
DDR_dm
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR_dq
:
inout
STD_LOGIC_VECTOR
(
31
downto
0
);
DDR_dqs_n
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR_dqs_p
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR_odt
:
inout
STD_LOGIC
;
DDR_ras_n
:
inout
STD_LOGIC
;
DDR_reset_n
:
inout
STD_LOGIC
;
DDR_we_n
:
inout
STD_LOGIC
;
FIXED_IO_ddr_vrn
:
inout
STD_LOGIC
;
FIXED_IO_ddr_vrp
:
inout
STD_LOGIC
;
FIXED_IO_mio
:
inout
STD_LOGIC_VECTOR
(
53
downto
0
);
FIXED_IO_ps_clk
:
inout
STD_LOGIC
;
FIXED_IO_ps_porb
:
inout
STD_LOGIC
;
FIXED_IO_ps_srstb
:
inout
STD_LOGIC
;
gpio_rtl_0_tri_o
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_araddr
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_arburst
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_arcache
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_arlen
:
out
STD_LOGIC_VECTOR
(
7
downto
0
);
M00_AXI_0_arlock
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
M00_AXI_0_arprot
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_arqos
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_arready
:
in
STD_LOGIC
;
M00_AXI_0_arsize
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_arvalid
:
out
STD_LOGIC
;
M00_AXI_0_awaddr
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_awburst
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_awcache
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_awlen
:
out
STD_LOGIC_VECTOR
(
7
downto
0
);
M00_AXI_0_awlock
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
M00_AXI_0_awprot
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_awqos
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_awready
:
in
STD_LOGIC
;
M00_AXI_0_awsize
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
M00_AXI_0_awvalid
:
out
STD_LOGIC
;
M00_AXI_0_bready
:
out
STD_LOGIC
;
M00_AXI_0_bresp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_bvalid
:
in
STD_LOGIC
;
M00_AXI_0_rdata
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_rlast
:
in
STD_LOGIC
;
M00_AXI_0_rready
:
out
STD_LOGIC
;
M00_AXI_0_rresp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
M00_AXI_0_rvalid
:
in
STD_LOGIC
;
M00_AXI_0_wdata
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
M00_AXI_0_wlast
:
out
STD_LOGIC
;
M00_AXI_0_wready
:
in
STD_LOGIC
;
M00_AXI_0_wstrb
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
M00_AXI_0_wvalid
:
out
STD_LOGIC
;
aclk1_0
:
in
STD_LOGIC
;
pcie_clk
:
in
STD_LOGIC
;
pcie_mgt_0_rxn
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_mgt_0_rxp
:
in
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_mgt_0_txn
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_mgt_0_txp
:
out
STD_LOGIC_VECTOR
(
1
downto
0
);
pcie_rst_n
:
in
STD_LOGIC
;
user_lnk_up_0
:
out
STD_LOGIC
;
usr_irq_ack_0
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
usr_irq_req_0
:
in
STD_LOGIC_VECTOR
(
0
to
0
)
);
end
component
processing_system_pcie_wrapper
;
begin
-- architecture top
-- Never trigger PS_POR or PROGRAM_B
...
...
@@ -407,58 +338,6 @@ pci_clk_buf : IBUFDS_GTE2
ODIV2
=>
open
,
CEB
=>
'0'
);
--Pcie: Pcie_wrapper
-- port map (
-- M00_AXI_0_araddr => m_axil_o.araddr,
-- M00_AXI_0_arburst => open,
-- M00_AXI_0_arcache => open,
-- M00_AXI_0_arlen => open,
-- M00_AXI_0_arlock => open,
-- M00_AXI_0_arprot => open,
-- M00_AXI_0_arqos => open,
-- M00_AXI_0_arready => m_axil_i.arready,
-- M00_AXI_0_arsize => open,
-- M00_AXI_0_arvalid => m_axil_o.arvalid,
-- M00_AXI_0_awaddr => m_axil_o.awaddr,
-- M00_AXI_0_awburst => open,
-- M00_AXI_0_awcache => open,
-- M00_AXI_0_awlen => open,
-- M00_AXI_0_awlock => open,
-- M00_AXI_0_awprot => open,
-- M00_AXI_0_awqos => open,
-- M00_AXI_0_awready => m_axil_i.awready,
-- M00_AXI_0_awsize => open,
-- M00_AXI_0_awvalid => m_axil_o.awvalid,
-- M00_AXI_0_bready => m_axil_o.bready,
-- M00_AXI_0_bresp => m_axil_i.bresp,
-- M00_AXI_0_bvalid => m_axil_i.bvalid,
-- M00_AXI_0_rdata => m_axil_i.rdata,
-- M00_AXI_0_rlast => m_axil_i.rlast,
-- M00_AXI_0_rready => m_axil_o.rready,
-- M00_AXI_0_rresp => m_axil_i.rresp,
-- M00_AXI_0_rvalid => m_axil_i.rvalid,
-- M00_AXI_0_wdata => m_axil_o.wdata,
-- M00_AXI_0_wlast => m_axil_o.wlast,
-- M00_AXI_0_wready => m_axil_i.wready,
-- M00_AXI_0_wstrb => m_axil_o.wstrb,
-- M00_AXI_0_wvalid => m_axil_o.wvalid,
---- M_AXIS_H2C_0_0_tdata => axis_icap.data,
---- M_AXIS_H2C_0_0_tkeep => axis_icap.keep,
---- M_AXIS_H2C_0_0_tlast => axis_icap.last,
---- M_AXIS_H2C_0_0_tready => axis_icap.ready,
---- M_AXIS_H2C_0_0_tvalid => axis_icap.valid,
-- aclk1_0 => clk_sys_62m5,
---- axi_aclk => axi_clk,
-- pcie_mgt_0_rxn => rxn,
-- pcie_mgt_0_rxp => rxp,
-- pcie_mgt_0_txn => txn,
-- pcie_mgt_0_txp => txp,
-- pcie_clk => pci_clk,
-- pcie_rst_n => perst_n,
-- user_lnk_up_0 => open,
-- usr_irq_ack_0 => open,
-- usr_irq_req_0 => "0"
-- );
AXI2WB
:
xwb_axi4lite_bridge
port
map
(
...
...
Write
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